5962-9800102KZA [AVAGO]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, HERMETIC SEALED, SMD, DIP-8;
| 型号： | 5962-9800102KZA |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, HERMETIC SEALED, SMD, DIP-8 输出元件 光电 |
| 文件： | 总12页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hermetically Sealed,High Speed,High CMR,
Logic Gate Optocouplers
DataSheet
6N134,* 81028, HCPL-563X, HCPL-663X, HCPL-565X, 5962-98001,
HCPL-268K, HCPL-665X, 5962-90855, HCPL-560X
*See matrix for available extensions.
Features
Description
• Dual marked with device part number and DSCC
drawing number
• Manufactured and tested on a MIL-PRF-38534
Certified Line
These units are single, dual and quad channel,
hermetically sealed optocouplers. The products are
capable of operation and storage over the full military
temperature range and can be purchased as either
standard product or with full MIL-PRF-38534 Class Level
H or K testing or from the appropriate DSCC Drawing. All
devicesare manufactured and tested on aMIL-PRF-38534
certified line and are included in the DSCC Qualified
Manufacturers List QML-38534 for Hybrid Microcircuits.
Quad channel devices are available by special order in
the 16 pin DIP through hole packages.
• QML-38534, Class H and K
• Five hermetically sealed package configurations
• Performance guaranteed over full military
temperature range: -55°C to +125°C
• High speed: 10 M Bit/s
• CMR: > 10,000 V/µs typical
• 1500 Vdc withstand test voltage
• 2500 Vdc withstand test voltage for HCPL-565X
• High radiation immunity
• 6N137, HCPL-2601, HCPL-2630/-31 function
compatibility
• Reliability data
Truth Table (Positive Logic)
Multichannel Devices
Input
Output
• TTL circuit compatibility
On (H)
Off (L)
L
H
Applications
• Military and space
• High reliability systems
• Transportation, medical, and life critical systems
• Line receiver
• Voltage level shifting
Single Channel DIP
Input
Enable
Output
On (H)
Off (L)
On (H)
Off (L)
H
H
L
L
L
• Isolated input line receiver
• Isolated output line driver
• Logic ground isolation
• Harsh industrial environments
• Isolation for computer, communication, and test
equipment systems
H
H
H
Functional Diagram
Multiple channel devices available
V
CC
V
E
V
OUT
GND
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage
and/or degradation which may be induced by ESD.
Each channelcontainsaGaAsPlight emitting diode which
is optically coupled to an integrated high speed photon
Because the same electrical die (emitters and detectors)
are used foreach channelofeach device listed in thisdata
detector. The output of the detector is an open collector sheet, absolute maximum ratings, recommended
Schottky clamped transistor. Internal shields provide a operating conditions, electrical specifications, and
guaranteed common mode transient immunity performance characteristics shown in the figures are
specification of 1000 V/µs. For Isolation Voltage
applications requiring up to 2500 Vdc, the HCPL-5650
family is also available. Package styles for these parts are
identical for all parts. Occasional exceptions exist due to
package variations and limitations, and are as noted.
Additionally, the same package assembly processes and
8 and 16 pin DIP through hole (case outlines P and E materials are used in all devices. These similarities give
respectively), and 16 pin surface mount DIP flat pack justification forthe use ofdata obtained from one part to
(case outline F),leadlessceramicchip carrier(case outline
2). Devices may be purchased with a variety of lead bend
and plating options.See Selection Guide Table fordetails.
Standard Microcircuit Drawing (SMD) parts are available
for each package and lead style.
represent other parts’ performance for reliability and
certain limited radiation test results.
SelectionGuide–PackageStylesandLeadConfigurationOptions
Package
Lead Style
Channels
16 Pin DIP
8 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
20 Pad LCCC
Surface Mount
2
Through Hole Through Hole Through Hole Through Hole Unformed Leads
2
1
2
2
4
Common Channel
Wiring
V , GND
CC
None
V , GND
CC
V , GND
CC
V , GND
CC
None
Withstand Test Voltage
Avago Part # & Options
Commercial
1500 Vdc
1500 Vdc
1500 Vdc
2500 Vdc
1500 Vdc
1500 Vdc
6N134[1]
HCPL-5600
HCPL-5601
HCPL-560K
Gold Plate
HCPL-5630
HCPL-5631
HCPL-563K
Gold Plate
HCPL-5650
HCPL-5651
HCPL-6650
HCPL-6651
HCPL-665K
Gold Plate
HCPL-6630
HCPL-6631
HCPL-663K
Solder Pads*
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped*
6N134/883B
HCPL-268K
Gold Plate
Gold Plate
Option #200
Option #100
Option #300
Option #200
Option #100
Option #300
Option #200
Option #100
Option #300
Option #200
Butt Cut/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
None
5962-
None
None
None
None
8102801EX
8102801EC
8102801EA
8102801UC
8102801UA
8102801TA
9085501HPX
9085501HPC
9085501HPA
9085501HYC
9085501HYA
9085501HXA
8102802PX
8102802PC
8102802PA
8102802YC
8102802YA
8102802ZA
8102805PX
8102805PC
8102805PA
8102804FX
8102804FC
81028032X
Solder Dipped*
81028032A
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
5962-
5962-
5962-
5962-
5962-
9800101KEX 9085501KPX
9800101KEC 9085501KPC
9800101KEA 9085501KPA
9800101KUC 9085501KYC
9800101KUA 9085501KYA
9800101KTA 9085501KXA
9800102KPX
9800102KPC
9800102KPA
9800102KYC
9800102KYA
9800102KZA
9800104KFX
9800104KFC
9800103K2X
Solder Dipped*
9800103K2A
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
*Solder contains lead.
Note:
1. JEDEC registered part.
2
Functional Diagrams
16 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
Unformed Leads
4 Channels
20 Pad LCCC
Surface Mount
2 Channels
Through Hole
2 Channels
Through Hole
1 Channel
Through Hole
2 Channels
15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
V
1
2
3
4
8
7
6
5
1
V
8
CC
CC
V
V
CC
CC
19
20
13
12
V
O2
V
V
O1
O2
V
V
V
V
V
E
O1
O2
O3
O1
2
3
4
7
6
5
GND
2
V
OUT
V
CC1
2
3
10
V
O1
V
O2
V
O4
GND
GND
1
GND
GND
GND
7
8
Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic chip carrier)
package has isolated channels with separate VCC and ground connections. All diagrams are “top view.”
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Leaded Device Marking
Leadless Device Marking
Avago LOGO
Avago P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
* 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
Avago LOGO
Avago P/N
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
* XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Avago CAGE CODE*
COUNTRY OF MFR.
Avago CAGE CODE*
COUNTRY OF MFR.
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
3
Outline Drawings (continued)
8 Pin DIP Through Hole, 1 and 2 Channels
8 Pin DIP Through Hole, 2 Channels
2500 Vdc Withstand Test Voltage
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
5.08 (0.200)
MAX.
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
16 Pin Flat Pack, 4 Channels
20 Terminal LCCC Surface Mount, 2 Channels
7.24 (0.285)
6.99 (0.275)
8.70 (0.342)
9.10 (0.358)
2.29 (0.090)
MAX.
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
1.02 (0.040) (3 PLCS)
2.03 (0.080)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
11.13 (0.438)
10.72 (0.422)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
1.27 (0.050)
REF.
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
0.46 (0.018)
0.36 (0.014)
1.52 (0.060)
2.03 (0.080)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.31 (0.012)
0.23 (0.009)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
5.23
(0.206)
MAX.
0.89 (0.035)
0.69 (0.027)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 and 16 pin DIP. DSCC Drawing part numbers contain provisions for
lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
MIN.
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Solder contains lead.
5
Absolute Maximum Ratings
No derating required up to +125°C.
Parameter
Symbol
Min.
-65
Max.
Units
°C
Storage Temperature
T
S
+150
Operating Temperature
TA
TC
-55
+125
°C
Case Temperature
+170
°C
Junction Temperature
T
J
+175
°C
Lead Solder Temperature
260 for 10 sec
°C
Peak Forward Input Current (each channel, ≤1 ms duration)
Average Input Forward Current (each channel)
Input Power Dissipation (each channel)
Reverse Input Voltage (each channel
Supply Voltage (1 minute maximum)
Output Current (each channel)
Output Voltage (each channel)
Output Power Dissipation (each channel)
Package Power Dissipation (each channel)
IF(PEAK)
IF(AVG)
40
20
35
5
mA
mA
mW
V
V
R
V
CC
7.0
25
7*
40
200
V
IO
mA
V
V
O
PO
PD
mW
mW
*Selection for higher output voltages up to 20 V is available.
Single Channel Product Only
Enable Input Voltage
V
E
5.5
V
8 Pin Ceramic DIP Single Channel Schematic
Note enable pin 7. An external 0.01 µF to 0.1 µF bypass
capacitor must be connected between V and ground
CC
for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5600/01/0K
(▲), Class 1
6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51, HCPL-6630/31/3K
and HCPL-6650/51/5K
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
IFL
Min.
0
Max.
250
20
Units
µA
Input Current, Low Level, Each Channel
Input Current, High Level, Each Channel*
Supply Voltage, Output
IFH
10
mA
V
V
CC
4.5
5.5
6
Fan Out (TTL Load) Each Channel
N
*Meets or exceeds DSCC SMD and JEDEC requirements.
6
Recommended Operating Conditions (cont’d.)
Single Channel Product Only[10]
Parameter
Symbol
Min.
2.0
0
Max.
Units
V
V
High Level Enable Voltage
Low Level Enable Voltage
V
V
EH
CC
V
EL
0.8
ElectricalCharacteristics (T = -55°C to +125°C, unless otherwise specified)
A
[13]
Limits
Group A
Parameter
Symbol Test Conditions
Subgroups Min. Typ.** Max. Units Fig. Note
High Level
Output Current
IOH*
V = 5.5 V, V = 5.5 V,
IF = 250 µA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
20
250 µA
1
1
CC
O
Low Level
Output Voltage
V *
OL
V = 5.5 V, IF = 10 mA,
0.3
0.6
V
2
1, 9
1
CC
IOL (Sinking) = 10 mA
Current Transfer
Ratio
hF CTR
V = 0.6 V, IF = 10 mA,
100
%
O
V = 5.5 V
CC
Single
Channel
ICCH*
V = 5.5 V, IF = 0 mA
CC
9
14
28
42
18
36
50
mA
mA
mA
mA
mA
mA
1
Supply
Current
Dual
Channel
V = 5.5 V,
18
25
13
26
33
6
CC
IF1 = IF2 = 0 mA
Quad
Channel
V = 5.5 V, IF1 = IF2 =
CC
IF3 = IF4 = 0 mA
Logic
Low
Single
Channel
ICCL*
V = 5.5 V,
1, 2, 3
1
6
CC
IF = 20 mA
Supply
Current
Dual
Channel
V = 5.5 V,
CC
IF1 = IF2 = 20 mA
Quad
V = 5.5 V, IF1 = IF2 =
CC
Channel
IF3 = IF4 = 20 mA
Input Forward
Voltage
V *
F
IF = 20 mA
1, 2, 3
1, 2
1.5
1.9
V
V
3
3
1, 15
1, 16
1.55
1.75
1.85
3
Input Reverse
Breakdown
Voltage
BV *
IR = 10 µA
1, 2, 3
5
V
1
R
V = 1500
Input-Output
Leakage Current
I *
RH ≤ 65%
1
1.0
µA
2, 8, 17
18
I-O
I-O
Vdc
T = 25°C
A
V = 2500
I-O
t = 5 s
1
4
1.0
4.0
µA
Vdc
Capacitance
Between Input/
Output
C
I-O
f = 1 MHz, T = 25°C
1.0
pF
1, 3,
14
C
*Identified test parameters for JEDEC registered parts.
**All typical values are at VCC = 5 V, T = 25°C.
A
7
Electrical Characteristics, (cont’d) T = -55°C to +125°C unless otherwise specified
A
Limits
Group A[13]
Parameter
Symbol Test Conditions
Subgroups Min. Typ.** Max. Units Fig. Note
Propagation Delay
Time to High
Output Level
V = 5 V, RL =
510 Ω, CL = 50
pF, IF = 13 mA
tPLH
*
9
60
100 ns
140
4, 5, 1, 5
6
CC
10, 11
9
tPHL*
55
100 ns
Propagation Delay
Time to Low
Output Level
10, 11
120
Output Rise Time
Output Fall Time
tLH
RL = 510 Ω,
9, 10, 11
35
35
90
40
ns
1
CL = 50 pF, IF =
tHL
13 mA
Common Mode
Transient
Immunity at
High Output
Level
|CMH|
V
CM = 50 V(PEAK),
9, 10, 11
9, 10, 11
1000 >10000
V/µs
7
7
1, 7,
14
V = 5 V,
CC
V (min.) = 2 V,
O
RL = 510 Ω,
IF = 0 mA
Common Mode
Transient
|CML|
VCM = 50 V(PEAK),
1000 >10000
V/µs
1, 7,
14
V = 5 V,
CC
Immunity at
Low Output
Level
V (max.) = 0.8 V,
RL = 510 Ω,
IF = 10 mA
O
Single Channel Product Only
Low Level
Enable Current
IEL
V = 5.5 V,
V = 0.5 V
E
1, 2, 3
1, 2, 3
1, 2, 3
-1.45
-2.0 mA
V
CC
High Level
Enable Voltage
V
EH
2.0
10
Low Level
V
EL
0.8
V
Enable Voltage
*Identified test parameters for JEDEC registered part.
**All typical values are at VCC = 5 V, T = 25°C.
A
Typical Characteristics, T = 25°C, V = 5 V
A
CC
Parameter
Sym.
Typ.
60
Units
pF
Test Conditions
Fig.
Note
Input Capacitance
C
IN
V = 0 V, f = 1 MHz
1
1
F
Input Diode Temperature
Coefficient
∆V
-1.5
mV/°C
IF = 20 mA
F
∆T
A
Resistance (Input-Output)
R
I-O
1012
Ω
V = 500 V
I-O
2
Single Channel Product Only
Propagation Delay Time of
Enable from V to V
tELH
tEHL
35
35
ns
ns
RL = 510 Ω, CL = 50 pF
8, 9
1, 11
1, 12
IF = 13 mA, V = 3 V,
EH
EL
EH
V = 0 V
EL
Propagation Delay Time of
Enable from V to V
EL
EH
Dual and Quad Channel Product Only
Input-Input
Leakage Current
I
I-I
0.5
nA
Relative Humidity ≤ 65%
V = 500 V, t = 5 s
I-I
4
Resistance (Input-Input)
Capacitance (Input-Input)
R
1012
0.55
Ω
V = 500 V
4
4
I-I
I-I
C
I-I
pF
f = 1 MHz
8
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all output
leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge
of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point
on the trailing edge of the output pulse.
6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single channel
parameter limits for each channel.
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(V < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
O
high state (V > 2.0 V).
O
8. This is a momentary withstand test, not an operating condition.
9. It is essential that a bypass capacitor (0.01 to 0.1 µF, ceramic) be connected from VCC to ground. Total lead length between both ends
of this external capacitor and the isolator connections should not exceed 20 mm.
10. No external pull up is required for a high logic state on the enable input.
11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point
on the trailing edge of the output pulse.
12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point
on the leading edge of the output pulse.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits
specified for all lots not specifically tested.
15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.
18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.
Figure 1. High Level Output Current vs.
Temperature.
Figure 2. Input-Output Characteristics.
Figure 3. Input Diode Forward
Characteristic.
9
D.U.T.
5 V
V
CC
PULSE
GENERATOR
R
L
I
F
V
O
Z
t
= 50 Ω
= 5 ns
O
H
0.01 µF
BYPASS
V
O
C *
L
INPUT
MONITORING
NODE
GND
Rm
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
Figure 5. Propagation Delay, t
and
PHL
t
vs. Pulse Input Current, I .
PLH
FH
Figure 4. Test Circuit for t
and t
.*
PLH
PHL
D.U.T.
+5 V
B
V
CC
510 Ω
I
I
A
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
GND
–
V
FF
V
CM
+
PULSE GEN.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Test Circuit for Common Mode Transient Immunity and
Typical Waveforms.
10
PULSE
GENERATOR
OUTPUT V
MONITORING
NODE
E
Z
= 50 Ω
= 5 ns
O
r
t
+5 V
D.U.T.
V
CC
R
L
V
E
I
= 13 mA
F
V
OUT
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
C *
L
GND
* C INCLUDES PROBE AND
L
STRAY WIRING CAPACITANCE.
Figure 9. Enable Propagation Delay vs.
Temperature.
Figure 8. Test Circuit for t
and t
.
ELH
EHL
V
CC
+5.5 V
V
D.U.T.*
OC
+5.5 V
V
CC
(EACH INPUT)
0.01 µF
+
–
V
200 Ω
200 Ω
(EACH OUTPUT)
IN
5.3 V
(EACH OUTPUT)
GND
CONDITIONS: I = 20 mA
F
I
= 25 mA
O
T
= +125 °C
A
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
11
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Avago’s Hi-Rel Optocouplers are in compliance with
MIL-PRF-38534 Classes H and K. Class H and Class K
devices are also in compliance with DSCC drawings
81028, 5962-90855 and 5962-98001.
Testing consists of 100% screening and quality conform-
ance inspection to MIL-PRF-38534.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5968-4743E
5968-9407E June 19, 2007
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