ACPL-563KLOPTION-100 [AVAGO]
Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 10MBps, HERMETIC SEALED, DIP-8;
| 型号： | ACPL-563KLOPTION-100 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 10MBps, HERMETIC SEALED, DIP-8 |
| 文件： | 总11页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-267XL, ACPL-268KL, ACPL-560XL,
ACPL-563XL, 5962-08242*
Hermetically Sealed, 3.3V High Speed, High CMR,
Logic Gate Optocouplers
Data Sheet
*SeeꢀSelectionꢀGuideꢀforꢀfullꢀmatrixꢀofꢀpartꢀnumbers.
Description
Features
Theseꢀ unitsꢀ areꢀ singleꢀ andꢀ dualꢀ channel,ꢀ hermeticallyꢀ •ꢀ Lowꢀpowerꢀconsumption
sealedꢀoptocouplers.ꢀTheꢀproductsꢀareꢀcapableꢀofꢀopera-
tionꢀandꢀstorageꢀoverꢀtheꢀfullꢀmilitaryꢀtemperatureꢀrangeꢀ
andꢀ canꢀ beꢀ purchasedꢀ asꢀ eitherꢀ standardꢀ commercialꢀ
productꢀ orꢀ withꢀ fullꢀ MIL-PRF-38534ꢀ Classꢀ Levelꢀ Hꢀ orꢀ Kꢀ
•ꢀ 3.3Vꢀsupplyꢀvoltages
•ꢀ DualꢀmarkedꢀwithꢀdeviceꢀpartꢀnumberꢀandꢀDSCCꢀ
drawingꢀnumber
testingꢀorꢀfromꢀDSCCꢀDrawingꢀ5962-08242.ꢀAllꢀdevicesꢀ •ꢀ ManufacturedꢀandꢀtestedꢀonꢀaꢀMIL-PRF-38534ꢀ
areꢀmanufacturedꢀandꢀtestedꢀonꢀaꢀMIL-PRF-38534ꢀcerti-
fiedꢀlineꢀandꢀareꢀincludedꢀinꢀtheꢀDSCCꢀQualifiedꢀManu-
facturersꢀListꢀQML-38534ꢀforꢀHybridꢀMicrocircuits.ꢀ
CertifiedꢀLine
•ꢀ QML-38534,ꢀClassꢀHꢀandꢀK
•ꢀ Threeꢀhermeticallyꢀsealedꢀpackageꢀconfigurations
Truth Table (PositiveꢀLogic)
Multichannel Devices
•ꢀ Performanceꢀguaranteedꢀoverꢀfullꢀmilitaryꢀ
temperatureꢀrange:ꢀ-55°Cꢀtoꢀ+125°Cꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
Input
Onꢀ(H)
Offꢀ(L)
Output
•ꢀ Highꢀspeed:ꢀ10ꢀMbdꢀtypical
L
•ꢀ CMR:ꢀ>ꢀ10,000ꢀV/µsꢀtypical
H
•ꢀ 1500ꢀVdcꢀwithstandꢀtestꢀvoltage
•ꢀ TTLꢀcircuitꢀcompatibility
Single Channel DIP
•ꢀ HCPL-260L/060L/263L/063Lꢀfunctionꢀcompatibility
Input
Onꢀ(H)
Offꢀ(L)
Onꢀ(H)
Offꢀ(L)
Enable
Output
H
H
L
L
Applications
H
H
H
•ꢀ Militaryꢀandꢀaerospace
•ꢀ Highꢀreliabilityꢀsystems
•ꢀ Transportation,ꢀmedical,ꢀandꢀlifeꢀcriticalꢀsystems
•ꢀ Lineꢀreceiver
L
Functional Diagram
Multipleꢀchannelꢀdevicesꢀavailable
•ꢀ Voltageꢀlevelꢀshifting
•ꢀ Isolatedꢀinputꢀlineꢀreceiver
•ꢀ Isolatedꢀoutputꢀlineꢀdriver
•ꢀ Logicꢀgroundꢀisolation
•ꢀ Harshꢀindustrialꢀenvironments
V
CC
V
E
V
OUT
•ꢀ Isolationꢀforꢀcomputer,ꢀcommunication,ꢀandꢀtestꢀ
equipmentꢀsystems
GND
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Eachꢀ channelꢀ containsꢀ aꢀ GaAsPꢀ lightꢀ emittingꢀ diodeꢀ Becauseꢀtheꢀsameꢀelectricalꢀdieꢀ(emittersꢀandꢀdetectors)ꢀ
whichꢀisꢀopticallyꢀcoupledꢀtoꢀanꢀintegratedꢀhighꢀspeedꢀ areꢀusedꢀforꢀeachꢀchannelꢀofꢀeachꢀdeviceꢀlistedꢀinꢀthisꢀ
photonꢀdetector.ꢀTheꢀoutputꢀofꢀtheꢀdetectorꢀisꢀanꢀopenꢀ dataꢀ sheet,ꢀ absoluteꢀ maximumꢀ ratings,ꢀ recommendedꢀ
collectorꢀ Schottkyꢀ clampedꢀ transistor.ꢀ Internalꢀ shieldsꢀ operatingꢀconditions,ꢀelectricalꢀspecifications,ꢀandꢀper-
provideꢀaꢀguaranteedꢀcommonꢀmodeꢀtransientꢀimmu- formanceꢀcharacteristicsꢀshownꢀinꢀtheꢀfiguresꢀareꢀiden-
nityꢀspecificationꢀofꢀ1000ꢀV/µs.ꢀPackageꢀstylesꢀforꢀtheseꢀ ticalꢀ forꢀ allꢀ parts.ꢀ Occasionalꢀ exceptionsꢀ existꢀ dueꢀ toꢀ
partsꢀareꢀ8ꢀandꢀ16ꢀpinꢀDIPꢀthroughꢀholeꢀ(caseꢀoutlinesꢀ packageꢀ variationsꢀ andꢀ limitations,ꢀ andꢀ areꢀ asꢀ noted.ꢀ
PꢀandꢀEꢀrespectively).ꢀDevicesꢀmayꢀbeꢀpurchasedꢀwithꢀaꢀ Additionally,ꢀtheꢀsameꢀpackageꢀassemblyꢀprocessesꢀandꢀ
varietyꢀofꢀleadꢀbendꢀandꢀplatingꢀoptions.ꢀSeeꢀSelectionꢀ materialsꢀareꢀusedꢀinꢀallꢀdevices.ꢀ
GuideꢀTableꢀ forꢀ details.ꢀ Standardꢀ Microcircuitꢀ Drawingꢀ
(SMD)ꢀ partsꢀ areꢀ availableꢀ forꢀ eachꢀ packageꢀ andꢀ leadꢀ
style.
Selection Guide – Package Styles and Lead Configuration Options
Package
16 Pin DIP
ThroughꢀHole
2
8 Pin DIP
ThroughꢀHole
1
8 Pin DIP
ThroughꢀHole
2
LeadꢀStyle
Channels
CommonꢀChannelꢀWiring
WithstandꢀTestꢀVoltage
AvagoꢀPartꢀ#ꢀ&ꢀOptions
StandardꢀCommercial
MIL-PRF-38534,ꢀClassꢀH
MIL-PRF-38534,ꢀClassꢀK
StandardꢀLeadꢀFinish
SolderꢀDipped*
VCC,ꢀGND
1500ꢀVdc
None
VCC,ꢀGND
1500ꢀVdc
1500ꢀVdc
ACPL-2670L
ACPL-2672L
ACPL-268KL
GoldꢀPlate
ACPL-5600L
ACPL-5601L
ACPL-560KL
GoldꢀPlate
ACPL-5630L
ACPL-5631L
ACPL-563KL
GoldꢀPlate
Optionꢀ-200
Optionꢀ-100
Optionꢀ-300
Optionꢀ-200
Optionꢀ-100
Optionꢀ-300
Optionꢀ-200
Optionꢀ-100
Optionꢀ-300
ButtꢀCut/GoldꢀPlate
GullꢀWing/Soldered*
ClassꢀHꢀSMDꢀPartꢀ#
Prescriptꢀforꢀallꢀbelow
EitherꢀGoldꢀorꢀSolder
GoldꢀPlate
5962-
5962-
5962-
0824203HEX
0824203HEC
0824203HEA
0824203HUC
0824203HUA
0824203HTA
0824201HPX
0824201HPC
0824201HPA
0824201HYC
0824201HYA
0824201HXA
0824202HPX
0824202HPC
0824202HPA
0824202HYC
0824202HYA
0824202HXA
SolderꢀDipped*
ButtꢀCut/GoldꢀPlate
ButtꢀCut/Soldered*
GullꢀWing/Soldered*
ClassꢀKꢀSMDꢀPartꢀ#
Prescriptꢀforꢀallꢀbelow
EitherꢀGoldꢀorꢀSolder
GoldꢀPlate
5962-
5962-
5962-
0824203KEX
0824203KEC
0824203KEA
0824203KUC
0824203KUA
0824203KTA
0824201KPX
0824201KPC
0824201KPA
0824201KYC
0824201KYA
0824201KXA
0824202KPX
0824202KPC
0824202KPA
0824202KYC
0824202KYA
0824202KXA
SolderꢀDipped*
ButtꢀCut/GoldꢀPlate
ButtꢀCut/Soldered*
GullꢀWing/Soldered*
*ꢀSolderꢀcontainsꢀlead.
2
Functional Diagrams
16ꢀPinꢀDIP
8ꢀPinꢀDIP
8ꢀPinꢀDIP
ThroughꢀHole
2ꢀChannels
ThroughꢀHole
1ꢀChannel
ThroughꢀHole
2ꢀChannels
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1
2
8
7
6
5
1
V
8
CC
CC
V
CC
V
V
O1
O2
V
V
E
O1
2
3
4
7
6
5
V
OUT
3
4
V
O2
GND
GND
GND
Note:ꢀDualꢀchannelꢀdevicesꢀhaveꢀcommonꢀV ꢀandꢀground.ꢀSingleꢀchannelꢀDIPꢀhasꢀanꢀ
CC
enableꢀpinꢀ7.ꢀꢀAllꢀdiagramsꢀareꢀ“topꢀview.”
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
8 Pin DIP Through Hole, 1 and 2 Channels
Device Marking
9.40 (0.370)
8.13 (0.320)
MAX.
Avago LOGO
Avago P/N
DSCC SMD[1]
DSCC SMD[1]
PIN ONE/
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
* 50434
COMPLIANCE INDICATOR,[1]
9.91 (0.390)
DATE CODE, SUFFIX (IF NEEDED)
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
COUNTRY OF MFR.
Avago CAGE CODE[1]
4.32 (0.170)
MAX.
ESD IDENT
Noteꢀ1.ꢀQualifiedꢀpartsꢀonly
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3
Hermetic Optocoupler Options
Option
Description
100
Surfaceꢀmountableꢀhermeticꢀoptocouplerꢀwithꢀleadsꢀtrimmedꢀforꢀbuttꢀjointꢀassembly.ꢀThisꢀoptionꢀisꢀavailableꢀ
onꢀstandardꢀcommercial,ꢀclassꢀHꢀ&ꢀclassꢀKꢀproductꢀinꢀ8ꢀandꢀ16ꢀpinꢀDIPꢀ(seeꢀdrawingsꢀbelowꢀforꢀdetails).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Leadꢀfinishꢀisꢀsolderꢀdippedꢀratherꢀthanꢀgoldꢀplated.ꢀThisꢀoptionꢀisꢀavailableꢀonꢀstandardꢀcommercial,ꢀclassꢀHꢀ
andꢀclassꢀKꢀproductsꢀinꢀ8ꢀandꢀ16ꢀpinꢀDIP.ꢀDSCCꢀDrawingꢀpartꢀnumbersꢀcontainꢀprovisionsꢀforꢀleadꢀfinish.ꢀ
Surfaceꢀmountableꢀhermeticꢀoptocouplerꢀwithꢀleadsꢀcutꢀandꢀbentꢀforꢀgullꢀwingꢀassembly.ꢀThisꢀoptionꢀisꢀavail-
ableꢀonꢀstandardꢀcommercial,ꢀclassꢀHꢀ&ꢀclassꢀKꢀproductꢀinꢀ8ꢀandꢀ16ꢀpinꢀDIPꢀ(seeꢀdrawingsꢀbelowꢀforꢀdetails).ꢀ
Thisꢀoptionꢀhasꢀsolderꢀdippedꢀleads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
MIN.
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Solderꢀcontainsꢀlead.
4
Absolute Maximum Ratings
Noꢀderatingꢀrequiredꢀupꢀtoꢀ+125°C.
Parameter
Symbol
Min.
-65
-55
Max.
Units
°C
StorageꢀTemperature
OperatingꢀTemperature
CaseꢀTemperature
TS
TA
TC
TJ
+150
+125
°C
+170
°C
JunctionꢀTemperature
LeadꢀSolderꢀTemperature
+175
°C
260ꢀforꢀ10ꢀsec
40
°C
PeakꢀForwardꢀInputꢀCurrent
(eachꢀchannel,ꢀ≤1ꢀmsꢀduration)
IF(PEAK)
IF(AVG)
mA
AverageꢀInputꢀForwardꢀCurrentꢀ(eachꢀchannel)
InputꢀPowerꢀDissipationꢀ(eachꢀchannel)
ReverseꢀInputꢀVoltageꢀ(eachꢀchannel
SupplyꢀVoltageꢀ(1ꢀminuteꢀmaximum)
OutputꢀCurrentꢀ(eachꢀchannel)
20
35
5
mA
mW
V
VR
VCC
IO
7.0
25
7
V
mA
V
OutputꢀVoltageꢀ(eachꢀchannel)
VO
PO
PD
OutputꢀPowerꢀDissipationꢀ(eachꢀchannel)
PackageꢀPowerꢀDissipationꢀ(eachꢀchannel)
40
200
mW
mW
Single Channel Product Only
EnableꢀInputꢀVoltage
VE
3.6
V
8 Pin Ceramic DIP Single Channel Schematic
Noteꢀenableꢀpinꢀ7.ꢀAnꢀexternalꢀ0.01ꢀµFꢀtoꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀmustꢀ
beꢀconnectedꢀbetweenꢀV ꢀandꢀgroundꢀforꢀeachꢀpackageꢀtype.
CC
ESD Classification
MIL-PRF-38534ꢀandꢀMIL-STD-883,ꢀMethodꢀ3015
ACPL-560L/01L/0KL,ꢀ5962-0824201
ACPL-5630L/31L/3KL,ꢀ5962-0824202
ACPL-2670L/72L/268KL,ꢀ5962-0824203
( B),ꢀClassꢀ1B
(
(
A),ꢀClassꢀ3A
),ꢀClassꢀ2
Recommended Operating Conditions
Parameter
Symbol
IFL
Min.
0
Max.
250
20
Units
µA
InputꢀCurrent,ꢀLowꢀLevel,ꢀEachꢀChannel
InputꢀCurrent,ꢀHighꢀLevel,ꢀEachꢀChannel
SupplyꢀVoltage,ꢀOutput
IFH
10
3.0
mA
V
VCC
N
3.6
6
FanꢀOutꢀ(TTLꢀLoad)ꢀEachꢀChannel
5
Recommended Operating Conditions (cont’d.)
SingleꢀChannelꢀProductꢀOnly[10]
Parameter
Symbol
VEH
Min.
2.0
0
Max.
VCC
Units
HighꢀLevelꢀEnableꢀVoltage
LowꢀLevelꢀEnableꢀVoltage
V
V
VEL
0.8
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)
Group
A[13]
Limits
Sub-
groups
Parameter
Symbol Test Conditions
Min.
Typ.*
Max.
Units
Fig.
Note
HighꢀLevel
OutputꢀCurrent
IOH
VCCꢀ=ꢀ3.3ꢀV,ꢀVOꢀ=ꢀ3.3ꢀV,
IFꢀ=ꢀ250ꢀµA
1,ꢀ2,ꢀ3
6
250
µA
1
1
LowꢀLevel
OutputꢀVoltage
VOL
VCCꢀ=ꢀ3.3ꢀV,ꢀIFꢀ=ꢀ10ꢀmA,
IOLꢀ(Sinking)ꢀ=ꢀ10ꢀmA
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
0.3
0.6
V
2
1,ꢀ8
1
CurrentꢀTransfer
Ratio
hFꢀCTR
ICCH
VOꢀ=ꢀ0.6ꢀV,ꢀIFꢀ=ꢀ10ꢀmA,
VCCꢀ=ꢀ3.3ꢀV
100
%
Logicꢀ
Highꢀ
Supplyꢀ
Current
Single
Channel
VCCꢀ=ꢀ3.3ꢀV,ꢀIFꢀ=ꢀ0ꢀmA
5
10
6
11
22
15
30
mA
mA
mA
mA
V
1
Dual
Channel
VCCꢀ=ꢀ3.3ꢀV,
IF1ꢀ=ꢀIF2ꢀ=ꢀ0ꢀmA
Logicꢀ
low
Supplyꢀ
Current
Single
Channel
ICCL
VCCꢀ=ꢀ3.3ꢀV,
IFꢀ=ꢀ20ꢀmA
1,ꢀ2,ꢀ3
1
Dual
Channel
VCCꢀ=ꢀ3.3ꢀV,
IF1ꢀ=ꢀIF2ꢀꢀ=ꢀ20ꢀmA
12
1.55
InputꢀForward
Voltage
VF
IFꢀ=ꢀ20ꢀmA
1,ꢀ2
3
1.75
1.85
3
1
InputꢀReverse
BreakdownꢀVoltage
BVR
II-O
IRꢀ=ꢀ10ꢀµA
1,ꢀ2,ꢀ3
5
V
1
Input-Output
LeakageꢀCurrent
RHꢀ≤ꢀ65%,ꢀTAꢀ=ꢀ25°C
1
4
1.0
4.0
µA
pF
2,ꢀ7
tꢀ=ꢀ5ꢀs,ꢀV ꢀ=ꢀ1500ꢀVdc
I-O
CapacitanceꢀBetweenꢀ CI-O
Input/ꢀOutput
fꢀ=ꢀ1ꢀMHz,ꢀTCꢀ=ꢀ25°C
1.0
1,ꢀ3,
13
*AllꢀtypicalꢀvaluesꢀareꢀatꢀVCCꢀ=ꢀ3.3ꢀV,ꢀTAꢀ=ꢀ25°C.
6
Electrical Characteristics (cont’d) TA = -55°C to +125°C unless otherwise specified
Group A[13]
Limits
Typ.*
43
Parameter
Symbol Test Conditions
Subgroups Min.
Max.
100
140
Units
Fig.
Note
PropagationꢀDelayꢀ
TimeꢀtoꢀHighꢀOutputꢀ
Level
tPLH
V ꢀ=ꢀ3.3ꢀV,ꢀRLꢀ=ꢀ510ꢀΩ,
CLꢀ=ꢀ50ꢀpF,ꢀIFꢀ=ꢀ13ꢀmA
9
ns
4,ꢀ5,ꢀ6
1,ꢀ5
CC
10,ꢀ11
PropagationꢀDelayꢀ
TimeꢀtoꢀLowꢀOutputꢀ
Level
tPHL
9
54
100
120
ns
10,ꢀ11
OutputꢀRiseꢀTime
OutputꢀFallꢀTime
tLH
RLꢀ=ꢀ510ꢀΩ,ꢀCLꢀ=ꢀ50ꢀpF,ꢀ
IFꢀ=ꢀ13ꢀmA
9,ꢀ10,ꢀ11
20
8
90
40
ns
1
tHL
CommonꢀModeꢀ
Transient
Immunityꢀatꢀ
HighꢀOutput
Level
|CMH|
VCMꢀ=ꢀ50ꢀVꢀ(PEAK),
VCCꢀ=ꢀ3.3ꢀV,ꢀ
VOꢀ(min.)ꢀ=ꢀ2ꢀV,
RLꢀ=ꢀ510ꢀΩ,ꢀIFꢀ=ꢀ0ꢀmA
9,ꢀ10,ꢀ11
9,ꢀ10,ꢀ11
1000
1000
>10000
V/µs
7
7
1,ꢀ6,
13
CommonꢀMode
Transient
ImmunityꢀatꢀLowꢀ
OutputꢀLevel
|CML|
VCMꢀ=ꢀ50ꢀVꢀ(PEAK),
VCCꢀ=ꢀ3.3ꢀV,ꢀ
VOꢀ(max.)ꢀ=ꢀ0.8ꢀV,ꢀ
RLꢀ=ꢀ510ꢀΩ,ꢀꢀIFꢀ=ꢀ10ꢀmA
>10000
-0.54
V/µs
1,ꢀ6,
13
Single Channel Product Only
LowꢀLevel
EnableꢀCurrent
IEL
VCCꢀ=ꢀ3.3ꢀV,
VEꢀ=ꢀ0.5ꢀV
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
-2.0
2.0
mA
V
HighꢀLevel
EnableꢀVoltage
VEH
VEL
9
LowꢀLevel
0.8
V
EnableꢀVoltage
*AllꢀtypicalꢀvaluesꢀareꢀatꢀVCCꢀ=ꢀ3.3ꢀV,ꢀTAꢀ=ꢀ25°C.
Typical Characteristics, T = 25°C, V = 3.3 V
A
CC
Parameter
Sym.
CIN
Typ.
60
Units
Test Conditions
Fig.
Note
InputꢀCapacitance
pF
VFꢀ=ꢀ0ꢀV,ꢀfꢀ=ꢀ1ꢀMHz
IFꢀ=ꢀ20ꢀmA
1
1
InputꢀDiodeꢀTemperature
Coefficient
∆VF
-1.5
mV/°C
∆T
A
Resistanceꢀ(Input-Output)
RI-O
1012
Ω
V ꢀ=ꢀ500ꢀV
2
I-O
Single Channel Product Only
PropagationꢀDelayꢀTimeꢀof
EnableꢀfromꢀVEHꢀtoꢀVEL
tELH
tEHL
32
28
ns
ns
RLꢀ=ꢀ510ꢀΩ,ꢀCLꢀ=ꢀ50ꢀpF
IFꢀ=ꢀ13ꢀmA,ꢀVEHꢀ=ꢀ3ꢀV,
VELꢀ=ꢀ0V
8,ꢀ9
1,ꢀ10
1,ꢀ11
PropagationꢀDelayꢀTimeꢀof
EnableꢀfromꢀVELꢀtoꢀVEH
Dual Channel Product Only
Input-Input
LeakageꢀCurrent
II-I
0.5
nA
RelativeꢀHumidityꢀ≤ꢀ65%
4
V ꢀ=ꢀ500ꢀV,ꢀtꢀ=ꢀ5ꢀs
I-I
Resistanceꢀ(Input-Input)
Capacitanceꢀ(Input-Input)
RI-I
CI-I
1012
0.55
Ω
VI-Iꢀ=ꢀ500ꢀV
fꢀ=ꢀ1ꢀMHz
4
4
pF
7
Notes:
ꢀ 1.ꢀ Eachꢀchannel.
ꢀ 2.ꢀ Allꢀ devicesꢀ areꢀ consideredꢀ two-terminalꢀ devices;ꢀ II-Oꢀ isꢀ measuredꢀ betweenꢀ allꢀ inputꢀ leadsꢀ orꢀ terminalsꢀ shortedꢀ togetherꢀ andꢀ allꢀ outputꢀ
leadsꢀorꢀterminalsꢀshortedꢀtogether.
ꢀ 3.ꢀ Measuredꢀbetweenꢀeachꢀinputꢀpairꢀshortedꢀtogetherꢀandꢀallꢀoutputꢀconnectionsꢀforꢀthatꢀchannelꢀshortedꢀtogether.
ꢀ 4.ꢀ Measuredꢀbetweenꢀadjacentꢀinputꢀpairsꢀshortedꢀtogetherꢀforꢀeachꢀmultichannelꢀdevice.
ꢀ 5.ꢀ tPHLꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀtheꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀ
theꢀoutputꢀpulse.ꢀTheꢀtPLHꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀpointꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀ
onꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
ꢀ 6.ꢀ CMLꢀ isꢀ theꢀ maximumꢀ rateꢀ ofꢀ riseꢀ ofꢀ theꢀ commonꢀ modeꢀ voltageꢀ thatꢀ canꢀ beꢀ sustainedꢀ withꢀ theꢀ outputꢀ voltageꢀ inꢀ theꢀ logicꢀ lowꢀ stateꢀ
(VOꢀ<ꢀ0.8ꢀV).ꢀ CMHꢀ isꢀ theꢀ maximumꢀ rateꢀ ofꢀ fallꢀ ofꢀ theꢀ commonꢀ modeꢀ voltageꢀ thatꢀ canꢀ beꢀ sustainedꢀ withꢀ theꢀ outputꢀ voltageꢀ inꢀ theꢀ logicꢀ
highꢀstateꢀ(VOꢀ>ꢀ2.0ꢀV).
ꢀ 7.ꢀ Thisꢀisꢀaꢀmomentaryꢀwithstandꢀtest,ꢀnotꢀanꢀoperatingꢀcondition.
ꢀ 8.ꢀ Itꢀisꢀessentialꢀthatꢀaꢀbypassꢀcapacitorꢀ(0.01ꢀtoꢀ0.1ꢀµF,ꢀceramic)ꢀbeꢀconnectedꢀfromꢀVCCꢀtoꢀground.ꢀTotalꢀleadꢀlengthꢀbetweenꢀbothꢀendsꢀofꢀ
thisꢀexternalꢀcapacitorꢀandꢀtheꢀisolatorꢀconnectionsꢀshouldꢀnotꢀexceedꢀ20ꢀmm.
ꢀꢀ9.ꢀ Noꢀexternalꢀpullꢀupꢀisꢀrequiredꢀforꢀaꢀhighꢀlogicꢀstateꢀonꢀtheꢀenableꢀinput.
10.ꢀ TheꢀtELHꢀenableꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀenableꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀ
theꢀtrailingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
11.ꢀ TheꢀtEHLꢀenableꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀtheꢀenableꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀ
theꢀleadingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
12.ꢀ Standardꢀcommercialꢀpartsꢀreceiveꢀ100%ꢀtestingꢀatꢀ25°Cꢀ(Subgroupsꢀ1ꢀandꢀ9).ꢀClassꢀHꢀandꢀKꢀpartsꢀreceiveꢀ100%ꢀtestingꢀatꢀ25,ꢀ125,ꢀandꢀ
-55°Cꢀ(Subgroupsꢀ1ꢀandꢀ9,ꢀ2ꢀandꢀ10,ꢀ3ꢀandꢀ11,ꢀrespectively).
13.ꢀ Parametersꢀareꢀtestedꢀasꢀpartꢀofꢀdeviceꢀinitialꢀcharacterizationꢀandꢀafterꢀdesignꢀandꢀprocessꢀchanges.ꢀParametersꢀareꢀguaranteedꢀtoꢀlimitsꢀ
specifiedꢀforꢀallꢀlotsꢀnotꢀspecificallyꢀtested.
100
80
60
40
20
0
5
4
3
2
1
0
VCC = 3.3 V
TA = 25 °C
VCC = 3.3 V
VO = 3.3 V
IF = 250 µA
RL
510 Ω
1 kΩ
4 kΩ
-60 -40 -20
0
20 40 60 80 100 120 140
1
2
3
4
5
6
7
TA - TEMPERATURE - °C
IF - INPUT DIODE FORWARD CURRENT - mA
Figure 1. High Level Output Current vs. Tempera- Figure 2. Input-Output Characteristics.
ture.
Figure 3. Input Diode Forward Characteristics.
8
D.U.T.
3.3 V
120
100
80
60
40
20
0
V
CC
PULSE
GENERATOR
VCC = 3.3 V
RL= 510 Ω
R
L
TA = 25°C
I
F
V
O
Z
t
= 50Ω
= 5 ns
O
H
0.01 µF
BYPASS
V
O
C *
L
INPUT
MONITORING
NODE
GND
tPLH
Rm
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
tPHL
10 11 12 13 14 15 16 17 18 19 20
IF - PULSE INPUT CURRENT - mA
Figure 5. Propagation Delay, tPHL and tPLH vs. Pulse Input
Current, IFH.
Figure 4. Test Circuit for tPHL and tPLH.*
D.U.T.
+3.3 V
B
V
CC
510
Ω
I
I
A
OUTPUT V
120
O
MONITORING
NODE
VCC = 3.3 V
IF = 13 mA
RL = 510 Ω
0.01 µF
BYPASS
100
GND
-
V
80
FF
V
CM
tPLH
+
60
PULSE GEN.
40
tPHL
20
0
-60 -40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
9
80
PULSE
GENERATOR
OUTPUT V
MONITORING
NODE
VCC = 3.3 V
E
Z
= 50
= 5 ns
Ω
70 VEH = 3.0 V
VEL = 0 V
O
r
t
+3.3 V
60
50
40
30
20
10
0
IF = 13 mA
D.U.T.
V
CC
R
L
V
E
I
= 13 mA
tELH
F
V
OUT
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
C *
tEHL
L
GND
* C INCLUDES PROBE AND
L
STRAY WIRING CAPACITANCE.
-60 -40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
Figure 9. Enable Propagation Delay vs. Temperature.
Figure 8. Test Circuit for tEHL and tELH.
V
CC
+5.5 V
V
D.U.T.*
OC
+5.5 V
V
CC
(EACH INPUT)
0.01 µF
+
-
V
200
Ω
200
Ω
IN
5.3 V
(EACH OUTPUT)
(EACH OUTPUT)
GND
CONDITIONS: I = 20 mA
F
I
= 25 mA
O
T
= +125 o
C
A
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
10
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Avago’sꢀ Hi-Relꢀ Optocouplersꢀ areꢀ inꢀ complianceꢀ withꢀ
MIL-PRF-38534ꢀ Classesꢀ Hꢀ andꢀ K.ꢀ Classꢀ Hꢀ andꢀ Classꢀ Kꢀ
devicesꢀ areꢀ alsoꢀ inꢀ complianceꢀ withꢀ DSCCꢀ drawingꢀ
5962-08242.
Testingꢀconsistsꢀofꢀ100%ꢀscreeningꢀandꢀqualityꢀconfor-
manceꢀinspectionꢀtoꢀMIL-PRF-38534.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved.
AV02-1327EN - June 30, 2008
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