ACPM-7821
更新时间：2024-09-18 08:12:02
品牌：AVAGO
描述：4 x 4 Power Amplifier Module for J-CDMA (898 - 925 MHz)
概述
数据手册ACPM-7821 概述
4 x 4 Power Amplifier Module for J-CDMA (898 - 925 MHz) 4 ×4功率放大器模块J- CDMA （ 898 - 925兆赫）
ACPM-7821 数据手册
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PDF下载ACPM-7821
4x4 Power Amplifier Module
for J-CDMA (898 – 925 MHz)
Data Sheet
Features
Description
• Excellent linearity
The ACPM-7821 is a CDMA (Code Division Multiple
Access) power amplifier module designed for hand-
sets operating in the 898–925MHz bandwidth. The
ACPM-7821 meets stringent CDMA linearity require-
ments up to 28 dBm output power.
• High efficiency
• 10-pin surface mounting package
(4 mm x 4 mm x 1.1 mm)
• Low quiescent current
A low current (Vcont) pin is provided for high effi-
ciency improvement of the low output power range.
The ACPM-7821 features CoolPAM circuit technology
offering state-of-the-art reliability, temperature
stability and ruggedness.
• Internal 50Ω matching networks for both RF input
and output
•
CDMA 95A/B, CDMA2000-1X/EVDO
ACPM-7821 is self contained, incorporating 50 ohm
input and output matching networks.
Applications
• Digital Cellular (J-CDMA)
Functional Block Diagram
Vref(1)
Vcont(2)
Bias Circuit & Control Logic
Inter
Stage
Match
Input
Match
Output
Match
DA
PA
RF Input
(4)
RF Output
(8)
MMIC
MODULE
Vcc1(5)
Vcc2(6)
Ordering Information
Part Number
No. of Devices
Container
ACPM-7821-TR1
ACPM-7821-BLK
1000
100
7" Tape and Reel
Bulk
Table 1. Absolute Maximum Ratings[1]
Parameter
Symbol
Min.
Nominal
Max.
Unit
RF Input Power
Pin
–
–
10.0
5.0
dBm
V
DC Supply Voltage
DC Reference Voltage
Control Voltage
Vcc
0
3.4
2.85
2.85
–
Vref
Vcont
Tstg
0
3.3
V
0
3.3
V
Storage Temperature
-55
+125
°C
Table 2. Recommended Operating Conditions
Parameter
Symbol
Min.
Nominal
Max.
Unit
DC Supply Voltage
Vcc
3.2
3.4
4.2
V
V
DC Reference Voltage
Vref
2.75
2.85
2.95
Mode Control Voltage
– High Power Mode
– Low Power Mode
Vcont
Vcont
–
–
0
2.85
–
–
V
V
Operating Frequency
Fo
To
898
-30
–
925
85
MHz
Case Operating Temperature
25
°C
Table 3. Power Range Truth Table
Power Mode
Symbol
Vref
Vcont[2]
Range
High Power Mode
Low Power Mode
Shut Down Mode
Notes:
PR2
PR1
–
2.85
2.85
0
Low
High
–
~28 dBm
~17 dBm
–
1. No damage assuming only one parameter is set at limit at a time with all other parameters set at or
below nominal value.
2. High (2.0V – 3.0V), Low (0.0V – 0.5V).
2
Table 4. Electrical Characteristics for CDMA Mode (Vcc=3.4V, Vref=2.85V, T=25°C)
Characteristics
Symbol
Condition
Min.
Typ.
Max.
Unit
Gain_hi
Gain_low
Pout = 28.0 dBm
Pout = 17 dBm
24
17
27
20
dB
dB
Gain
PAE_hi
PAE_low
Pout = 28.0 dBm
Pout = 17 dBm
37
17
41.2
21.5
%
%
Power Added Efficiency
Total Supply Current
Icc_hi
Icc_low
Pout = 28.0 dBm
Pout = 17 dBm
450
68
500
86
mA
mA
Iq_hi
Iq_low
High Power Mode
Low Power Mode
85
14
115
22
mA
mA
Quiescent Current
Reference Current
Iref_hi
Iref_low
Pout = 28.0 dBm
Pout = 17 dBm
4
4.5
7
8
mA
mA
Control Current[1]
Icont
Ipd
Pout = 17 dBm
Vref = 0V
0.2
0.2
1
5
mA
Total Current in Power-down mode
µA
0.885 MHz offset ACPR1_hi
1.98 MHz offset ACPR2_hi
Pout = 28.0 dBm
Pout = 28.0 dBm
-53
-60
-46
-57
dBc
dBc
ACPR in High power mode
ACPR in Low power mode
Harmonic Suppression
0.885 MHz offset ACPR1_low
1.98 MHz offset ACPR2_low
Pout = 17 dBm
Pout = 17 dBm
-57
-68
-46
-57
dBc
dBc
Second
Third
2f0
3f0
Pout = 28.0 dBm
Pout = 28.0 dBm
-35
-55
-30
-40
dBc
dBc
Input VSWR
VSWR
S
2:1
2.5:1
-60
VSWR
dBc
Stability (Spurious Output)
Noise Power in Rx Band
Ruggedness (No Damage)
Notes:
VSWR 6:1, All phase
Pout = 28.0 dBm
RxBN
Ru
-136
-134
10:1
dBm/Hz
VSWR
Pout < 28.0 dBm, Pin < 10.0 dBm
1. Control current when series 6.2kohm is used.
2. Characterized with IS-95 modulated signal
3
Characterization Data(Vcc=3.4V, Vref=2.85V, T=25°C)
30
25
20
15
10
500
450
400
350
898MHz
910MHz
925MHz
898MHz
300
910MHz
250
200
925MHz
150
100
50
5
0
0
-10
-5
0
5
10
15
20
25
30
-10
-5
0
5
10
15
20
25
30
Pout (dBm)
Pout (dBm)
Figure 1. Total Current vs. Output Power.
Figure 2. Gain vs. Output Power.
45
40
35
30
25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
898MHz
910MHz
925MHz
898MHz
910MHz
925MHz
20
15
10
5
0
-10
-5
0
5
10
15
20
25
30
-10
-5
0
5
10
15
20
25
30
Pout (dBm)
Pout (dBm)
Figure 4. Adjacent Channel Power Ratio 1 vs.
Output Power.
Figure 3. Power Added Efficiency vs. Output Power.
-40
-45
-50
-55
898MHz
-60
-65
-70
910MHz
925MHz
-75
-80
-85
-90
-10
-5
0
5
10
15
20
25
30
Pout (dBm)
Figure 5. Adjacent Channel Power Ratio 2 vs.
Output Power.
4
Evaluation Board Description
Vref
1 Vref
GND 10
GND 9
C1
100pF
Vcont
2 Vcont
3 GND
4 RF In
5 Vcc1
C2
100pF
R1
6.2kohm
RF Out
RF Out 8
GND 7
RF In
Vcc1
Vcc2 6
C4
2.2µF
C3
22pF
C7
68pF
C5
1.5nF
C6
2.2µF
Vcc2
Figure 6. Evaluation Board Schematic.
C1
R1
C2
AVAGO
ACPM-7821
PYYWW
AAAAA
C7
C3
C5
C6
C4
Figure 7. Evaluation Board Assembly Diagram.
5
Package Dimensions and Pin Descriptions
Pin 1 Mark
0.48
10
9
1
2
4
0.1
3
4
5
8
7
6
1.1 0.1
4
0.1
TOP VIEW
SIDE VIEW
1.9
1.0
Pin #
Name
Vref
Description
Reference Voltage
Control Voltage
Ground
1
2
3
4
5
6
7
8
9
10
0.5
0.85
0.85
Vcont
GND
RF In
Vcc1
Vcc2
GND
RF Out
GND
GND
0.6
RF Input
Supply Voltage
Supply Voltage
Ground
1.7
1.9
RF Output
Ground
0.4
0.4
Ground
BOTTOM VIEW
PIN DESCRIPTIONS
Figure 8. Package Dimensional Drawing and Pin Descriptions.
6
Package Dimensions and Pin Descriptions, continued
Pin 1 Mark
AVAGO
ACPM-7821
PYYWW
Manufacturing Part Number
Lot Number
P
Manufacturing info
AAAAA
YY
WW
Manufacturing Year
Work Week
AAAAA Assembly Lot Number
Figure 9. Marking Specifications.
7
Peripheral Circuit in Handset
+2.85V
C8
MSM PA_ON
PA_R0
R1
C2
C1
Output Matching Circuit
C6
ACPM-7821
Vdd
Vref
Vcont
GND
IN
GND
GND
OUT
GND
Vcc2
RF Out
RF In
Duplexer
RF SAW
Vcc1
C7
L1
C3
C4
C5
VBATT
Notes:
- Recommended voltage for Vref is 2.85V
- Place C1 near to Vref pin.
- Place C3 and C4 close to pin 5 (Vcc1) and pin 6 (Vcc2). These capacitors can affect the RF performance
- Use 50Ω transmission line between PAM and Duplexer and make it as short as possible to reduce conduction loss
- π-type circuit topology is good to use for matching circuit between PA and Duplexer.
- Pull-up resistor(R1) should be used to limit current drain. 6.2kΩ is recommended for ACPM-7821
Figure 10. Peripheral Circuit.
8
Calibration
power where PA mode changes from high mode to
Calibration procedure is shown in Figure 11. Two low mode), should be adopted to prevent system
calibration tables, high mode and low mode respec- oscillation. 3 to 5 dB is recommended for Hysteresis.
tively, are required for CoolPAM, which is due to gain
difference in each mode.
Average Current and Talk Time
Probability Distribution Function implies that what
For continuous output power at the mode change
is important for longer talk time is the efficiency of
points, the input power should be adjusted accord-
low or medium power range rather than the efficiency
ing to gain step during the mode change.
at full power. ACPM-7821 idle current is 14 mA and
operating current at 17 dBm is 68 mA at nominal
Offset Value
condition. This PA with low current consumption pro-
longs talk time by no less than 30 minutes compared
to other PAs.
(difference between rising point and falling point)
Offset value, which is the difference between the ris-
ing point (output power where PA mode changes from
low mode to high mode) and falling point (output
Average current = ∫(PDF x Current)dp
TX AGC
Gain
Low mode
High mode
High Mode
Low Mode
Pout
Max PWR
Pout
Falling
Rising
Falling
Min PWR
Rising
Figure 12. Setting of offset between rising and falling power.
Figure 11. Calibration procedure.
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
700
600
500
CDG Urban
CDG Suburban
400
300
200
100
0
0.00
-50
-40
-30
-20
-10
0
10
20
30
PA Out (dBm)
Conv PAM
Digitally Controlled PA
Cool PAM
Figure 13. CDMA Power Distribution Function.
9
0.1
PCB Design Guidelines
0.25
The recommended ACPM-7821 PCB Land pattern is
shown in Figure 14 and Figure 15. The substrate is
coated with solder mask between the I/O and con-
ductive paddle to protect the gold pads from short
circuit that is caused by solder bleeding/bridging.
0.85
Stencil Design Guidelines
A properly designed solder screen or stencil is
required to ensure optimum amount of solder paste
is deposited onto the PCB pads.
0.4
0.7
0.6
The recommended stencil layout is shown in Figure
16. Reducing the stencil opening can potentially
generate more voids. On the other hand, stencil open-
ings larger than 100% will lead to excessive solder
paste smear or bridging across the I/O pads or
conductive paddle to adjacent I/O pads. Considering
the fact that solder paste thickness will directly affect
the quality of the solder joint, a good choice is to use
laser cut stencil composed of 0.100 mm (4mils) or
0.127 mm (5mils) thick stainless steel which is capable
of producing the required fine stencil outline.
Ø 0.3mm
on 0.6mm pitch
Figure 14. Metallization.
0.8
0.65
0.5
1.8
0.6
0.85
2.0
0.8 x 0.5
0.8 x 0.6
Figure 15. Solder Mask Opening.
0.7
0.6
0.4
1.6
0.85
1.6
Figure 16. Solder Paste Stencil Aperture.
10
Tape Drawing
Dimension List
Annote
Millimeter
4.40 0.10
4.40 0.10
1.70 0.10
1.55 0.05
1.60 0.10
4.00 0.10
8.00 0.10
Annote
P2
P10
E
Millimeter
2.00 0.05
A0
B0
K0
D0
D1
P0
P1
40.00 0.20
1.75 0.10
F
5.50 0.05
W
T
12.00 0.30
0.30 0.05
Figure 17. Tape and Reel Format – 4mm x 4mm.
11
Reel Drawing
BACK VIEW
FRONT VIEW
Figure 18. Plastic Reel Format–13"/4".
12
Handling and Storage
package at various temperatures and relative humid-
ity, and times. After soak, the components are sub-
jected to three consecutive simulated reflows.
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the envi-
ronment. With the increase in voltage potential, the
outlet of neutralization or discharge will be sought. If
the acquired discharge route is through a semicon-
ductor device, destructive damage will result. ESD
countermeasure methods should be developed and
used to control potential ESD damage during handling
in a factory environment at each manufacturing site.
The out of bag exposure time maximum limits are
determined by the classification test describe
above which corresponds to an MSL classification
level 6 to 1 according to the JEDEC standard
IPC/JEDEC J-STD-020A and J-STD-033.
ACPM-7821 is MSL3. Thus, according to the J-STD-
033 p.11 the maximum Manufacturers Exposure Time
(MET) for this part is 168 hours. After this time
period, the part would need to be removed from the
reel, de-taped and then re-bake.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sen-
sitive to damage induced by absorbed moisture and MSL classification reflow temperature for the
temperature. Avago follows JEDEC Standard J-STD ACPM-7821 is targeted at 250°C +0/-5°C. Figure 19
020A. Each component and package type is classi- and Table 7 show typical SMT profile for maximum
fied for moisture sensitivity by soaking a known dry temperature of 250°C +0/-5°C.
Table 5. ESD Classification
Pin#
HBM
MM
CDM
Rating
Class
Rating
Class
Rating
Class
All Pins
1000V
Class 1C
200V
Class B
200V
Class II
(JESD22-A115-A)
(JESD22-C101C)
Note:
1. PA module products should be considered extremely ESD sensitive.
Table 6. Moisture Classification Level and Floor Life
MSL Level
Floor Life (out of bag) at factory ambient ≤30°C/60% RH or as stated
1
Unlimited at ≤30oC/85% RH
1 year
2
2a
4 weeks
3
168 hours
72 hours
4
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note:
1. The MSL Level is marked on the MSL Label on each shipping bag.
13
Handling and Storage, continued
Figure 19. Typical SMT Reflow Profile for Maximum Temperature = 250 +0/-5°C.
Table 7. Typical SMT Reflow Profile for Maximum Temperature = 250+0/-5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°C/sec max
3°C/sec max
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60–120 sec
100°C
150°C
60–180 sec
Tsmax to TL
- Ramp-up Rate
3°C/sec max
Time maintained above:
- Temperature (TL)
- Time (TL)
183°C
60–150 sec
217°C
60–150 sec
Peak Temperature (Tp)
225 +0/-5°C
10–30 sec
250 +0/-5°C
10–30 sec
Time within 5°C of actual Peak Temperature (tp)
Ramp-down Rate
6°C/sec max
6 min max.
6°C/sec max
8 min max.
Time 25°C to Peak Temperature
14
Handling and Storage, continued
Removal for Failure Analysis
Not following the requirements of 4-1 may cause
moisture/reflow damage that could hinder or com-
pletely prevent the determination of the original fail-
ure mechanism.
Storage Conditions
Packages described in this document must be stored
in sealed moisture barrier, anti-static bags. Shelf life
in a sealed moisture barrier bag is 12 months at <40°C
and 90% relative humidity (RH) J-STD-033 p.7.
Baking of Populated Boards
Some SMD packages and board materials are not able
to withstand long duration bakes at 125°C. Examples
of this are some FR-4 materials, which cannot with-
stand a 24 hr bake at 125°C. Batteries and electro-
lytic capacitors are also temperature sensitive. With
component and board temperature restrictions in
mind, choose a bake temperature from Table 4-1 in
J-STD 033; then determine the appropriate bake
duration based on the component to be removed. For
additional considerations see IPC-7711 and IPC-7721.
Out-of-Bag Time Duration
After unpacking the device must be soldered to the
PCB within 168 hours as listed in the J-STD-020B
p.11 with factory conditions <30oC and 60% RH.
Baking
It is not necessary to re-bake the part if both condi-
tions (storage conditions and out-of-bag
condition) have been satisfied. Baking must be done
if at least one of the conditions above have
not been satisfied. The baking conditions are 125
for 24 hours J-STD-033 p.8.
Derating due to Factory Environmental Conditions
°C
Factory floor life exposures for SMD packages
removed from the dry bags will be a function of the
ambient environmental conditions. A safe, yet con-
servative, handling approach is to expose the SMD
packages only up to the maximum time limits for each
moisture sensitivity level as shown in Table 6. This
approach, however, does not work if the factory hu-
midity or temperature are greater than the testing
conditions of 30°C/60% RH. A solution for address-
ing this problem is to derate the exposure times based
on the knowledge of moisture diffusion in the com-
ponent packaging materials (ref. JESD22-A120). Rec-
ommended equivalent total floor life exposures can
be estimated for a range of humidity’s and tempera-
tures based on the nominal plastic thickness for each
device. Table 8 lists equivalent derated floor lives for
humidity’s ranging from 20– 90% RH for three tem-
peratures, 20°C, 25°C, and 30°C. This table is appli-
cable to SMDs molded with novolac, biphenyl or mul-
tifunctional epoxy mold compounds. The following
assumptions were used in calculating Table 8:
CAUTION: Tape and reel materials typically cannot
be baked at the temperature described above.
If out-of-bag exposure time is exceeded, parts must
be baked for a longer time at low temperatures, or
the parts must be re-reeled, de-taped, re-baked and
then put back on tape and reel. (See moisture sensi-
tive warning label on each shipping bag for informa-
tion of baking)
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This
method will minimize moisture related component
damage. If any component temperature exceeds
200°C, the board must be baked dry per 4-2 prior to
rework and/or component removal. Component tem-
peratures shall be measured at the top center of the
package body. Any SMD packages that have not ex-
ceeded their floor life can be exposed to a maximum
body temperature as high as their specified maximum
reflow temperature.
1. Activation Energy for diffusion = 0.35eV
(smallest known value).
2. For ≤60% RH, use Diffusivity = 0.121exp
(- 0.35eV/kT) mm2/s (this uses smallest known
Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp
(- 0.35eV/kT) mm2/s (this uses largest known
Diffusivity @ 30°C).
15
Table 8. Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C For ICs with Novolac, Biphenyl and
Multifunctional Epoxies (Reflow at same temperature at which the component was classified)
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited
in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved.
Obsoletes 5989-2534EN
AV01-0265EN July 10, 2006
ACPM-7821 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ACPM-7821-BLK | AVAGO | 4 x 4 Power Amplifier Module for J-CDMA (898 - 925 MHz) | 获取价格 |
|
| ACPM-7821-TR1 | AVAGO | 4 x 4 Power Amplifier Module for J-CDMA (898 - 925 MHz) | 获取价格 |
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| ACPM-7822 | AVAGO | JCDMA 4x4 Power Amplifier Module (898-925MHz) | 获取价格 |
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| ACPM-7822-BLK | AVAGO | JCDMA 4x4 Power Amplifier Module (898-925MHz) | 获取价格 |
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| ACPM-7822-TR1 | AVAGO | JCDMA 4x4 Power Amplifier Module (898-925MHz) | 获取价格 |
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| ACPM-7824-BLK | AVAGO | 824MHz - 849MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER, 4 X 4 MM, GREEN PACKAGE-10 | 获取价格 |
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| ACPM-7824-TR1 | AVAGO | 824MHz - 849MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER, 4 X 4 MM, GREEN PACKAGE-10 | 获取价格 |
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| ACPM-7831-BLK | ETC | Amplifier. Other | 获取价格 |
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| ACPM-7831-TR1 | ETC | Amplifier. Other | 获取价格 |
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| ACPM-7833 | AGILENT | CDMA1900 (PCS) Power Amplifier Module | 获取价格 |
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