AFBR-53D5EZ [AVAGO]
850 nm VCSEL, 1 x 9 Fibre Optic Transceivers for Gigabit Ethernet; 850纳米VCSEL ， 1 ×9光纤收发器千兆以太网
| 型号： | AFBR-53D5EZ |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 850 nm VCSEL, 1 x 9 Fibre Optic Transceivers for Gigabit Ethernet |
| 文件： | 总15页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFBR-53D5Z Family
850 nm VCSEL, 1 x 9 Fibre Optic Transceivers
for Gigabit Ethernet
Data Sheet
Features
Description
Compliant with Specifications for IEEE- 802.3z Gigabit
The AFBR-53D5Z transceiver from Avago Technologies
allows the system designer to implement a range of
solutions for multimode Gigabit Ethernet applications.
Ethernet
Industry Standard Mezzanine Height 1 x 9 Package
Style with Integral Duplex SC Connector
The overall Avago Technologies transceiver product
consists of three sections: the transmitter and receiver
optical subassemblies, an electrical subassembly, and
the package housing which incorporates a duplex SC
connector receptacle.
AFBR-53D5Z Performance: 220 m with 62.5/125 m
MMF
IEC 60825-1 Class 1/CDRH Class I Laser Eye Safe
Single +5 V Power Supply Operation with PECL Logic
Interfaces
Transmitter Section
Wave Solder and Aqueous Wash Process Compatible
RoHS compliance
The transmitter section of the AFBR-53D5Z consists of
an 850 nm Vertical Cavity Surface Emitting Laser (VC-
SEL) in an optical subassembly (OSA), which mates to
the fiber cable.
Applications
Switch to Switch Interface
Switched Backbone Applications
High Speed Interface for File Servers
High Performance Desktops
Receiver Section
The receiver of the AFBR-53D5Z includes a silicon PIN
photodiode mounted together with a custom, silicon
bipolar transimpedance preamplifier IC in an OSA. This
OSA is mated to a custom silicon bipolar circuit that
provides post-amplification and quantization.
Related Products
Physical Layer ICs Available for Optical or Copper In-
The post-amplifier also includes a Signal Detect circuit
which provides a PECL logic-high output upon detec-
tion of a usable input optical signal level. This singleen-
ded PECL output is designed to drive a standard PECL
input through a 50 Ω PECL load.
terface (HDMP-1636A/1646A)
Versions of this Transceiver Module Also Available for
Fibre Channel (AFBR-53D3Z)
GigabitInterfaceConverters(GBIC)forGigabitEthernet
(CX, SX,)
Package and Handling Instructions
Flammability
Regulatory Compliance
(See the Regulatory Compliance Table for transceiver
performance)
The AFBR-53D5Z transceiver housing is made of high
strength, heat resistant, chemically resistant, and UL
94V-0 flame retardant plastic.
The overall equipment design will determine the certifi-
cation level. The transceiver performance is offered as a
figure of merit to assist the designer in considering their
use in equipment designs.
Recommended Solder and Wash Process
The AFBR-53D5Z is compatible with industry standard
wave or hand solder processes.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important. The first case is during handling of
the transceiver prior to mounting it on the circuit board.
It is important to use normal ESD handling precautions
for ESD sensitive devices. These precautions include us-
ing grounded wrist straps, work benches, and floor mats
in ESD controlled areas. The transceiver performance
has been shown to provide adequate performance in
typical industry production environments.
Process plug
This transceiver is supplied with a process plug (HFBR-
5000) for protection of the optical ports within the
duplex SC connector receptacle. This process plug pre-
vents contamination during wave solder and aqueous
rinse as well as during handling, shipping and storage.
It is made of a hightemperature, molded sealing mate-
rial that can withstand 80°C and a rinse pressure of 110
lbs per square inch.
The second case to consider is static discharges to the
exterior of the equipment chassis containing the trans-
ceiver parts. To the extent that the duplex SC connector
receptacle is exposed to the outside of the equipment
chassis it may be subject to whatever system-level ESD
test criteria that the equipment is intended to meet. The
transceiver performance is more robust than typical in-
dustry equipment requirements of today.
Recommended Solder fluxes used with the AFBR-53D5Z
should be water-soluble, organic fluxes. Recommended
solder fluxes include Lonco 3355-11 from London
Chemical West, Inc. of Burbank, CA, and 100 Flux from
Alpha-Metals of Jersey City, NJ.
Recommended Cleaning/Degreasing Chemicals
Electromagnetic Interference (EMI)
Alcohols: methyl, isopropyl, isobutyl.
Most equipment designs utilizing these high-speed
transceivers from Avago Technologies will be required
to meet the requirements of FCC in the United States,
CENELEC EN55022 (CISPR 22) in Europe and VCCI in Ja-
pan. Refer to EMI section (page 5) for more details.
Aliphatics: hexane, heptane Other: soap solution, naph-
tha.
Do not use partially halogenated hydrocarbons such
as 1,1.1 trichloroethane, ketones such as MEK, acetone,
chloroform, ethyl acetate, methylene dichloride, phe-
nol, methylene chloride, or N-methylpyrolldone. Also,
HP does not recommend the use of cleaners that use
halogenated hydrocarbons because of their potential
environmental harm.
Immunity
Equipment utilizing these transceivers will be subject
to radio-frequency electromagnetic fields in some en-
vironments. These transceivers have good immunity to
such fields due to their shielded design.
2
Eye Safety
CAUTION:
These laser-based transceivers are classified as AEL Class
There are no user serviceable parts nor any mainte-
I (U.S. 21 CFR(J) and AEL Class 1 per EN 60825-1 (+A11). nance required for the AFBR-53D5Z. All adjustments are
They are eye safe when used within the data sheet lim- made at the factory before shipment to our customers.
its per CDRH. They are also eye safe under normal op-
Tampering with or modifying the performance of the
erating conditions and under all reasonably forseeable AFBR-53D5Z will result in voided product warranty.
single fault conditions per EN60825-1. Avago Technolo- It may also result in improper operation of the AFBR-
gies has tested the transceiver design for compliance 53D5Z circuitry, and possible overstress of the laser
with the requirements listed below under normal op-
source. Device degradation or product failure may re-
erating conditions and under single fault conditions sult.
where applicable. TUV Rheinland has granted certi-fica-
Connection of the AFBR-53D5Z to a nonapproved opti-
tion to these transceivers for laser eye safety and use
in EN 60950 and EN 60825-2 applications. Their perfor-
mance enables the transceivers to be used without con-
cern for eye safety up to 7 volts transmitter VCC.
cal source, operating above the recommended absolute
maximum conditions or operating the AFBR-53D5Z in a
manner inconsistent with its design and function may
result in hazardous radiation exposure and may be con-
sidered an act of modifying or manufacturing a laser
product. The person(s) performing such an act is re-
quired by law to recertify and reidentify the laser prod-
uct under the provisions of U.S. 21 CFR (Subchapter J).
Regulatory Compliance
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
MIL-STD-883C
Method 3015.4
Class 1 (>2000V).
Electrostatic Discharge (ESD)
to the Duplex SC Receptacle
Variation of IEC 801-2
Typically withstand at least 15 kV
without damage when the duplex SC
connector receptacle is contacted by a
Human Body Model probe.
Electromagnetic Interference
(EMI)
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A)
Margins are dependent on customer
board and chassis designs.
VCCI Class I
Immunity
Variation of IEC 61000-4-3
Typically show no measurable effect
from a 10 V/m field swept from 27 to
1000 MHz applied to the transceiver
without a chassis enclosure.
Laser Eye Safety and
Equipment Type Testing
US 21 CFR, Subchapter J per Para-
graphs 1002.10 and 1002.12
AEL Class I, FDA/CDRH
AFBR-53D5Z Accenssion #9720151-53
EN60950-2000
EN60825-1:1994+A1:2002+A2:2001
EN60825-2:2000
AEL Class 1, TUV Rheinland of North
America AFBR-53D5Z
Certificate #09771047.028
Protection Class III
Component Recognition
Underwriters Laboratories and Ca-
nadian Standards Association Joint
Component Recognition for Informa-
tion Technology Equipment Including
Electrical Business Equipment.
UL File E173874
3
APPLICATION SUPPORT
Optical Power Budget and Link Penalties
is a single-ended, +5 V PECL output signal that is dc-
coupled to pin 4 of the module. Signal Detect should
not be ac-coupled externally to the follow-on circuits
because of its infrequent state changes. Caution should
be taken to account for the proper interconnection be-
tween the supporting Physical Layer integrated circuits
and this AFBR-53D5Z transceiver. Figure 3 illustrates a
recommended interface circuit for interconnecting to a
+5 Vdc PECL fiber-optic transceiver.
The worst-case Optical Power Budget (OPB) in dB for a
fiberoptic link is determined by the difference between
the minimum transmitter output optical power (dBm
avg) and the lowest receiver sensitivity (dBm avg). This
OPB provides the necessary optical signal range to es-
tablish a working fiber-optic link. The OPB is allocated
for the fiber-optic cable length and the corresponding
link penalties. For proper link performance, all penalties
that affect the link performance must be accounted for
within the link optical power budget. The Gigabit Eth-
ernet IEEE 802.3z standard identifies, and has modeled,
the contributions of these OPB penalties to establish the
link length requirements for 62.5/125 m and 50/125 m
multimode fiber usage. Refer to the IEEE 802.3z standard
and its supplemental documents that develop the mod-
el, empirical results and final specifications.
Some fiber-optic transceiver suppliers’ modules include
internal capacitors, with or without 50 Ohm termina-
tion, to couple their Data and Data-bar lines to the
I/O pins of their module. When designing to use these
type of transceivers along with Avago Technologies’
transceivers, it is important that the interface circuit can
accommodate either internal or external capacitive cou-
pling with 50 Ohm termination components for proper
operation of both transceiver designs. The internal dc-
coupled design of the AFBR-53D5Z I/O connections was
done to provide the designer with the most flexibility
for interfacing to various types of circuits.
Data Line Interconnections
Avago Technologies’AFBR-53D5Z fiber-optic transceiver
is designed to directly couple to +5 V PECL signals. The
transmitter inputs are internally dc-coupled to the laser
driver circuit from the transmitter input pins (pins 7,
8). There is no internal, capacitively-coupled 50 Ohm
termination resistance within the transmitter input
section. The transmitter driver circuit for the laser light
source is a dc-coupled circuit. This circuit regulates the
output optical power. The regulated light output will
maintain a constant output optical power provided
the data pattern is reasonably balanced in duty factor.
If the data duty factor has long, continuous state times
(low or high data duty factor), then the output optical
power will gradually change its average output optical
power level to its pre-set value. As for the receiver sec-
tion, it is internally ac-coupled between the pre-ampli-
fier and the postamplifier stages. The actual Data and
Data-bar outputs of the postamplifier are dc-coupled
to their respective output pins (pins 2, 3). Signal Detect
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the
event of a single fault failure, the transmitter must either
maintain normal, eye-safe operation or be disabled.
In the AFBR-53D5Z there are three key elements to the
laser driver safety circuitry: a monitor diode, a window
detector circuit, and direct control of the laser bias.
The window detection circuit monitors the average
optical power using the monitor diode. If a fault occurs
such that the transmitter DC regulation circuit cannot
maintain the preset bias conditions for the laser emitter
within 20ꢀ, the transmitter will automatically be dis-
abled. Once this has occurred, only an electrical power
reset will allow an attempted turn-on of the transmitter.
4
Signal Detect
terminate EM fields to the chassis to prevent their emis-
sions outside the enclosure. This metal shield contacts
the panel or enclosure on the inside of the aperture
on all but the bottom side of the shield and provides
a good RF connection to the panel. This option can ac-
commodate various panel or enclosure thickness, i.e.,
.04 in. min. to 0.10 in. max. The reference plane for this
panel thickness variation is from the front surface of the
panel or enclosure. The recommended length for pro-
truding the AFBR-53D5EZ transceiver beyond the front
surface of the panel or enclosure is 0.25 in. With this op-
tion, there is flexibility of positioning the module to fit
the specific need of the enclosure design. (See Figure 6
for the mechanical drawing dimensions of this shield.)
The Signal Detect circuit provides a deasserted output
signal that implies the link is open or the transmitter
is OFF as defined by the Gigabit Ethernet specification
IEEE 802.3z, Table 38.1. The Signal Detect threshold is
set to transition from a high to low state between the
minimum receiver input optional power and –30 dBm
avg. input optical power indicating a definite opti-
cal fault (e.g. unplugged connector for the receiver or
transmitter, broken fiber, or failed far-end transmitter or
data source). A Signal Detect indicating a working link is
functional when receiving encoded 8B/10B characters.
The Signal Detect does not detect receiver data error or
error-rate. Data errors are determined by Signal process-
ing following the transceiver.
The third configuration, option F, is for applications that
are designed to have a flush mounting of the module
with respect to the front of the panel or enclosure. The
flush-mount design accommodates a large variety of
panel thickness, i.e., 0.04 in. min. to 0.10 in. max. Note
the reference plane for the flush-mount design is the in-
terior side of the panel or enclosure. The recommended
distance from the centerline of the transceiver front
solder posts to the inside wall of the panel is 0.55 in.
This option contacts the inside panel or enclosure wall
on all four sides of this metal shield. See Figure 8 for the
mechanical drawing dimensions of this shield.
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from electron-
ic equipment. Success in controlling generated Elec-
tromagnetic Interference (EMI) enables the designer to
pass a governmental agency’s EMI regulatory standard;
and more importantly, it reduces the possibility of inter-
ference to neighboring equipment. There are three op-
tions available for the AFBR-53D5Z with regard to EMI
shielding which provide the designer with a means to
achieve good EMI performance. The EMI performance
of an enclosure using these transceivers is dependent
on the chassis design. Avago Technologies encourages
using standard RF suppression practices and avoiding
poorly EMI-sealed enclosures.
The two designs are comparable in their shielding ef-
fectiveness. Both design options connect only to the
equipment chassis and not to the signal or logic ground
of the circuit board within the equipment closure. The
front panel aperture dimensions are recommended
in Figures 7 and 9. When layout of the printed circuit
board is done to incorporate these metal-shielded
transceivers, keep the area on the printed circuit board
directly under the metal shield free of any components
and circuit board traces. For additional EMI performance
advantage, use duplex SC fiber-optic connectors that
have low metal content inside them. This lowers the
ability of the metal fiber-optic connectors to couple EMI
out through the aperture of the panel or enclosure.
The first configuration is a standard AFBR-53D5Z fiber-
optic transceiver that has no external EMI shield. This
unit is for applications where EMI is either not an issue
for the designer, or the unit resides completely inside
a shielded enclosure, or the module is used in low den-
sity, extremely quiet applications.
The second configuration, option E, is for EMI shielding
applications where the position of the transceiver mod-
ule will extend outside the equipment enclosure. The
external metal shield of the transceiver helps locally to
5
Evaluation Kit
To help you in your preliminary transceiver evaluation,
Avago Technologies offers a 1250 MBd Gigabit Ethernet
evaluation board (Part # HFBR-0535). This board allows
testing of the fiber-optic VCSEL transceiver. It includes
the AFBR-53D5Z transceiver, test board, and application
instructions. In addition, a complementary evaluation
board is available for the HDMP-1636A 1250 MBd Giga-
bit Ethernet serializer/ deserializer (SERDES) IC. (Part #
HDMP-163k) Please contact your local Field Sales repre-
sentative for ordering details.
Absolute Maximum Ratings
Parameter
Symbol
Min.
-40
Typ.
Max.
100
7.0
Unit
°C
V
Reference
Storage Temperature
Supply Voltage
T
S
V
V
V
-0.5
-0.5
1
2
CC
I
Data Input Voltage
Transmitter Differential Input Village
Output Current
V
V
CC
1.6
50
95
V
D
I
D
mA
ꢀ
Relative Humidity
RH
5
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
70
Unit
°C
°C
V
Reference
Ambient Operating Temperature
Case Temperature
T
A
0
T
C
90
3
Supply Voltage
V
4.75
5.25
CC
Power Supply Rejection
Transmitter Data Input Voltage - Low
PSR
V -V
50
mV
V
4
5
5
P-P
-1.810
-1.165
0.3
-1.475
-0.880
1.6
IL CC
Transmitter Data Input Voltage - High V -V
V
IH CC
D
Transmitter Differential Input Voltage
Data Output Load
V
R
R
V
50
W
6
6
DL
Signal Detect Output Load
50
W
SDL
Process Compatibility
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Hand Lead Soldering Temperature /Time
T
t
/
260/10
°C/sec.
SOLD
SOLD
Wave Soldering and Aqueous Wash
T
t
/
260/10
°C/sec.
7
SOLD
SOLD
Notes:
1. The transceiver is class 1 eye-safe up to VCC = 7 V.
2. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs without damaging the input circuit.
3. Case temperature measurement referenced to the center-top of the internal metal transmitter shield.
4. Tested with a 50 mVP–P sinusoidal signal in the frequency range from 500 Hz to 1500 kHz on the VCC supply with the recommended power
supply filter in place. Typically less than a 0.25 dB change in sensitivity is experienced.
5. Compatible with 10 K, 10 KH, and 100 K ECL and PECL input signals.
6. The outputs are terminated to VCC –2 V.
7. Aqueous wash pressure < 110 psi.
6
Transmitter Electrical Characteristics
(TA = 0°C to +70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
85
Max.
120
0.63
Unit
mA
W
Reference
Supply Current
I
CCT
Power Dissipation
Data Input Current - Low
P
DIST
0.45
0
I
IL
I
IH
-350
mA
Data Input Current - High
Laser Reset Voltage
16
350
2.5
mA
V
V
2.7
1
CCT-reset
Receiver Electrical Characteristics
(TA = 0°C to +70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
mA
W
V
Reference
Supply Current
I
105
0.53
130
CCR
Power Dissipation
P
V
V
0.63
2
3
3
4
4
3
3
DISR
Data Output Voltage - Low
Data Output Voltage - High
Data Output Rise Time
Data Output Fall Time
Signal Detect Output Voltage - Low
Signal Detect Output Voltage - High
- V
-1.950
-1.045
-1.620
-0.740
0.40
OL
CC
- V
V
OH
CC
t
T
ns
ns
V
t
f
0.40
V
V
- V
-1.950
-1.045
-1.620
-0.740
OL
CC
- V
V
OH
CC
Notes:
1. The Laser Reset Voltage is the voltage level below which the VCCT voltage must be lowered to cause the laser driver circuit to reset from an
electrical/optical shutdown condition to a proper electrical/optical operating condition. The maximum value corresponds to the worst-case
highest VCC voltage necessary to cause a reset condition to occur. The laser safety shutdown circuit will operate properly with transmitter
VCC levels of 3.5 Vdc ≤ VCC ≤ 7.0 Vdc.
2. Power dissipation value is the power dissipated in the receiver itself. It is calculated as the sum of the products of VCC and ICC minus the sum
of the products of the output voltages and currents.
3. These outputs are compatible with 10 K, 10 KH, and 100 K ECL and PECL inputs.
4. These are 20-80ꢀ values.
7
Transmitter Optical Characteristics
(TA = 0°C to +70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
50/125 mm, NA = 0.20 Fiber
P
-9.5
-4
dBm
avg.
1
OUT
Output Optical Power
62.5/125 mm, NA = 0.275 Fiber
P
-9.5
-4
dBm
avg.
1
2
OUT
Optical Extinction Ratio
Center Wavelength
9
dB
l
830
850
860
nm
C
Spectral Width - rms
Optical Rise / Fall Time
s
0.85
0.26
-117
nm rms
ns
t /t
T
3, 4, Fig. 1
f
RIN
dB/Hz
dB
12
Coupled Power Ratio
CPR
9
5
6
Total Transmitter Jitter Added at TP2
227
ps
Receiver Optical Characteristics
(TA = 0°C to +70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
dBm avg.
Reference
Input Optical Power
P
-17
0
7
IM
62.5 m
50 m
- 12.5 dBm avg.
- 13.5 dBm avg.
8
8
Stressed Receiver Sensitivity
Stressed Receiver Eye Opening at TP4
201
ps
6, 9
10
Receiver Electrical 3dB Upper Cutoff
Frequency
1500
860
MHz
Operating Center Wavelength
Return Loss
C
770
12
nm
dB
11
Signal Detect - Asserted
Signal Detect - Deasserted
Signal Detect - Hysteresis
PA
-18
dBm avg.
dBm avg.
db
PD
-30
15
PA - PD
Notes:
1. The maximum Optical Output Power complies with the IEEE 802.3z specification, and is class 1 laser eye safe.
2. Optical Extinction Ratio is defined as the ratio of the average output optical power of the transmitter in the high (“1”) state to the low (“0”)
state. The transmitter is driven with a Gigabit Ethernet 1250 MBd 8B/10B encoded serial data pattern. This Optical Extinction Ratio is ex-
pressed in decibels (dB) by the relationship 10log(Phigh avg/Plow avg).
3. These are unfiltered 20-80ꢀ values.
4. Laser transmitter pulse response characteristics are specified by an eye diagram (Figure 1). The characteristics include rise time, fall time,
pulse overshoot, pulse undershoot, and ringing, all of which are controlled to prevent excessive degradation of the receiver sensitivity. These
parameters are specified by the referenced Gigabit Ethernet eye diagram using the required filter. The output optical waveform complies
with the requirements of the eye mask discussed in section 38.6.5 and Fig. 38-2 of IEEE 802.3z.
5. CPR is measured in accordance with EIA/TIA-526-14A as referenced in 802.3z, section 38.6.10.
6. TP refers to the compliance point specified in 802.3z, section 38.2.1.
7. The receive sensitivity is measured using a worst case extinction ratio penalty while sampling at the center of the eye.
8. The stressed receiver sensitivity is measured using the conformance test signal defined in 802.3z, section 38.6.11. The conformance test sig-
nal is conditioned by applying deterministic jitter and intersymbol interference.
9. The stressed receiver jitter is measured using the conformance test signal defined in 802.3z, section 38.6.11 and set to an average optical
power 0.5 dB greater than the specified stressed receiver sensitivity.
10. The 3 dB electrical bandwidth of the receiver is measured using the technique outlined in 802.3z, section 38.6.12.
11. Return loss is defined as the minimum attenuation (dB) of received optical power for energy reflected back into the optical fiber.
8
Table 1. Pinout Table
Pin
Symbol
Functional Description
Mounting Pins The mounting pins are provided for transceiver mechanical attachment to the circuit board.
They are embedded in the nonconductive plastic housing and are not connected to the trans-
ceiver internal circuit. They should be soldered into plated-through holes on the printed circuit
board.
1
2
V
Receiver Signal Ground
Directly connect this pin to receiver signal ground plane. (For AFBR-53D5Z, V
EER
V
)
EER = EET
RD+
RD-
SD
Receiver Data Out
RD+ is an open-emitter output circuit. Terminate this high-speed differential PECL output with
standard PECL techniques at the follow-on device input pin.
3
4
Receiver Data Out Bar
RD- is an open-emitter output circuit. Terminate this high-speed differential PECL output with
standard PECL techniques at the follow-on device input pin.
Signal Detect
Normal optical input levels to the receiver result in a logic “1”output, V , asserted. Low input
OH
optical levels to the receiver result in a fault condition indicated by a logic “0”output V
deasserted.
,
OH
Signal Detect is a single-ended PECL output. SD can be terminated with standard PECL tech-
niques via 50 W to V - 2V. Alternatively, SD can be loaded with a 270W resistor to V to
CCR
EER
conserve electrical power with small compromise to signal quality. If Signal Detect output is
not used, leave it open-circuited. This Signal Detect output can be used to drive a PECL input
on an upstream circuit, such as, Signal Detect input pr Loss of Signal-bar.
5
6
7
8
9
V
V
Receiver Power Supply
Provide +5 Vdc via the recommended receiver power supply filter circuit.
Locate the power supply filter circuit as close as possible to the V
CCR
pin.
CCR
Transmitter Power Supply
Provide +5 Vdc via the recommended transmitter power supply filter circuit.
Locate the power supply filter circuit as close as possible to the V
CCT
pin.
CCT
TD-
Transmitter Data In-Bar
Terminate this high-speed differential PECL input with standard PECL techniques at the trans-
mitter input pin.
TD+
Transmitter Data In
Terminate this high-speed differential PECL input with standard PECL techniques at the trans-
mitter input pin.
V
Transmitter Signal Ground
Directly connect this pin to the transmitter signal ground plane.
EET
1 = V
EER
1.3
NIC
2 = RD+
RX
1.0
0.8
3 = RD-
4 = SD
5 = V
CCR
0.5
6 = V
CCT
0.2
0
7 = TD-
8 = TD+
TX
-0.2
NIC
9 = V
EET
0
0.22
0.375
0.625
0.78 1.0
NORMALIZED TIME
TOP VIEW
NIC = NO INTERNAL CONNECTION (MOUNTING PINS)
Figure 1. Transmitter Optical Eye Diagram Mask.
Figure 2. Pin-Out.
9
3.3 Vdc
GND
+
C5
0.1 µF
5 Vdc
R3
68
R2
68
9
8
V
TD+
V
V
CC2 EE2
EET
50 Ω
50 Ω
CLOCK
SYNTHESIS
CIRCUIT
TD+
C9 0.01 µF
LASER
DRIVER
CIRCUIT
PECL
INPUT
OUTPUT
DRIVER
PARALLEL
TO SERIAL
CIRCUIT
TD-
TD-
7
C10 0.01 µF
R4
191
R1
191
R13
150
R12
150
L2
6
5
V
CCT
CCR
5 Vdc
AFBR-53D5Z
FIBER-OPTIC
TRANSCEIVER
HDMP-1636A/-1646A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
C2
1 µH
0.1 µF
C3
C4
+
L1
TRANSCEIVER)
V
0.1
µF
10
µF
C1
C8*
1 µH
+
0.1
µF
10 µF*
SIGNAL
DETECT
CIRCUIT
SD
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
4
3
R9
270
CLOCK
RD-
50 Ω
RD-
RECOVERY
C12 0.01 µF
PRE-
POST-
R14
CIRCUIT
INPUT
AMPLIFIER
AMPLIFIER
BUFFER
SERIAL TO
100
RD+
EER
RD+
2
1
PARALLEL
CIRCUIT
50 Ω
C11 0.01 µF
V
R11
270
R10
270
SEE HDMP-1636A/-1646A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
NOTES:
*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
Figure 3. Recommended Gigabit/sec Ethernet AFBR-53D5Z Fiber-Optic Transceiver and HDMP-1636A/1646A SERDES Integrated Circuit Transceiver Interface
and Power Supply Filter Circuits.
1.9 0.1
0.075 0.004
(2X)
∅
-A-
20.32
0.800
∅0.000
M A
0.8 0.1
0.032 0.004
∅
(9X)
20.32
0.800
∅
0.000
M A
2.54
0.100
(8X)
TOP VIEW
Figure 4. Recommended Board Layout Hole Pattern.
10
XXXX-XXXX
KEY:
A
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = AFBR-53xx
ZZZZ = 850 nꢀ
TX
RX
39.6
(1.56)
12.7
(0.50)
MAX.
4.7
(0.185)
AREA
RESERVED
FOR
PROCESS
PLUG
25.4
(1.00)
12.7
(0.50)
MAX.
2.0 0.1
(0.079 0.004)
2.5
(0.10)
SLOT WIDTH
SLOT DEPTH
+0.1
-0.05
0.25
+0.004
-0.002
(0.010
)
9.8
(0.386)
MAX.
0.51
(0.020)
3.3 0.38
(0.130 0.015)
20.32
(0.800)
15.8 0.15
(0.622 0.006)
+0.25
-0.05
0.46
+0.25
9X
∅
(
1.27
+0.010
-0.002
-0.05
2X
∅
(
0.018
)
+0.010
-0.002
0.050
)
2.54
(0.100)
8X
20.32
(0.800)
23.8
(0.937)
20.32
(0.800)
1.3
∅
(0.051)
2X
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE 0.025 ꢀꢀ UNLESS OTHERWISE SPECIFIED.
Figure 5. Package Outline Drawing for AFBR-53D5Z.
11
XXXX-XXXX
KEY:
A
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = AFBR-53xx
ZZZZ = 850 nꢀ
TX
RX
29.6
(1.16)
UNCOMPRESSED
39.6
(1.56)
12.7
(0.50)
4.7
(0.185)
MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
25.4
(1.00)
12.7
(0.50)
MAX.
2.0 0.1
(0.079 0.004)
SLOT WIDTH
+0.1
-0.05
+0.004
-0.002
0.25
2.09
(0.08)
10.2
(0.40)
UNCOMPRESSED
MAX.
(
0.010
)
9.8
(0.386)
MAX.
1.3
(0.05)
3.3 0.38
(0.130 0.015)
20.32
(0.80)
15.8 0.15
(0.622 0.006)
+0.25
-0.05
0.46
+0.25
1.27
9X ∅
+0.010
-0.002
-0.05
2X ∅
(
0.018
)
+0.010
(
0.050
)
-0.002
2.54
(0.100)
8X
20.32
(0.800)
23.8
(0.937)
20.32
(0.800)
1.3
(0.051)
2X ∅
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE 0.025 ꢀꢀ UNLESS OTHERWISE SPECIFIED.
Figure 6. Package Outline for AFBR-53D5EZ.
12
0.8
(0.032)
2X
0.8
(0.032)
2X
+0.5
-0.25
10.9
+0.02
-0.01
(0.43
)
9.4
(0.37)
27.4 0.50
(1.08 0.02)
6.35
(0.25)
MODULE
PROTRUSION
PCB BOTTOM VIEW
Figure 7. Suggested Module Positioning and Panel Cut-out for AFBR-53D5EZ.
13
XXXX-XXXX
KEY:
A
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = AFBR-53xx
ZZZZ = 850 nꢀ
TX
RX
39.6
(1.56)
12.7
(0.50)
MAX.
1.01
4.7
(0.185)
(0.40)
AREA
RESERVED
FOR
PROCESS
PLUG
25.4
(1.00)
12.7
(0.50)
29.7
(1.17)
MAX.
2.0 0.1
(0.079 0.004)
SLOT WIDTH
25.8
(1.02)
MAX.
2.2
(0.09)
SLOT DEPTH
+0.1
-0.05
+0.004
-0.002
10.2
(0.40)
0.25
MAX.
(
0.010
)
14.4
(0.57)
22.0
(0.87)
9.8
(0.386)
MAX.
3.3 0.38
(0.130 0.015)
20.32
(0.800)
15.8 0.15
(0.622 0.006)
+0.25
0.46
-0.05
+0.25
9X ∅
1.27
+0.010
-0.002
-0.05
2X ∅
(
0.018
)
+0.010
-0.002
(
0.050
)
AREA
RESERVED
2.54
8X
20.32
(0.800)
23.8
(0.937)
20.32
(0.800)
(0.100)
FOR
PROCESS
PLUG
1.3
(0.051)
2X ∅
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE 0.025 ꢀꢀ UNLESS OTHERWISE SPECIFIED.
Figure 8. Package Outline for AFBR-53D5FZ.
14
1.98
(0.078)
DIMENSION SHOWN FOR MOUNTING MODULE
FLUSH TO PANEL. THICKER PANEL WILL
RECESS MODULE. THINNER PANEL WILL
PROTRUDE MODULE.
1.27
(0.05)
OPTIONAL SEPTUM
30.2
KEEP OUT ZONE
(1.19)
0.36
(0.014)
10.82
14.73
(0.426)
(0.58)
13.82
(0.544)
26.4
(1.04)
BOTTOM SIDE OF PCB
12.0
(0.47)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE 0.025 ꢀꢀ UNLESS OTHERWISE SPECIFIED.
Figure 9. Suggested Module Positioning and Panel Cut-out for AFBR-53D5FZ.
Ordering Information
850 nm VCSEL (SX – Short Wavelength Laser)
AFBR-53D5Z
AFBR-53D5EZ
AFBR-53D5FZ
No shield, plastic housing.
Extended/protruding shield, plastic housing.
Flush shield, plastic housing.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-2172EN
V02-0457EN - April 23, 2012
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