AFBR-79EIDZ [AVAGO]
QSFP iSR4 Pluggable, Parallel Fiber-Optics Module for 40Gb Ethernet, 4 x 10Gb Ethernet and InfiniBand Applications; QSFP iSR4可插拔，并行光纤光学模块的40Gb以太网， 4× 10Gb以太网和InfiniBand应用
| 型号： | AFBR-79EIDZ |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | QSFP iSR4 Pluggable, Parallel Fiber-Optics Module for 40Gb Ethernet, 4 x 10Gb Ethernet and InfiniBand Applications |
| 文件： | 总19页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFBR-79EIDZ
QSFP+ iSR4 Pluggable, Parallel Fiber-Optics Module
for 40Gb Ethernet, 4 x 10Gb Ethernet
and InfiniBand Applications
Data Sheet
Description
Features
The Avago Technologies AFBR-79EIDZ is a Four-Channel, • Complianttothe40GBASE-SR4andXLPPISpecifications
Pluggable, Parallel, Fiber-Optic QSFP+ Transceiver for 40
Gigabit Ethernet (40GbE) applications with added capa-
bility of inter-operating with IEEE 10GBASE-SR compliant
products. It also supports 4 x 10G InfiniBand (IB) quadruple
data rate (40G-IB-QDR) application and is backward com-
patible to the 4 x 5G IB dual data rate (20G-IB-DDR) and 4
x 2.5G IB single data rate (10G-IB-SDR) applications. This
per IEEE 802.3ba-2010
• Support optical interoperability with IEEE 802.3ae
10GBASE-SR modules of various form factors such as
SFP+, XFP, and X2
• Support 40G-IB-QDR
/ 20G-IB-DDR / 10G-IB-SDR
applications
transceiver is a high performance module for short-range • Compliant to the industry standard SFF-8436 QSFP+
multi-lane data communication and interconnect ap-
plications. It integrates four data lanes in each direction
with each lane operating at 10.3125 Gbps, giving an ag-
gregated bandwidth of 40 Gbps. This transceiver can
Specification Revision 3.5
• Power Level 1: Max Power <1.5W
• High port density: 21mm horizontal port pitch
also be used for high density 10 Gigabit Ethernet appli- • Operates at 10.3125 Gbps per channel with 64b/66b
cation to allow effective port count of over 100 within
1 RU rack. It allows optical interoperability with any 10
Gigabit Ethernet (10GbE) transceiver, compliant to the
IEEE 802.3ae 10GBASE-SR specifications, of form factors
such as SFP+, XFP and X2. This transceiver is designated
as a QSFP+ iSR4 solution, where the letter i represents in-
teroperability between this QSFP+ transceiver with any
10GBASE-SR compliant modules.
encoded data for 40GbE / 10GbE applications and at
10 Gbps with 8b/10b compatible encoded data for
40G-IB-QDR application
• Links up to 100m using OM3 fiber and 150m using
OM4 fiber
• 0 to 70°C case temperature operating range
• Proven High Reliability 850 nm technology: Avago
VCSEL array transmitter and Avago PIN array receiver
This QSFP+ transceiver link length for either 40 Gigabit
Ethernet or high density 10 Gigabit Ethernet application
is up to 100 m using OM3 fiber or 150 m using OM4 fiber.
These modules are designed to operate over multimode
fiber systems using a nominal wavelength of 850nm. The
electrical interface uses a 38 contact edge type connector.
• Hot pluggable transceiver for servicing and ease of
installation
• Two Wire Serial (TWS) interface with maskable
interrupts for expanded functionality
• Utilizes a standard 12/8 lane optical fiber with MTP
The optical interface uses an 8 or 12 fiber MTP (MPO)
(MPO) optical connector for high density and thin,
light-weight cable management
connector. This module incorporates Avago Technolo-
gies proven integrated circuit and VCSEL technology to
provide reliable long life, high performance, and consis-
tent service.
Applications
• 40GbE, high density 4 x 10GbE, and 40G-IB-QDR /
Part Number Ordering Options
20G-IB-DDR / 10G-IB-SDR interconnects
AFBR-79EIDZ
QSFP+ iSR4 module with full real-time
digital diagnostic monitoring
• Datacom/Telecom switch & router connections
• Data aggregation and backplane applications
• Proprietary protocol and density applications
AFBR-79Q4EKZ*
AFBR-79Q2EKZ**
Evaluation Board
Evaluation Kit
*
Includes GUI and User Guide
** Includes GUI, User Guide, i-Port and Power Supply
Patent - www.avagotech.com/patents
Transmitter
Receiver
The optical transmitter portion of the transceiver (see
Figure 1) incorporates a 4-channel VCSEL (Vertical Cavity
Surface Emitting Laser) array, a 4-channel input buffer and
The optical receiver portion of the transceiver (see
Figure 1) incorporates a 4-channel PIN photodiode array, a
4-channel TIA array, a 4 channel output buffer, diagnostic
laser driver, diagnostic monitors, control and bias blocks. monitors, and control and bias blocks. The Rx Output
The transmitter is designed for EN 60825 and CDRH eye Buffer provides CML compatible differential outputs for
safety compliance; Class 1 out of the module. The Tx the high speed electrical interface presenting nominal sin-
Input Buffer provides CML compatible differential inputs gle-ended output impedances of 50 Ohms to AC ground
presenting a nominal differential input impedance of and 100 Ohms differentially that should be differentially
100 Ohms. AC coupling capacitors are located inside the terminated with 100 Ohms. AC coupling capacitors are
QSFP+ module and are not required on the host board. For
located inside the QSFP+ module and are not required
module control and interrogation, the control interface on the host board. Diagnostic monitors for optical input
(LVTTL compatible) incorporates a Two Wire Serial (TWS) power are implemen-ted and results are available through
interface of clock and data signals. Diagnostic monitors the TWS interface.
for VCSEL bias, module temperature, and module power
Alarm and warning thresholds are established for the
supply voltage are implemented and results are available
monitored attributes. Flags are set and interrupts gene-
through the TWS interface.
rated when the attributes are outside the thresholds. Flags
Alarm and warning thresholds are established for are also set and interrupts generated for loss of optical
the monitored attributes. Flags are set and interrupts
generated when the attributes are outside the thresholds. set even if the condition initiating the flag clears and
Flags are also set and interrupts generated for loss of input
operation resumes. All interrupts can be masked and flags
input signal (LOS). All flags are latched and will remain
signal (LOS) and transmitter fault conditions. All flags are are reset upon reading the appropriate flag register. The
latched and will remain set even if the condition initiating electrical output will squelch for loss of input signal (unless
the latch clears and operation resumes. All interrupts can
be masked and flags are reset by reading the appropriate
flag register. The optical output will squelch for loss of
squelch is disabled) and channel de-activation through
TWS interface. Status and alarm/warning information are
available via the TWS interface. To reduce the need for
input signal unless squelch is disabled. Fault detection polling, the hardware interrupt signal is provided to inform
or channel deactivation through the TWS interface will hosts of an assertion of alarm, warning and/or LOS.
disable the channel. Status, alarm/warning and fault infor-
mation are available via the TWS interface. To reduce the
need for polling, the hardware interrupt signal is provided
to inform hosts of an assertion of alarm, warning, LOS and/
or Tx fault.
TX Input Buꢀer
4 Channels
Laser Driver
4 Channels
Din[4:1][p/n] (8)
SCL
SDA
ModSelL
LPMode
ModPresL
ResetL
IntL
Diagnostic
Monitors
Control
RX Output Buꢀer
4 Channels
TIA
4 Channels
Dout[4:1][p/n] (8)
Figure 1. Transceiver Block Diagram
2
High Speed Electrical Signal Interface
Control Signal Interface
Figure 2 shows the interface between an ASIC/SerDes The module has the following low speed signals for
and the QSFP+ module. For simplicity, only one channel control and status: ModSelL, LPMode, ResetL, ModPrsL,
is shown. The high speed signal lines are AC-coupled
100 Ohm differential lines. The AC coupling is inside the serial interface scaled for 3.3 volt LVTTL. It is implemented
QSFP+ module and not required on the host board. The as a slave device. Signals and timing characteristics are
100 Ohm differential terminations are inside the QSFP+ further defined in the Control Interface section. The
IntL. In addition, there is an industry standard two wire
module for the transmitter lines and at the host ASIC/
SerDes for the Receiver lines. All transmitter and receiver
registers of the serial interface memory are defined in the
Memory Map section and corresponding Avago Technol-
electrical channels are compliant to module XLPPI specifi- ogies QSFP+ Memory Map document.
cations per IEEE 802.3ba.
Host Board
(Only one channel shown for simplicity)
Rx 1
Rx 2
Rx 3
Rx 4
Rx Out p
Rx
Rx Out n
QSFP + Module
Tx In p
ASIC (SerDes)
Tx 4
Tx 3
Tx 2
Tx 1
Tx
Tx In n
Figure 2. Application Reference Diagram
3
Digital Diagnostic Monitoring
Regulatory & Compliance
Digital diagnostic monitoring is available for AFBR-79EIDZ. Various standard and regulations apply to the modules.
Theinformationprovidesopportunityforpredictivefailure
identification, compliance prediction, fault isolation and
component monitoring.
These include eye-safety, EMC, ESD and RoHS. See the
Regulatory Section for details regarding these and com-
ponent recognition. Please note the module transmitter is
a Class 1 laser product. See Regulatory Compliance Table
for details.
Predictive Failure Identification – The diagnostic informa-
tion allows the host system to identify potential link
problems. Once identified, a “failover” technique can be
used to isolate and replace suspect devices before system
uptime is impacted.
Package Outline
The module is designed to meet the package outline
defined in the QSFP+ SFF-8436 Specification. See the
package outline and host board footprint figures (Figures
13 – 16) for details.
Compliance Prediction – The real-time diagnostic para-
meters can be monitored to alert the system when
operating limits are exceeded and compliance cannot be
ensured. As an example, the real time average receiver
optical power can be used to assess the compliance of the
cable plant and remote transmitter.
Handling and Cleaning
The transceiver module can be damaged by exposure to
current surges and over voltage events. Care should be
taken to restrict exposure to the conditions defined in
the Absolute Maximum Ratings. Wave soldering, reflow
soldering and/or aqueous wash process with the modules
on board are not recommended. Normal handling precau-
tions for electrostatic discharge sensitive devices should
be observed.
Fault Isolation – The diagnostic information can allow
the host to pinpoint the location of a link problem and
accelerate system servicing and minimize downtime.
Component Monitoring – As part of host system qualifi-
cation and verification, real time transceiver diagnostic in-
formation can be combined with system level monitoring
to ensure performance and operating environment are
meeting application requirements.
Each module is supplied with an inserted port plug for
protection of the optical ports. This plug should always be
in place whenever a fiber cable is not inserted.
Digital diagnostic monitoring for the following attributes
is implemented.
The optical connector includes recessed elements that
are exposed whenever a cable or port plug is not inserted.
Prior to insertion of a fiber optic cable, it is recommended
that the cable end be cleaned to avoid contamination from
the cable plug. The port plug ensures the optics remains
clean and no additional cleaning should be needed. In the
event of contamination, dry nitrogen or clean dry air at
less than 20 psi can be used to dislodge the contamina-
tion. The optical port features (e.g. guide pins) preclude
use of a solid instrument. Liquids are also not advised.
Transceiver module temperature – represents the module
internal temperature (lower page 0 bytes 22-23)
Transceiver module power supply – reports the module
+3.3V supply voltage (lower page 0 bytes 26-27)
Transmitter laser bias current – reports the DC laser bias
current for each transmitter channel (lower page 0 bytes
42-43 for ch.1, bytes 44-45 for ch.2, bytes 46-47 for ch.3,
bytes 48-49 for ch.4)
Receiver input power – reports the average input optical
power for each receiver channel (lower page 0 bytes 34-35
for ch.1, bytes 36-37 for ch.2, bytes 38-39 for ch.3, bytes
40-41 for ch.4)
All diagnostic monitor attributes are two-byte fields. To
maintain coherency, the host must access these with
single two-byte read sequences.
For each monitored attribute, alarm and warning
thresholds are established. Flags are set and interrupts
generated when the attributes are outside the thresh-
olds. All flags are latched and will remain set even if the
condition initiating the flag clears. A mask bit that can be
set to prevent assertion of interrupt for each individual
attribute exists for every monitor flag. Entries in the mask
fields are volatile.
4
Absolute Maximum Ratings
Stress in excess of any of the individual Absolute Maximum Ratings can cause immediate catastrophic damage to the
module even if all other parameters are within recommended operating conditions. It should not be assumed that
limiting values of more than one parameter can be applied to the module concurrently. Exposure to any of the Absolute
Maximum Ratings for extended periods can adversely affect reliability.
Parameter
Symbol
Ts
Min
-40
Max
85
Units
°C
V
Reference
Storage Temperature
3.3 V Power Supply Voltage
Data Input Voltage – Single Ended
Data Input Voltage – Differential
Control Input Voltage
Control Output Current
Relative Humidity
Vcc
-0.5
-0.5
3.6
Vcc+0.5
V
|Vdip - Vdin
|
1.0
V
1
Vi
-0.5
-20
5
Vcc+0.5, 3.6
V
Io
20
95
mA
%
RH
Note:
1. This is the maximum voltage that can be applied across the differential inputs without damaging the input circuitry.
Recommended Operating Conditions
Recommended Operating Conditions specify parameters for which the optical and electrical characteristics hold
unless otherwise noted. Optical and electrical characteristics are not defined for operation outside the Recommended
Operating Conditions, reliability is not implied and damage to the module may occur for such operation over an
extended period of time.
Parameter
Case Temperature
Symbol
Tc
Min
0
Typ
40
Max
70
Units
°C
Reference
1
3.3 V Power Supply Voltage
Signal Rate per Channel
Control* Input Voltage High
Control* Input Voltage Low
Two Wire Serial (TWS) Interface Clock Rate
Power Supply Noise
Vcc
3.135
3.3
3.465
V
10.3125
GBd
V
2
Vih
Vil
2
Vcc+.3
0.8
-0.3
V
400
50
kHz
mVpp
Ohms
3
4
Receiver Differential Data Output Load
100
Fiber Length: 2000 MHz∙km 50µm MMF (OM3)
Fiber Length: 4700 MHz∙km 50µm MMF (OM4)
0.5
0.5
100
150
m
m
*
Control signals, LVTTL (3.3 V) compatible
Notes:
1. The position of case temperature measurement is shown in Figure 8.
2. 64b/66b coding is assumed
3. Power Supply Noise is defined as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power
supply filter with the module and recommended filter in place. Voltage levels including peak-to-peak noise are limited to the recommended
operating range of the associated power supply. See Figure 9 for recommended power supply filter.
4. Channel insertion loss of 1.9dB (OM3) / 1.5dB (OM4) included with 1.5dB (OM3) / 1dB (OM4) allocated for connection and splice loss.
Transceiver Electrical Characteristics*
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
Symbols
Min
Typ
Max
1.5
Units
W
Reference
Transceiver Power Consumption
Transceiver Power Supply Current
Transceiver Power On Initialization Time
475
2000
mA
ms
tpwr init
1
*
For control signal timing including ModSelL, LPMode, ResetL, ModPrsL, IntL, SCL and SDA see Control Interface Section.
Note:
1. Power On InitializationTime is the time from when the supply voltages reach and remain above the minimum Recommended Operating Conditions
to the time when the module enables TWS access. The module at that point is fully functional.
5
Transmitter Electrical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
Symbol
Min
Typ
Max
Units Notes
LOS Assert Threshold: Tx Data Input ΔVdi pp los
Differential Peak-to-Peak Voltage
Swing
50
mVpp
LOS Hysteresis
0.5
4
dB
1
Parameter
(From Table 86A-2 of IEEE 802.3ba)
Test Point*
Min
Typ
Max
Units Notes/Conditions
Single ended input voltage
tolerance [2]
TP1a
-0.3
4
V
Referred to TP1 signal
common
AC common mode input voltage
tolerance
TP1a
TP1
15
mV
dB
RMS
Differential input return loss
See IEEE
802.3ba
86A.4.1.1
10 MHz to 11.1 GHz
10 MHz to 11.1 GHz
Differential to common-mode
input return loss
TP1
10
dB
J2 Jitter tolerance
J9 Jitter tolerance
TP1a
TP1a
TP1a
0.17
0.29
0.07
UI
UI
UI
Defined in IEEE 802.3ba spec
Defined in IEEE 802.3ba spec
Data Dependent Pulse Width
Shrinkage (DDPWS) tolerance
Eye Mask Coordinates:
X1, X2
Y1, Y2
TP1a
SPECIFICATION VALUES
0.11, 0.31
Hit Ratio = 5x10-5
UI
mV
95, 350
*
See Figure 6 for Test Point definitions.
Note:
1. LOS Hysteresis is defined as 20*Log(LOS De-assert Level / LOS Assert Level).
2. The single ended input voltage tolerance is the allowable range of the instantaneous input signals
Y2
Y1
0
-Y1
-Y2
X2
1-X2
1-X1
X1
0
1
Time (UI)
Figure 3. Electrical Eye Mask Coordinates at Hit ratio 5 x 10-5 hits per sample
6
Receiver Electrical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
(From Table 86A-3 of IEEE 802.3ba)
Single ended output voltage
AC common mode voltage (RMS)
Termination mismatch at 1MHz
Differential output return loss
Test Point*
TP4
Min
Typ
Max
4
Units Notes/Conditions
-0.3
V
mV
%
Referred to signal common
TP4
7.5
5
RMS
TP4
TP4
See IEEE
802.3ba
86A.4.2.1
dB
10 MHz to 11.1 GHz
Common-mode output return loss
TP4
See IEEE
802.3ba
86A.4.2.2
dB
10 MHz to 11.1 GHz
Output transition time 20% to 80%
J2 Jitter output
TP4
TP4
TP4
TP4
28
ps
UI
UI
0.42
0.65
J9 Jitter output
Eye Mask coordinates:
X1, X2
Y1, Y2
SPECIFICATION VALUES
0.29, 0.5
Hit Ratio = 5x10-5
UI
mV
150, 425
*
See Figure 6 for Test Point definitions.
Y2
Y1
0
-Y1
-Y2
0
X1
X2
1-X1
1.0
Normalized Time [UI]
Figure 4. Rx Electrical Eye Mask Coordinates (TP4) at Hit ratio 5 x 10-5 hits per sample
7
Transmitter Optical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
(From Table 86-6 of IEEE 802.3ba)
Test Point*
TP2
Min
Typ
Max
860
0.65
Units Notes/Conditions
Center wavelength
840
850
nm
RMS spectral width
TP2
nm
RMS Spectral Width is the stan-
dard deviation of the spectrum
Average launch power, each lane
TP2
TP2
-7.6
-5.6
-1
3
dBm
Optical Modulation Amplitude
(OMA) each lane
dBm Even if the TDP<0.9 dB, the OMA
minimum must exceed -5.6 dBm
Difference in launch power
between any two lanes (OMA)
TP2
4
4
dB
Peak power, each lane
TP2
TP2
dBm
dBm
Launch power in OMA minus TDP,
each lane
-6.5
3
Transmitter and dispersion
penalty (TDP), each lane
TP2
3.5
12
dB
Extinction ratio
TP2
TP2
TP2
dB
dB
Optical return loss tolerance
Encircled flux
≥ 86% at 19 μm,
≤ 30% at 4.5 μm
If measured into type A1a.2
50 μm fiber in accordance
with EN 61280-1-4
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3
TP2
TP2
SPECIFICATION VALUES
0.23, 0.34, 0.43, 0.27, 0.35, 0.4
Hit Ratio = 5x10-5
UI
Average launch power of OFF
transmitter, each lane
-30
dBm
*
See Figure 6 for Test Point definitions.
1+Y3
1
X1 = 0.23
X2 = 0.34
X3 = 0.43
Y1 = 0.27
Y2 = 0.35
Y3 = 0.40
1-Y1
1-Y2
0.5
Y2
Y1
0
-Y3
0
X1
X2
X3 1-X3 1-X2
1-X1
1.0
Normalized Time [UI]
Figure 5. Transmitter eye mask definitions at Hit ratio 5 x 10-5 hits per sample
8
Receiver Optical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
(From Table 86-8 of IEEE 802.3ba)
Center wavelength, each lane
Damage Threshold1
Test Point*
TP3
Min
840
3.4
Typ
Max
Units Notes/Conditions
850
860
nm
TP3
dBm
dBm
Maximum Average power at receiver TP3
input, each lane
2.4
Receiver Reflectance
TP3
TP3
-12
3
dB
Optical Modulation Amplitude
(OMA), each lane
dBm
Stressed receiver sensitivity in OMA, TP3
each lane
-5.4
dBm Measured with conformance test
signal at TP3 for BER = 10e-12
Conditions of stressed receiver
sensitivity: 2
TP3
TP3
TP3
TP3
Vertical Eye Closure Penalty,
each lane
1.9
0.30
0.47
-0.4
dB
UI
UI
Stressed eye J2 Jitter,
each lane
Stressed eye J9 Jitter,
each lane
OMA of each aggressor lane
Peak power, each lane
LOS Assert
TP3
TP3
TP3
TP3
TP3
dBm
dBm
dBm
dBm
dB
4
-30
0.5
LOS De-Assert – OMA
LOS Hysteresis
-7.5
*
See Figure 6 for Test Point definitions.
Note:
1. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one
lane. The receiver does not have to operate correctly at this input power
2. Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the
receiver. The apparent discrepancy between VECP and TDP is because VECP is defined at eye center while TDP is defined with 0.15 UI offsets of
the sampling instant
ASIC/
SerDes
ASIC/
SerDes
QSFP + TX
QSFP + RX
Fiber
TP 3
TP 0
TP 1 TP 1a
TP 2
TP 4a TP 4
TP 5
TP0 : Host ASIC transmitter output at ASIC package contact on the Host board
TP1 : Host ASIC transmitter output across the Host Board at the input side of the Host QSFP+ electrical connector
TP1a : Host ASIC transmitter output across the Host board at the output side of the Host QSFP+ electrical connector
TP2 : QSFP+ transmitter optical output at the end of a 2m to 5m patch cord
TP3 : QSFP+ receiver optical input at the end of the fiber
TP4a : QSFP+ receiver electrical output at the input side of the Host QSFP+ electrical connector
TP4 : QSFP+ receiver electrical output at the output side of the Host QSFP+ electrical connector
TP5 : Host ASIC receiver input at ASIC package contact on the Host board
Figure 6. Test point definitions
9
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge
(ESD) to the Electrical
Contacts
JEDEC Human Body Model (HBM)
(JESD22-A114-B)
Transceiver module withstands 1kV on high
speed pins and 2kV on low speed pins
JEDEC Charge Device Model (CDM)
(JESD22-C101D)
Transceiver module withstands 250V
Electrostatic Discharge (ESD) GR1089
to Optical connector
10 discharges of 8 kV on the electrical faceplate
with device inserted into a panel
Electrostatic Discharge
(ESD) to Optical Connector
Variation of EN 61000-4-2
Air discharge of 15kV(min) to connector w/o
damage
Electromagnetic Interference FCC Part 15 CENELEC EN55022
Typically passes with 10 dB margin. Actual
performance dependent on enclosure design
(EMI)
(CISPR 22A) VCCI Class 1
Immunity
Variation of EN 61000-4-3
Typically minimum effect from a 10V/m field
swept from 80 MHz to 1 GHz applied to the
module without a chassis enclosure
Laser Eye Safety and
Equipment Type Testing
EN 60825-1:2007 and
EN 60950-1:2006+A11+A1+A12
EN AEL & US FDA CDRH Class 1
Component Recognition
Underwriters Laboratories and Canadian
Standards Association Joint Component
Recognition for Information Technology
Equipment including Electrical Business
Equipment
UL File Number: E173874
RoHS Compliance
BS EN 1122:2001 Mtd B by ICP for Cadmium,
EPA Method 3051A by ICP for Lead and
Mercury, EPA Method 3060A & 7196A by
UV/Vis Spectrophotometry for Hexavalent
Chromium. EPA Method 3540C/3550B by
GC/MS for PPB and PBDE
Less than 100 ppm of cadmium,
Less than 1000 ppm of lead, mercury,
hexavalent chromium, polybrominated
biphenyls, and polybrominated biphenyl esters.
BS EN method by ICP and EPA methods by ICP,
UV/Vis Spectrophotometry and GC/MS.
10
QSFP+ Transceiver Pad Layout
38 GND
37 TX1n
36 TX1p
35 GND
34 TX3n
33 TX3p
32 GND
31 LPMode
30 Vcc1
29 VccTx
28 IntL
GND
1
TX2n
TX2p
GND
2
3
4
TX4n
TX4p
GND
5
6
7
ModSelL
ResetL
VccRx
SCL
8
9
10
11
12
13
14
15
16
17
18
19
27 ModPrsL
26 GND
25 RX4p
24 RX4n
23 GND
22 RX2p
21 RX2n
20 GND
SDA
GND
RX3p
RX3n
GND
RX1p
RX1n
GND
Top Side
Viewed from Top
Bottom Side
Viewed from Bottom
Figure 7. QSFP+ Transceiver Pad Layout
Pin
1
2
3
4
5
6
7
8
Logic
Symbol
GND
Tx2n
Tx2p
GND
Tx4n
Tx4p
GND
ModSelL
ResetL
Vcc Rx
SCL
Description
Plug Sequence
Notes
Ground
1
3
3
1
3
3
1
3
3
2
3
3
1
3
3
1
3
3
1
1
3
3
1
3
3
1
3
3
2
2
3
1
3
3
1
3
3
1
1
CML-I
CML-I
Transmitter Inverted Data Input
Transmitter Non-Inverted Data Input
Ground
Transmitter Inverted Data Input
Transmitter Non-Inverted Data Input
Ground
1
1
2
1
1
CML-I
CML-I
LVTTL-I
LVTTL-I
Module Select
Module Reset
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
+3.3V Power supply receiver
2-wire serial interface clock
2-wire serial interface data
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
Receiver Non-Inverted Data Output
Receiver Inverted Data Output
Ground
LVCMOS-I/O
LVCMOS-I/O
SDA
GND
CML-O
CML-O
Rx3p
Rx3n
GND
Rx1p
Rx1n
GND
CML-O
CML-O
1
1
GND
Ground
CML-O
CML-O
Rx2n
Rx2p
GND
Rx4n
Rx4p
GND
ModPrsL
IntL
Vcc Tx
Vcc1
LPMode
GND
Tx3p
Tx3n
GND
Tx1p
Tx1n
GND
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Receiver Inverted Data Output
Receiver Non-Inverted Data Output
Ground
Module Present
Interrupt
+3.3V Power supply transmitter
+3.3V Power Supply
Low Power Mode
1
1
CML-O
CML-O
LVTTL-O
LVTTL-O
2
2
LVTTL-I
Ground
1
1
1
CML-I
CML-I
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
CML-I
CML-I
Notes:
1. GND is the symbol for signal supply (power) common for the QSFP+ module. All are common within the
QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect
these directly to the host board signal-common ground plane
2. Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently.
11
Figure 8. Case Temperature Measurement Point
1 µH
22 µF
1 µH
22 µF
Vcc Tx
0.1 µF
Vcc_host =
3.3 Volt
GND
Vcc Rx
GND
0.1 µF
0.1 µF
0.1 µF 22 µF
1 µH
22 µF
Vcc1
GND
QSFP+ Module
Figure 9. Recommended Power Supply Filter
VCC25
VCC33
50 Ω
DPx
Signal Path (Pos)
VCC25
VCC33
50 Ω
DNx
Signal Path (Neg)
Figure 10. Transmitter Data Input Equivalent Circuit
12
VCC25
VCC25
VCC33
50 Ω
50 Ω
Doutp
Doutn
Signal Path (Neg)
Signal Path (Pos)
Figure 11. Receiver Data Output Equivalent Circuit
tHIGH
START
RESTART
STOP
START
tR
tLOW
tF
SCL
tHD,SDA
tHD,DAT
tSU,DAT
tBUF
tSU,STO
tF
tBUF
tSU,SDA
SDA In
tR
Figure 12. TWS Interface Bus Timing
13
Package Outline, Host PCB Footprint and Bezel Design
71
18.5
18.35
3
1
53
12.9
8.50
8.20
All dimensions in mm
Figure 13. Mechanical Package Outline
X
BASIC
37.00 MAX.
Y
11.30 MIN.
10.60
Ø1.05 0.05
12 PLC
Ø0.10 A K
7.60
3.10
BASIC
M
S
S
L
9.00
6 PLC
3.40
17.90 REF.
22.15
7.20
16.80
19.00
1.10
C
7.60
Cross-hatched area denotes
component and trace keep-out
(except chassis ground)
3.10
This area denotes
component keep-out
(traces allowed)
Notes:
1. Datum X & Y are established by the customer’s fiducial
2. Datum A is the top surface of the host board
3. Location of the edge of PCB is application specific
4. Finished hole size
All dimensions in mm
Figure 14. QSFP+ Host Board Mechanical Footprint
14
2.51
1
Ø1.55 0.05
Ø0.05 A X K
5.18
S
1
3
0.80
0.20
7.40
7.00
Datum Axis C
15.02 MAX.
19.20 MAX.
16.80
2
0.20
3
22.15
C
0.35 0.03
0.05 A L-K C
Ø1.55 0.05
Ø0.05 A X Y
1.80 0.03
0.05 A C L-K
Notes:
1. Centerline of Pad
2. Surface traces permitted within this length
3. Indicated holes are optional
All dimensions in mm
Figure 15. QSFP+ Host Board Mechanical Footprint Detail
B
1
2
21 0.1
43 0.3
Bezel
R0.3 TYP
10.15 0.1
A
TYP
0.15 0.1
(Bottom of cut-out
in bezel to top of
PC Board)
2
37 MAX
20 0.1 TYP
Notes:
1
Minimum pitch dimension for individual cages.
Dimension baseline is datum K or L .
2
All dimensions in mm
3. Not recommended for PCI applications.
Figure 16. Host Board Bezel Design
15
Control Interface
LPMode
The control interface combines dedicated signal lines for Low power mode. When held high by host, the module
ModSelL, LPMode, ResetL, ModPrsL, IntL with two-wire
serial (TWS), interface clock (SCL) and data (SDA), signals
is held at low power mode. When held low by host, the
module operates in the normal mode. For class 1 power
to provide users rich functionality over an efficient and level modules (1.5W), low power mode has no effect.
easily used interface. The TWS interface is implemented
ModPrsL
as a slave device and compatible with industry standard
two-wire serial protocol. It is scaled for 3.3 volt LVTTL.
Outputs are high-z in the high state to support busing of
these signals. Signal and timing characteristics are further
defined in the Control I/O Characteristics section. For
more details, see QSFP+ SFF-8436.
ModPrsL is pulled up to Vcc_Host on the host board and
grounded in the module. The ModPrsL is asserted “Low”
when module is inserted into the host connector, and
deasserted “High” when the module is physically absent
from the host connector.
ModSelL
IntL
The ModSelL is an input signal. When held low by the
host, the module responds to 2-wire serial communica-
tion commands. The ModSelL allows the use of multiple
QSFP+ modules on a single 2-wire interface bus. When
the ModSelL is “High”, the module will not respond to or
acknowledge any 2-wire interface communication from
the host. ModSelL signal input node is biased to the“High”
state in the module. In order to avoid conflicts, the host
system shall not attempt 2-wire interface communica-
tions within the ModSelL de-assert time after any QSFP+
module is deselected. Similarly, the host must wait at least
for the period of the ModSelL assert time before communi-
cating with the newly selected module. The assertion and
de-assertion periods of different modules may overlap as
long as the above timing requirements are met.
IntL is an output signal. When“Low”, it indicates a possible
module operational fault or a status critical to the host
system. The host identifies the source of the interrupt
using the 2-wire serial interface. The IntL signal is an
open collector output and must be pulled to host supply
voltage on the host board. A corresponding soft status
IntL signal is also available in the transceiver memory
page 0 address 2 bit 1.
Soft Status and Control
A number of soft status signals and controls are available
in the AFBR-79EIDZ transceiver memory and accessible
through the TWS interface. Some soft status signals
include receiver LOS, optional transmitter LOS, transmitter
fault and diagnostic monitor alarms and warnings. Some
soft controls include transmitter disable (Tx_Dis), receiver
output disable (Rx_Dis), transmitter squelch disable (Tx_
SqDis), receiver squelch disable (Rx_SqDis), and masking
of status signal in triggering IntL. All soft status signals
and controls are per channel basis. All soft control entries
are volatile.
ResetL
The ResetL signal is pulled to Vcc in the QSFP+ module.
A low level on the ResetL signal for longer than the
minimum pulse length (t_Reset_init) initiates a complete
module reset, returning all user module settings to their
default state. Module Reset Assert Time (t_init) starts on
the rising edge after the low level on the ResetL pin is
released. During the execution of a reset (t_init) the host
shall disregard all status bits until the module indicates a
completion of the reset interrupt. The module indicates
this by posting an IntL signal with the Data_Not_Ready bit
negated. Note that on power up (including hot insertion)
the module will post this completion of reset interrupt
without requiring a reset.
16
Receiver LOS
Transmitter Disable
The receiver LOS status signal is on page 0 address 3 bits The transmitter disable control is on page 0 address 86
0-3 for channels 1-4 respectively. Receiver LOS is based bits 0-3 for channels 1-4 respectively. When in transmit-
on input optical modulation amplitude (OMA). This status ter fault, toggling the transmitter disable bit signals the
register is latched and it is cleared on read.
transmitter channel to exit the fault state and restores the
channel function, unless fault condition persists.
Transmitter LOS
Receiver Disable
The transmitter LOS status signal is on page 0 address 3
bits 4-7 for channels 1-4 respectively. Transmitter LOS is
based on input differential voltage. This status register is
latched and it is cleared on read.
The receiver disable control is on page 3 address 241 bits
4-7 for channels 1-4 respectively.
Transmitter Squelch Disable
Transmitter Fault
The transmitter squelch disable control is on page 3
The transmitter fault status signal is on page 0 address address 240 bits 0-3 for channels 1-4 respectively. AFBR-
4 bits 0-3 for channels 1-4 respectively. Conditions that 79EIDZ transceivers have transmitter output squelch
lead to transmitter fault include laser fault, which occurs function enabled as default.
generally at transceiver end of life. In addition, unbal-
Receiver Squelch Disable
anced electrical input data can cause transmitter fault
to be triggered. When fault is triggered, the correspond-
ing transmitter channel output will be disabled. Module
reset or toggling of soft transmitter disable can restore
the transmitter channel function unless fault condition
persists. This status register is latched and it is cleared on
read.
The receiver squelch disable control is on page 3 address
240 bits 4-7 for channels 1-4 respectively. AFBR-79EI-
DZ transceivers have receiver output squelch function
enabled as default.
17
I/O Timing for Control and Status Functions
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted. Typical
values are for Tc = 40°C, Vcc = 3.3 V
Parameter
Symbol
Min Typ Max
Units Reference
Initialization Time
t_init
2000
ms
Time from power on, hot plug or rising edge of Reset until the
module is fully functional. This time does not apply to non Power
level 0 modules in the Low Power state
LPMode Assert Time
Interrupt Assert Time
Interrupt De-assert Time
ton_LPMode
ton_IntL
100
200
500
μs
ms
μs
Time from assertion of LPMode until the module power
consumption enters power level 1
Time from occurrence of condition triggering IntL until
Vout:IntL=Vol
Toff_IntL
Time from clear on read operation of associated flag until
Vout:IntL=Voh. This includes deassert times for RX LOS, TX Fault
and other flag bits
Reset Init Assert Time
Reset Assert Time
t_reset_init
t_reset
2
μs
A Reset is generated by a low level longer than the minimum reset
pulse time present on the ResetL pin
2000
2000
2000
ms
ms
ms
Time from rising edge on the ResetL pin until the module is fully
functional
Serial Bus Hardware
Ready Time
t_serial
Time from power on until module responds to data transmission
over the 2-wire serial bus
Monitor Data Ready Time
t_data
Time from power on to data not ready, bit 0 of Byte 2, deasserted
and IntL asserted
RX LOS Assert Time
TX Fault Assert Time
Flag Assert Time
ton_los
100
200
200
ms
ms
ms
Time from RX LOS state to RX LOS bit set and IntL asserted
Time from TX Fault state to TX fault bit set and IntL asserted
ton_Txfault
ton_Flag
Time from occurrence of condition triggering flag to associated
flag bit set and IntL asserted.
Mask Assert Time
ton_Mask
toff_Mask
ton_Pdown
100
100
100
ms
ms
ms
Time from mask bit set until associated IntL assertion is inhibited
Time from mask bit cleared until associated IntL operation resumes
Mask Deassert TIme
Power Set Assert Time
Time from P_Down bit set until module power consumption
enters power level 1
Power Set Deassert Time
RX Squelch Assert Time
toff_Pdown
ton_Rxsq
300
80
ms
Time from P_Down bit cleared until the module is fully functional
μs
Time from loss of RX input signal until the squelched output
condition is reached
RX Squelch Deassert Time
TX Squelch Assert Time
TX Squelch Deassert Time
TX Disable Assert Time
TX Disable Deassert Time
toff_Rxsq
ton_Txsq
toff_Txsq
ton_txdis
toff_txdis
ton_rxdis
toff_rxdis
ton_sqdis
80
μs
Time from resumption of RX input signals until normal RX output
condition is reached
400
400
100
400
100
100
100
100
ms
ms
ms
ms
ms
ms
ms
ms
Time from loss of TX input signal until the squelched output
condition is reached
Time from resumption of TX input signals until normal TX output
condition is reached
Time from TX Disable bit set until optical output falls below 10%
of nominal
Time from TX Disable bit cleared until optical output rises above
90% of nominal
RX Output Disable
Assert Time
Time from RX Output Disable bit set until RX output falls below
10% of nominal
RX Output Disable Deassert
Time
Time from RX Output Disable bit cleared until RX output rises
above 90% of nominal
Squelch Disable Assert Time
This applies to RX and TX Squelch and is the time from bit set until
squelch functionality is disabled
Squelch Disable Deassert Time toff_sqdis
This applies to RX and TX Squelch and is the time from bit cleared
until squelch functionality is enabled
18
Memory Map
The memory is structured as a single address, multiple page approach. The address is given as A0xh. The structure of
the memory is shown in Figure 17. The memory space is arranged into a lower, single page, address space of 128 bytes
and multiple upper address space pages of 128 bytes each. This structure permits timely access to addresses in the
lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings
are available with the Page Select function. For a more detailed description of the QSFP+ memory map see the QSFP+
SFF-8436 Specification or the Avago Technologies QSFP+ Memory Map document.
2-wire serial address, 1010000x (A0h)"
0
2
(3 Bytes)
(19 Bytes)
(12 Bytes)
(48 Bytes)
(4 Bytes)
(12 Bytes)
(2 Bytes)
(7 Bytes)
(12 Bytes)
(4 Bytes)
(4 Bytes)
(1 Bytes)
ID and status
Interrupt Flags
Module Monitors
Channel Monitors
Reserved
3
21
22
33
34
81
82
85
86
Control
97
98
Reserved
99
100
106
107
118
119
122
123
126
127
127
Module and
Channel Mask
Reserved
Password Change
Entry Area (Optional)
Password Entry
Area (Optional)
Page Select Byte
Page 00
Page 01 (Optional)
Page 02 (Optional)
User EEPROM Data
Page 03
128
191
192
223
224
255
128
128
129
129
(1 Bytes)
(1 Bytes)
128
255
(128 Bytes)
128
175
176
223
224
225
(48 Bytes)
(48 Bytes)
(2 Bytes)
(16 Bytes)
(12 Bytes)
(2 Bytes)
(64 Bytes)
(32 Bytes)
Base ID Fields
CC_APPS
Module Threshold
Channel Threshold
Reserved
Extended ID
AST Table Length (TL)
130 Application Code (2 Bytes)
131
(32 Bytes)
Vendor Speci-c ID
Entry 0
132 Application Code (2 Bytes)
226 Vendor Speci-c
241 Channel Controls
133
Entry 1
242
253
254
255
Channel Monitor
other entries
Masks
254 Application Code (2 Bytes)
255
Reserved
Entry TL
Figure 17. Two-Wire Serial Address A0xh Page Structure
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-2830EN - May 27, 2013
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