HCMS-2902 [AVAGO]
High Performance CMOS 5 x 7 Alphanumeric Displays; 高性能CMOS 5× 7文数字显示
| 型号： | HCMS-2902 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | High Performance CMOS 5 x 7 Alphanumeric Displays |
| 文件： | 总16页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCMS-29xx Series
High Performance CMOS 5 x 7 Alphanumeric Displays
DataSheet
Description
Features
The HCMS-29xx series are high performance, easy • Easy to use
to use dot matrix displays driven by on-board CMOS
ICs. Each display can be directly interfaced with a
microprocessor, thus eliminating the need for
cumbersome interface components. The serial IC
interface allows higher character count information
displays with a minimum of data lines. A variety of
colors, font heights, and character counts gives
designers a wide range of product choices for their
specific applications and the easy to read 5 x 7 pixel
format allows the display of uppercase, lower case,
Katakana,andcustomuser-definedcharacters.These
displays are stackable in the x- and y- directions,
making them ideal for high character count displays.
• Interfaces directly with microprocessors
• 0.15" character height in 4, 8, and 16 (2x8) character
packages
• 0.20" character height in 4 and 8 character packages
• Rugged X- and Y-stackable package
• Serial input
• Convenient brightness controls
• Wave solderable
• Offered in five colors
• Low power CMOS technology
• TTL compatible
Applications
• Telecommunications equipment
• Portable data entry devices
• Computer peripherals
• Medical equipment
• Test equipment
• Business machines
• Avionics
• Industrial controls
Device Selection Guide
AlGaAs
HCMS-
HER
HCMS-
Orange
HCMS-
Yellow
HCMS-
Green
HCMS-
Package
Drawing
Description
1 x 4 0.15" Character
1 x 8 0.15" Character
2 x 8 0.15" Character
1 x 4 0.20" Character
1 x 8 0.20" Character
2905
2915
2925
2965
2975
2902
2912
2922
2962
2972
2904
2914
2924
2964
2974
2901
2911
2921
2961
2971
2903
2913
2923
2963
2973
A
B
C
D
E
ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID
STATIC DISCHARGE.
HCMS-290x
17.78 (0.700) MAX.
PIN FUNCTION
ASSIGNMENT TABLE
PIN # FUNCTION
4.45 (0.175) TYP.
2.22 (0.087) SYM.
1
2
3
4
5
6
7
8
9
DATA OUT
OSC
V LED
DATA IN
RS
CLK
CE
12
1
1
2
3
4
BLANK
GND
3.71 (0.146) TYP.
10.16 (0.400) MAX.
10 SEL
11 V LOGIC
12 RESET
2.11 (0.083) TYP.
DATE CODE
PIN # 1 IDENTIFIER
LIGHT INTENSITY CATEGORY
COLOR BIN
COUNTRY OF ORIGIN
0.25
(0.010)
PART NUMBER
5.08
(0.200)
HCMS-290X X Z
YYWW
COO
4.32
(0.170)
TYP.
0.51 (0.020)
PIN # 1
2.54
SYM.
1.27
(0.050)
SYM.
(0.100)
2.54 ± 0.13
(0.100 ± 0.005)
(NON ACCUM.)
TYP.
7.62
(0.300)
0.51 ± 0.13
(0.020 ± 0.005)
TYP.
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
HCMS-291x
35.56 (1.400) MAX.
2.22 (0.087) SYM.
4.45
(0.175)
TYP.
PIN FUNCTION
ASSIGNMENT TABLE
26
PIN # FUNCTION
3.71
TYP.
10.16 (0.400) MAX.
0
1
2
3
4
5
6
7
(0.146)
1
2
3
NO PIN
NO PIN
V LED
3
4
5
6
7
8
9
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
2.11 (0.083) TYP.
DATE CODE (YEAR, WEEK)
PIN # 1 IDENTIFIER
INTENSITY CATEGORY
COLOR BIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PART NUMBER
COUNTRY OF ORIGIN
0.25
(0.010)
HCMS-291X
YYWW
X
Z
COO
5.08 (0.200)
0.51
(0.020)
4.32
(0.170)
TYP.
V LOGIC
NO PIN
RESET
OSC
2.54
SYM.
(0.100)
0.51 ± 0.13
(0.020 ± 0.005)
1.27
(0.050)
DATA OUT
TYP.
SYM.
2.54 ± 0.13
(0.100 ± 0.005)
(NON ACCUM.)
7.62
(0.300)
TYP.
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
2
HCMS-292x
PIN FUNCTION ASSIGNMENT TABLE
PIN # FUNCTION PIN # FUNCTION
35.56 (1.400) MAX.
1B
2B
3B
4B
5B
6B
7B
8B
9B
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
1A
2A
3A
4A
5A
6A
7A
8A
9A
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
2.22 (0.088) SYM.
4.45 (0.175) MAX.
26B
26A
10B V LED
11B NO PIN
12B NO PIN
13B NO PIN
14B DATA IN
15B RS
16B NO PIN
17B CLOCK
18B CE
19B BLANK
20B GND LOGIC
21B SEL
22B V LOGIC
23B NO PIN
24B RESET
25B OSC
ROW B
10A V LED
11A NO PIN
12A NO PIN
13A NO PIN
14A DATA IN
15A RS
16A NO PIN
17A CLOCK
18A CE
19A BLANK
20A GND LOGIC
21A SEL
22A V LOGIC
23A NO PIN
24A RESET
25A OSC
0
8
1
9
2
3
4
5
6
7
4.83
(0.190)
3B
3A
19.81 (0.780) MAX.
9.65 (0.380)
ROW A
10
11
12
13
14
15
3.71 (0.146) TYP.
2.11 (0.083) TYP.
DATE CODE (YEAR, WEEK)
INTENSITY CATEGORY
PIN # 1 IDENTIFIER
26B DATA OUT
26A DATA OUT
COLOR BIN
PART NUMBER
COUNTRY OF ORIGIN
0.25
(0.010)
HCMS-292X
YYWW
X
Z
COO
5.08 (0.200)
0.51
(0.020)
2.54
SYM.
1.27
(0.050)
(0.100)
0.51 ± 0.13
(0.020 ± 0.005)
TYP.
2.03
(0.080)
2.54 ± 0.13
(0.100 ± 0.005)
(NON ACCUM.)
TYP.
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
HCMS-296x
PIN FUNCTION
ASSIGNMENT TABLE
PIN # FUNCTION
21.46 (0.845) MAX.
1
2
DATA OUT
OSC
3
4
5
V LED
DATA IN
RS
2.67 (0.105) SYM.
2.54 (0.100) TYP.
6
7
CLK
CE
8
9
BLANK
GND
4.57
(0.180)
0
1
2
3
TYP.
10
11
12
SEL
V LOGIC
RESET
11.43 (0.450) MAX.
5.36 (0.211) TYP.
PIN # 1 IDENTIFIER
DATE CODE (YEAR, WEEK)
INTENSITY CATEGORY
COLOR BIN
PART NUMBER
0.25
(0.010)
COUNTRY OF ORIGIN
HCMS-296X
YYWW
X Z
COO
5.31
(0.209)
3.71
TYP.
(0.146)
0.50
(0.020)
0.169
SYM.
(4.28)
0.51 ± 0.13
(0.020 ± 0.005)
TYP.
0.072
(1.83)
SYM.
2.54 ± 0.13
TYP.
(0.100 ± 0.005)
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
3
HCMS-297x
42.93 (1.690) MAX.
2.67 (0.105) SYM.
5.36 (0.211) TYP.
PIN FUNCTION
ASSIGNMENT TABLE
26
4.57
TYP.
PIN # FUNCTION
1
2
3
4
5
6
7
8
11.43 (0.450) MAX.
(0.180)
1
NO PIN
NO PIN
V LED
2
3
3
4
5
6
7
8
9
NO PIN
NO PIN
NO PIN
GND LED
NO PIN
NO PIN
V LED
NO PIN
NO PIN
NO PIN
DATA IN
RS
NO PIN
CLOCK
CE
BLANK
GND LOGIC
SEL
2.54 (0.100) TYP.
PIN # 1 IDENTIFIER
DATE CODE (YEAR, WEEK)
INTENSITY CATEGORY
COLOR BIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.25
(0.010)
PART NUMBER
COUNTRY OF ORIGIN
HCMS-297X
YYWW
5.31
(0.209)
X Z
COO
0.51
(0.020)
3.71
TYP.
(0.146)
V LOGIC
NO PIN
RESET
OSC
6.22
(0.245)
SYM.
0.51 ± 0.13
(0.020 ± 0.005)
TYP.
DATA OUT
1.90
(0.075)
SYM.
2.54 ± 0.13
(0.100 ± 0.005)
(NON ACCUM.)
TYP.
7.62
(0.300)
NOTES:
1. DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
Absolute Maximum Ratings
Logic Supply Voltage, VLOGIC to GNDLOGIC
LED Supply Voltage, VLED to GNDLED
Input Voltage, Any Pin to GND
-0.3 V to 7.0 V
-0.3 V to 5.5 V
-0.3 V to VLOGIC +0.3 V
-40°C to +85°C
85%
[1]
Free Air Operating Temperature Range TA
Relative Humidity (noncondensing)
Storage Temperature, TS
-55°C to 100°C
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping
Wave Soldering
260°C for 5 secs
250°C for 3 secs
ESD Protection @ 1.5 kΩ, 100 pF (each pin)
Class 1, 0-1999 V
[2]
TOTAL Package Power Dissipation at TA = 25°C
4 Character
8 Character
16 Character
1.2 W
2.4 W
4.8 W
Notes:
1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations.
Recommended Operating Conditions Over Temperature Range
(-40°C to +85°C)
Parameter
Symbol
Min.
3.0
Typ.
5.0
5.0
0
Max.
5.5
Units
V
Logic Supply Voltage
LED Supply Voltage
V
LOGIC
V
LED
4.0
5.5
V
GND to GND
–
-0.3
+0.3
V
LED
LOGIC
4
Electrical Characteristics Over Operating Temperature Range (-40°C to +85°C)
T = 25°C -40°C < T < 85°C
A
A
V
Typ.
= 5.0 V
Max.
3.0 V < V
Min.
< 5.5 V
LOGIC
LOGIC
Parameter
Symbol
Max.
Units Test Conditions
Input Leakage Current
I
µA
mA
µA
mA
µA
V = 0 V to V
IN LOGIC
I
HCMS-290X/ 296X (4 char)
HCMS-291X/ 297X (8 char)
HCMS-292X (16 char)
+7.5
+15
+15
-2.5
-5.0
-5.0
+50
+100
+100
I
OPERATING
I
(OPT)
(SLP)
V = V
IN LOGIC
LOGIC
LOGIC
HCMS-290X/ 296X (4 char)
HCMS-291X/ 297X (8 char)
HCMS-292X (16 char)
[1]
0.4
0.8
0.8
2.5
5
5
5
10
10
I
SLEEP
I
V = V
LOGIC
LOGIC
IN
LOGIC
HCMS-290X/ 296X (4 char)
HCMS-291X/ 297X (8 char)
HCMS-292X (16 char)
5
10
10
15
30
30
25
50
50
I
BLANK
I
(BL)
BL = 0 V
LED
LED
HMCS-290X/ 296X (4 char)
HCMS-291X/ 297X (8 char)
HCMS-292X (16 char)
[1]
2.0
4.0
4.0
4
8
8
4.0
8
8
I
SLEEP
I
(SLP)
LED
LED
HCMS-290X/ 296X (4 char)
HCMS 291X/ 297X (8 char)
HCMS-292X (16 char)
[2]
1
2
2
3
6
6
50
100
100
Peak Pixel Current
I
V
LED
= 5.5 V
PIXEL
HCMS-29X5 (AlGaAs)
HCMS-29XX (Other Colors)
15.4
14.0
17.1
15.9
18.7
17.1
mA
mA
All pixels ON,
Average value per pixel
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
V
2.0
V
V
V
V
V
4.5 V < V
< 5.5 V
< 4.5 V
< 5.5 V
< 4.5 V
ih
LOGIC
0.8 V
3.0 V < V
LOGIC
LOGIC
V
il
0.8
4.5 V < V
LOGIC
0.2 V
3.0 V < V
LOGIC
LOGIC
V
oh
2.0
0.8 V
V
LOGIC
= 4.5 V,
I
oh
= -40 µA
V
V
3.0 V < V
< 4.5 V
< 4.5 V
LOGIC
LOGIC
LOW Level Output Voltage
V
ol
0.4
0.2 V
V
LOGIC
= 5.5 V,
[3]
I = 1.6 mA
ol
V
3.0 V < V
LOGIC
LOGIC
Thermal Resistance
Rq
70
°C/ W IC junction to pin
J-P
Notes:
1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off.
2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value.
3. For the Oscillator Output, I = 40 µA.
ol
5
[1]
Optical Characteristics at 25°C
= 5.0 V, 50% Peak Current, 100% Pulse Width
V
LED
Peak
Wavelength
Dominant
[2]
Luminous Intensity per LED
Character Average (µcd)
Wavelength
[3]
l
(nm)
l
(nm)
Peak
d
Display Color
AlGaAs Red
High Efficiency Red
Orange
Part Number
HCMS-29X5
HCMS-29X2
HCMS-29X4
HCMS-29X1
HCMS-29X3
Min.
Typ.
230
64
Typ.
645
635
600
583
568
Typ.
637
626
602
585
574
95
29
29
64
Yellow
29
64
Green
57
114
Notes:
1. Refers to the initial case temperature of the device immediately prior to measurement.
2. Measured with all LEDs illuminated.
3. Dominant wavelength, l , is derived from the CIE chromaticity diagram and represents the single wavelength which defines the perceived LED color.
d
Electrical Description
Pin Function
Description
RESET (RST)
Sets Control Register bits to logic low. The Dot Register contents are
unaffected by the Reset pin. (logic low = reset; logic high = normal
operation).
DATA IN (DIN)
DATA OUT (DOUT
CLOCK (CLK)
Serial Data input for Dot or Control Register data. Data is entered on the
rising edge of the Clock input.
)
Serial Data output for Dot or Control Register data. This pin is used for
cascading multiple displays.
Clock input for writing Dot or Control Register data. When Chip Enable is
logic low, data is entered on the rising Clock edge.
REGISTER SELECT (RS)
CHIP ENABLE (CE)
Selects Dot Register (RS = logic low) or Control Register (RS = logic high)
as the destination for serial data entry. The logic level of RS is latched on
the falling edge of the Chip Enable input.
This input must be a logic low to write data to the display. When CE
returns to logic high and CLK is logic low, data is latched to either the LED
output drivers or a Control Register.
OSCILLATOR SELECT
(SEL)
Selects either an internal or external display oscillator source.
(logic low = External Display Oscillator; logic high = Internal Display
Oscillator).
OSCILLATOR (OSC)
Output for the Internal Display Oscillator (SEL = logic high) or input for an
External Display Oscillator (SEL = logic low).
BLANK (BL)
GNDLED
GNDLOGIC
VLED
Blanks the display when logic high. May be modulated for brightness control.
Ground for LED drivers.
Ground for logic.
Positive supply for LED drivers.
Positive supply for logic.
VLOGIC
6
AC Timing Characteristics Over Temperature Range (-40°C to +85°C)
Timing
Diagram Ref.
4.5 V < V
<5.5 V
V
= 3 V
LOGIC
LOGIC
Number
Description
Symbol Min.
Max.
Min.
Max.
Units
ns
1
2
3
Register Select Setup Time to Chip Enable
Register Select Hold Time to Chip Enable
t
t
t
10
10
20
10
rss
10
ns
rsh
Rising Clock Edge to Falling
Chip Enable Edge
20
ns
clkce
4
5
6
7
8
9
Chip Enable Setup Time to Rising Clock Edge
Chip Enable Hold Time to Rising Clock Edge
Data Setup Time to Rising Clock Edge
t
t
t
t
t
t
35
20
10
10
10
55
20
10
10
10
ns
ns
ns
ns
ns
ns
ces
ceh
ds
Data Hold Time after Rising Clock Edge
dh
[1]
Rising Clock Edge to D
40
18
65
30
OUT
dout
doutp
Propagation Delay D to D
Simultaneous Mode for One IC
IN
OUT
[1,2]
10
11
12
CE Falling Edge to D Valid
t
t
t
t
25
45
ns
OUT
cedo
clkh
clkl
Clock High Time
80
80
50
100
100
50
ns
Clock Low Time
ns
Reset Low Time
ns
rstl
Clock Frequency Frequency
Internal Display Oscillator
Internal Refresh Frequency
F
5
4
MHz
KHz
Hz
cyc
F
inosc
80
210
410
80
210
400
F
rf
150
150
External Display Oscillator
Prescaler = 1
F
exosc
51.2
410
1000
8000
51.2
410
1000
8000
KHz
KHz
Prescaler = 8
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
7
Display Overview
Reset
procedure shown in Table 1 and
the Write Cycle Timing Diagram.
The HCMS-29xx series is a
family of LED displays driven by
on-board CMOS ICs. The LEDs
are configured as 5 x 7 font
characters and are driven in
groups of 4 characters per IC.
Each IC consists of a 160-bit
shift register (the Dot Register),
two 7-bit Control Words, and
refresh circuitry. The Dot Regis-
ter contents are mapped on a
one-to-one basis to the display.
Thus, an individual Dot Register
bit uniquely controls a single
LED.
Reset initializes the Control
Registers (sets all Control
Register bits to logic low) and
places the display in the sleep
mode. The Reset pin should be
connected to the system
power-on reset circuit. The Dot
Registers are not cleared upon
power-on or by Reset. After
power-on, the Dot Register
contents are random; however,
Reset will put the display in
sleep mode, thereby blanking the
LEDs. The Control Register and
the Control Words are cleared to
all zeros by Reset.
First RS is brought low, then CE
is brought low. Next, each
successive rising CLK edge will
shift in the data at the D pin.
IN
Loading a logic high will turn
the corresponding LED on; a
logic low turns the LED off.
When all 160 bits have been
loaded (or 320 bits in an 8-digit
display), CE is brought to logic
high.
When CLK is next brought to
logic low, new data is latched
into the display dot drivers.
Loading data into the Dot
Register takes place while the
previous data is displayed and
eliminates the need to blank the
display while loading data.
8-character displays have two
ICs that are cascaded. The Data
Out line of the first IC is
internally connected to the Data
In line of the second IC forming
a 320-bit Dot Register. The dis-
play’s other control and power
lines are connected directly to
both ICs. In 16-character
displays, each row functions as
an independent 8-character
display with its own 320-bit Dot
Register.
To operate the display after
being Reset, load the Dot
Register with logic lows. Then
load Control Word 0 with the
desired brightness level and set
the sleep mode bit to logic high.
Pixel Map
Dot Register
In a 4-character display, the
160-bits are arranged as 20
columns by 8 rows. This array
can be conceptualized as four 5
x 8 dot matrix character loca-
The Dot Register holds the
pattern to be displayed by the
LEDs. Data is loaded into the
Dot Register according to the
Table 1. Register Truth Table
Function
CLK
CE
RS
Select Dot Register
Load Dot Register
Not Rising
#
L
D = HIGH LED = "ON"
IN
!
L
X
D = LOW LED = "OFF"
IN
Copy Data from Dot Register to Dot Latch
Select Control Register
L
H
#
L
X
H
X
X
Not Rising
[1,3]
Load Control Register
!
[2]
Latch Data to Control Word
L
!
Notes:
1. BIT D of Control Word 1 must have been previously set to Low for serial mode or High for
0
simultaneous mode.
2. Selection of Control Word 1 or Control Word 0 is set by D of the Control Shift Register. The
7
unselected control word retains its previous value.
3. Control Word data is loaded Most Significant Bit (D ) first.
7
8
HCMS-29xx Write Cycle Diagram
RS
T
RSS
T
RSH
1
2
CE
T
T
CEH
5
T
T
T
CLKL
12
CLKCE
3
CLKH
11
CES
4
CLK
[1]
T
T
DS
6
DH
7
NEW DATA LATCHED HERE
D
IN
T
T
CEDO
10
DOUT
8
D
(SERIAL)
OUT
T
DOUTP
9
D
OUT
(SIMULTANEOUS)
LED OUTPUTS,
CONTROL
PREVIOUS DATA
NEW DATA
REGISTERS
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
tions, but only 7 of the 8 rows
have LEDs (see Figures 1 & 2).
The bottom row (row 0) is not
used. Thus, latch location 0 is
never displayed. Column 0
controls the left-most column.
Data from Dot Latch locations
0-7 determine whether or not
pixels in Column 0 are
Control Register
successive rising CLK edge will
shift in the data on the D pin.
The Control Register allows
software modification of the IC’s
operation and consists of two
independent 7-bit control words.
IN
Finally, when 8 bits have been
loaded, the CE line is brought to
logic high. When CLK goes to
logic low, new data is copied
into the selected control word.
Loading data into the Control
Register takes place while the
previous control word
Bit D in the shift register
7
selects one of the two 7-bit
control words. Control Word 0
performs pulse width modula-
tion brightness control, peak
pixel current brightness control,
and sleep mode. Control Word 1
sets serial/simultaneous data
out mode, and external oscilla-
tor prescaler. Each function is
independent of the others.
turned-on or turned-off.
Therefore, the lower left pixel is
turned-on when a logic high is
stored in Dot Latch location 1.
Characters are loaded in
serially, with the left-most
character being loaded first and
the right-most character being
loaded last. By loading one
character at a time and latching
the data before loading the next
character, the figures will
appear to scroll from right to
left.
configures the display.
Control Word 0
Loading the Control Register
with D = Logic low selects
7
Control Word 0 (see Table 2).
Bits D -D adjust the display
0
3
Control Register Data Loading
brightness by pulse width
modulating the LED on-time,
while Bits D -D adjust the
Data is loaded into the Control
Register, MSB first, according to
the procedure shown in Table 1
and the Write Cycle Timing
Diagram. First, RS is brought to
logic high and then CE is
4
5
display brightness by changing
the peak pixel current. Bit D
6
selects normal operation or
sleep mode.
brought to logic low. Next, each
9
DATA OUT
RS (LATCHED)
H
L
DATA IN
CLK
L
H
H
L
SER/PAR
MODE
CHIP
ENABLE
DI
40 BIT
S.R.
DO
DI
40 BIT
S.R.
DO
DI
40 BIT
S.R.
DO
DI
40 BIT
S.R.
DO
DOT
REGISTERS
AND
DATA IN
CLR
CONTROL
REGISTER
DATA
OUT
LATCHES
REGISTER
SELECT
D
Q
RS
(LATCHED)
V LED +
CURRENT
REFERENCE
REFRESH
CONTROL
ANODE
CURRENT SOURCES
RESET
RST
PWM BRIGHTNESS
CONTROL
DOT
REGISTER
BIT # 159
PRESCALE
VALUE
ROW 7
H
L
÷8
OSC
ROW 1
0 x x x x
x x x x x
CHAR 1
x x x x x
CHAR 2
x x x x x ROW 0 (NO LEDS)
H
L
OSCILLATOR
COLUMN 0
CHAR 0
COLUMN 19
CHAR 3
L
H
OSC
SELECT
GND (LED)
BLANK
Figure 1.
DATA FROM
PREVIOUS
CHARACTER
PIXEL
DATA TO
NEXT
ROW 7
CHARACTER
ROW 6
ROW 5
ROW 4
ROW 3
ROW 2
ROW 1
ROW 0
(NOT USED)
Figure 2.
10
Sleep mode (Control Word 0, bit
Registers. In the simultaneous
mode, N ICs only need 8 clock
pulses to load the same data in
all Control Registers. The
are connected in series to form a
320-bit dot shift register. The
location of pixel 0 has not
changed. However, Dot Shift
Register bit 0 of IC2 becomes bit
160 of the 320-bit dot shift
register.
D = Low) turns off the Internal
6
Display Oscillator and the LED
pixel drivers. This mode is used
when the IC needs to be
powered up, but does not need
to be active. Current draw in
sleep mode is nearly zero. Data
in the Dot Register and Control
Words are retained during sleep
mode.
propagation delay from the first
IC to the last is N * t
.
DOUTP
External Oscillator Prescaler Bit D
1
The Control Registers of the two
ICs are independent of each
other. This means that to adjust
the display brightness the same
control word must be entered
into both ICs, unless the Control
Registers are set to simultaneous
mode.
Bit D of Control Word 1 is used
1
to scale the frequency of an
external Display Oscillator.
When this bit is logic low, the
external Display Oscillator
directly sets the internal display
clock rate. When this bit is a
logic high, the external oscillator
is divided by 8. This scaled
frequency then sets the internal
display clock rate. It takes 512
cycles of the display clock (or 8
x 512 = 4096 cycles of an
external clock with the divide by
8 prescaler) to completely
refresh the display once. Using
the prescaler bit allows the
designer to use a higher external
oscillator frequency without
extra circuitry.
Control Word 1
Loading the Control Register
with D = logic high selects
7
Control Word 1. This Control
Word performs two functions:
serial/simultaneous data out
mode and external oscillator
prescale select (see Table 2).
Longer character string systems
can be built by cascading multi-
ple displays together. This is
accomplished by creating a five
line bus. This bus consists of CE,
RS, BL, Reset, and CLK. The
display pins are connected to
the corresponding bus line.
Serial/Simultaneous Data Output D
0
Bit D of control word 1 is used
0
to switch the mode of D
OUT
between serial and simultaneous
data entry during Control
Register writes. The default
mode (logic low) is the serial
Thus, all CE pins are connected
to the CE bus line. Similarly, bus
lines for RS, BL, Reset, and CLK
are created. Then D is
IN
D
mode. In serial mode, D
OUT
OUT
connected to the right-most
This bit has no affect on the
internal Display Oscillator
Frequency.
is connected to the last bit (D )
7
display. D
from this display
OUT
of the Control Shift Register.
is connected to the next display.
The left-most display receives its
Storing a logic high to bit D
0
D
from the D
of the display
Bits D -D
IN
OUT
changes D
to simultaneous
2
6
OUT
to its right. D
from the
OUT
mode which affects the Control
Register only. In simultaneous
These bits must always be pro-
grammed to logic low.
left-most display is not used.
mode, D
nected to D . This arrangement
is logically con-
IN
OUT
Each display may be set to use
its internal oscillator, or the
displays may be synchronized by
setting up one display as the
master and the others as slaves.
The slaves are set to receive
their oscillator input from the
master’s oscillator output.
Cascaded ICs
Figure 3 shows how two ICs are
connected within an
HCMS-29XX display. The first IC
controls the four left-most
characters and the second IC
controls the four right-most
characters. The Dot Registers
allows multiple ICs to have their
Control Registers written to
simultaneously. For example, for
N ICs in the serial mode, N * 8
clock pulses are needed to load
the same data in all Control
11
Table 2. Control Shift Register
CONTROL WORD 0
D4 D3 D2
L
D6
D5
D1
D0
↑
Bit D
On-Time
Oscillator
Cycles
Duty
Factor
(%)
Relative
Brightness
(%)
7
Set Low
to Select
Control
Word 0
PWM Brightness
Control
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
0
1
0
0
1.7
3.3
5.0
6.7
8.3
11.7
15
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
0.2
0.4
0.6
0.8
1.0
1.4
1.8
2.1
2.7
3.5
4.3
5.5
7.0
9.4
11.7
2
L
3
L
4
L
5
L
7
L
9
H
H
H
H
H
H
H
H
11
14
18
22
28
36
48
60
18
23
30
37
47
60
80
100
Peak Current
Brightness
Control
Typical Peak
Pixel Current
(mA)
Relative Full
Scale Current
(Relative Brightness, %)
H
L
L
H
L
4.0
6.4
31
50
L
9.3
73 (Default at Power Up)
100
H
H
12.8
SLEEP MODE
L – DISABLES INTERNAL OSCILLATOR-DISPLAY BLANK
H – NORMAL OPERATION
CONTROL WORD 1
H
L
L
L
L
L
D1
D0
↑
Serial/ Simultaneous Data Out
Bit D
7
L – Dout holds contents of Bit D
7
Set High
to Select
Control
Word 1
Reserved for Future
Use (Bits D -D
must be set Low)
H – Dout is functionally tied to D
in
2
6
External Display Oscillator Prescaler
L – Oscillator Freq ∏ 1
H – Oscillator Freq ∏ 8
12
CE
RS
BL
RESET
CLK
CE
RS
BL
CE
RS
BL
RESET
CLK
RESET
CLK
IC1
IC2
BITS 0-159
BITS 160-319
CHARACTERS 4-7
CHARACTERS 0-3
D
D
D
D
IN
D
OUT
OUT
OUT
IN
SEL
OSC
SEL
SEL
OSC
OSC
D
IN
Figure 3. Cascaded ICs.
13
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Appendix A. Thermal
Considerations
The display IC has a maximum
junction temperature of 150°C.
The IC junction temperature can
be calculated with Equation 1
below.
P can be calculated as Equation
2 below.
D
R
= 100°C/W
θ
J-A
Figure 4 shows how to derate
the power of one IC versus
ambient temperature. Operation
at high ambient temperatures
may require the power per IC to
be reduced. The power con-
sumption can be reduced by
A typical value for Rq is
JA
100°C/W. This value is typical
for a display mounted in a
socket and covered with a
plastic filter. The socket is
soldered to a .062 in. thick PCB
with .020 inch wide, one ounce
copper traces.
25 30 35 40 45 50 55 60 65 70 75 80 85 90
– AMBIENT TEMPERATURE – °C
changing either the N, I
,
PIXEL
T
Osc cyc or V
. Changing
LED
A
V
has very little impact on
LOGIC
the power consumption.
Figure 4.
Appendix B. Electrical
Considerations
Current Calculations
Equation 1:
The peak and average display
current requirements have a
significant impact on power
supply selection. The maximum
peak current is calculated with
Equation 3 below.
TJMAX = TA + PD * RqJA
Where:
TJMAX = maximum IC junction temperature
TA = ambient temperature surrounding the display
RqJA = thermal resistance from the IC junction to ambient
PD = power dissipated by the IC
The average current required by
the display can be calculated
with Equation 4 below.
Equation 2:
PD = (N * IPIXEL * Duty Factor * VLED) + ILOGIC * VLOGIC
Where:
The power supply has to be able
PD = total power dissipation
N = number of pixels on (maximum 4 char * 5 * 7 = 140)
IPIXEL = peak pixel current.
to supply I
transients and
(AVG) continuously.
PEAK
supply I
LED
The range on V
allows noise
LED
Duty Factor = 1/8 * Osccyc/64
Osc cyc = number of ON oscillator cycles per row
ILOGIC = IC logic current
on this supply without signifi-
cantly changing the display
brightness.
VLOGIC = logic supply voltage
V
and V Considerations
LED
LOGIC
The display uses two indepen-
dent electrical systems. One
system is used to power the
display’s logic and the other to
power the display’s LEDs. These
two systems keep the logic
supply clean.
Equation 3:
IPEAK = M * 20 * IPIXEL
Where:
IPEAK = maximum instantaneous peak current for the display
M = number of ICs in the system
20 = maximum number of LEDs on per IC
IPIXEL = peak current for one LED
Separate electrical systems
allow the voltage applied to V
Equation 4:
LED
and V
to be varied
LOGIC
ILED(AVG) = N * IPIXEL * 1/8 * (oscillator cycles)/64
independently. Thus, V
can
LED
(see Variable Definitions above)
14
vary from 0 to 5.5 V without
affecting either the Dot or the
Electrostatic Discharge
Appendix D. Refresh Circuitry
This display driver consists of
20 one-of-eight column decoders
and 20 constant current sources,
1 one-of-eight row decoder and
eight row sinks, a pulse width
modulation control block, a peak
current control block, and the
circuit to refresh the LEDs. The
refresh counters and oscillator
are used to synchronize the
columns and rows.
The inputs to the ICs are pro-
tected against static discharge
and input current latchup. How-
ever, for best results, standard
CMOS handling precautions
should be used. Before use, the
HCMS-29XX should be stored in
antistatic tubes or in conductive
material. During assembly, a
grounded conductive work area
should be used and assembly
personnel should wear conduc-
tive wrist straps. Lab coats made
of synthetic material should be
avoided since they are prone to
static buildup. Input current
latchup is caused when the
Control Registers. V
can be
LED
varied between 4.0 to 5.5 V with-
out any noticeable variation in
light output. However, operating
V
below 4.0 V may cause
LED
objectionable mismatch between
the pixels and is not
recommended. Dimming the
display by pulse width modulat-
ing V
is also not
LED
recommended.
The 160 bits are organized as 20
columns by 8 rows. The IC
illuminates the display by
V
can vary from 3.0 to 5.5 V
LOGIC
without affecting either the
displayed message or the display
intensity. However, operation
below 4.5 V will change the
timing and logic levels and
operation below 3 V may cause
the Dot and Control Registers to
be altered.
sequentially turning ON each of
the 8 row-drivers. To refresh the
display once takes 512 oscillator
cycles. Because there are eight
row drivers, each row driver is
selected for 64 (512/8) oscillator
cycles. Four cycles are used to
briefly blank the display before
the following row is switched on.
Thus, each row is ON for 60
oscillator cycles out of a possible
64. This corresponds to the
CMOS inputs are subjected to
either a voltage below ground
(V < ground) or to a voltage
IN
higher then V
(V
>
LOGIC
IN
V
) and when a high current
LOGIC
is forced into the input. To
The logic ground is internally
connected to the LED ground by
a substrate diode. This diode
becomes forward biased and
conducts when the logic ground
is 0.4 V greater then the LED
ground. The LED ground and the
logic ground should be
connected to a common ground
which can withstand the current
introduced by the switching LED
drivers. When separate ground
connections are used, the LED
ground can vary from -0.3 V to
+0.3 V with respect to the logic
ground. Voltages below -0.3 V
can cause all the dots to be ON.
Voltage above +0.3 V can cause
dimming and dot mismatch. The
LED ground for the LED drivers
can be routed separately from
the logic ground until an
prevent input current latchup
and ESD damage, unused inputs
should be connected to either
ground or V
. Voltages
LOGIC
should not be applied to the
inputs until V has been
maximum LED on time.
LOGIC
applied to the display.
Appendix E. Display Brightness
Two ways have been shown to
control the brightness of this
LED display: setting the peak
current and setting the duty
factor. Both values are set in
Control Word 0. To compute the
resulting display brightness
when both PWM and peak
current control are used, simply
multiply the two relative bright-
ness factors. For example, if
Control Register 0 holds the
word 1001101, the peak current
Appendix C. Oscillator
The oscillator provides the
internal refresh circuitry with a
signal that is used to synchron-
ize the columns and rows. This
ensures that the right data is in
the dot drivers for that row. This
signal can be supplied from
either an external source or the
internal source.
A display refresh rate of 100 Hz
or faster ensures flicker-free
operation. Thus for an external
oscillator the frequency should
be greater than or equal to 512 x
100 Hz = 51.2 kHz. Operation
above 1 MHz without the
prescaler or 8 MHz with the
prescaler may cause noticeable
pixel to pixel mismatch.
is 73% of full scale (BIT D = L,
5
BIT D = L) and the PWM is set
4
appropriate ground plane is
available. On long
interconnections between the
display and the host system,
voltage drops on the analog
ground can be kept from
to 60% duty factor (BIT D = H,
3
BIT D = H, BIT D = L, BIT D =
2
1
0
H). The resulting brightness is
44% (.73 x .60 = .44) of full scale.
affecting the display logic levels
by isolating the two grounds.
15
3.0
2.6
The temperature of the display
will also affect the LED bright-
ness as shown in Figure 5.
HER/ORANGE
YELLOW
2.2
1.8
1.4
Appendix F. Reference Material
Application Note 1027:
Soldering LED Components
GREEN
AlGaAs
1.0
Application Note 1015: Contrast
Enhancement Techniques for
LED Displays
0.6
0.2
-55
-35
-15
5
25
45
65
85
T
– AMBIENT TEMPERATURE – °C
A
Figure 5.
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5988-4161EN
5989-3181EN June 2, 2006
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