HCPL-2219 [AVAGO]
Low Input Current Logic Gate Optocouplers; 低输入电流逻辑门光电耦合器
| 型号： | HCPL-2219 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Low Input Current Logic Gate Optocouplers |
| 文件： | 总13页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-2200,HCPL-2219
LowInputCurrentLogicGateOptocouplers
DataSheet
Description
Features
The HCPL-2200/2219 are optically coupled logic gates • 2.5 kV/ µs minimum Common Mode Rejection (CMR) at
that combine a GaAsP LED and an integrated high gain
photo detector. The detector has a three state output
stage and has a detector thresholdwithhysteresis. The
three state output eliminates the need for a pullup
resistor and allows for direct drive of data busses. The
VCM = 400 V (HCPL-2219)
• Compatible with LSTTL, TTL, and CMOS logic
• Wide V range (4.5 to 20 V)
CC
• 2.5 Mbd guaranteed over temperature
hysteresis provides differential mode noise immunity • Low input current (1.6 mA)
and eliminates the potential for output signal chatter.
• Three state output (no pullup resistor required)
• Guaranteed performance from 0°C to 85°C
Asuperiorinternalshieldon theHCPL-2219guarantees
common mode transient immunity of 2.5 kV/µs at a
common mode voltage of 400 volts.
• Hysteresis
• Safety approval
– UL recognized -3750 V rms for 1 minute
– CSA approved
The Electrical and Switching Characteristics of the
HCPL-2200/2219 are guaranteed over the tempera-
– IEC/ EN/ DIN EN 60747-5-2 approved with
VIORM = 630 Vpeak (HCPL-2219 Option 060 only)
ture range of 0°C to 85°C and a V range of 4.5 volts to
CC
• MIL-PRF-38534 hermetic version available
(HCPL-5200/ 1)
20volts. LowI andwideV rangeallowcompatibility
F
CC
with TTL, LSTTL, and CMOS logic and result in lower
power consumption compared to other high speed
optocouplers. Logic signals are transmitted with a Applications
typical propagation delay of 160 nsec.
• Isolation of high speed logic systems
The HCPL-2200/2219 are useful for isolating high
speed logic interfaces, buffering of input and output
lines, and implementing isolated line receivers in
high noise environments.
• Computer-peripheral interfaces
• Microprocessor system interfaces
• Ground loop elimination
• Pulse transformer replacement
• Isolated buss driver
Functional Diagram
• High speed line receiver
NC
ANODE
CATHODE
NC
1
2
3
4
8
7
6
5
V
V
V
CC
TRUTH TABLE
(POSITIVE LOGIC)
O
LED
ENABLE OUTPUT
ON
OFF
ON
H
H
L
L
Z
Z
H
L
E
OFF
GND
SHIELD
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
Minimum CMR
Small-Outline
SO-8
Widebody
(400 Mil)
8-Pin DIP (300 Mil)
Hermetic
Input On-
Current
(mA)
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Single
Channel
Package
Single and Dual
Channel
dV/ dt
(V/ µs)
V
(V)
CM
Packages
[1]
1,000
50
1.6
HCPL-2200
HCPL-2201
HCPL-2202
HCPL-0201
HCNW2201
1.8
1.6
1.6
HCPL-2231
HCPL-2232
[1]
2,500
400
HCPL-2219
[2]
[2]
5,000
300
HCPL-2211
HCPL-2212
HCPL-0211
HCNW2211
1.8
2.0
1,000
50
HCPL-52XX
HCPL-62XX
Notes:
1. HCPL-2200/ 2219 devices include output enable/ disable functionality.
2. Minimum CMR of 10 kV/ µs with VCM = 1000 V can be achieved with input current, IF, of 5 mA.
2
Ordering Information
HCPL-2200, HCPL-2219 are UL Recognized with 3750 Vrms for 1 minute per UL1577 and are approved
under CSA Component Acceptance Notice #5, File CA 88324.
Option
Part
RoHS
non RoHS
Surface Gull
Tape
UL 5000 Vrms/ IEC/ EN/ DIN
Number Compliant Compliant Package
Mount
Wing & Reel 1 Minute rating EN 60747-5-2 Quantity
-000E
HCPL-2200 -300E
-500E
no option 300 mil DIP-8
50 per tube
-300
X
X
X
X
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
-500
X
X
X
-000E
no option 300 mil DIP-8
-300E
-300
-500
-060
-360
-560
X
X
X
X
HCPL-2219 -500E
-060E
X
X
X
-360E
X
X
X
X
-560E
To order, choose a part number from the part number column and combine with the desired option from
the option column to form an order entry.
Example 1:
HCPL-2219-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel
packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-2200 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for
information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15,
2001 and RoHS compliant will use ‘–XXXE.’
Schematic
I
CC
V
CC
8
I
F
I
O
+
–
V
V
O
2
7
6
5
V
F
I
E
E
3
GND
SHIELD
3
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
5
TYPE NUMBER
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
1
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2
3
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
4
Solder Reflow Thermal Profile
Regulatory Information
300
The HCPL-2200/2219 have been
approved by the following
organizations:
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
UL
200
100
0
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
Recognized under UL 1577,
Component Recognition Program,
File E55361.
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
CSA
50 SEC.
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
IEC/ EN/ DIN EN 60747-5-2
Note: Non-halide flux should be used.
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
(Option 060 only)
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
150 - 200 °C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
Note: Non-halide flux should be used.
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap
(External Clearance)
L(IO1)
7.1
mm
Measured from input terminals to output terminals,
shortest distance through air.
Min. External
Tracking Path
(External Creepage)
L(IO2)
7.4
0.08
200
IIIa
mm
mm
V
Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal
Plastic Gap
(Internal Clearance)
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
Tracking Resistance
(Comparative
Tracking Index)
CTI
DIN IEC 112/ VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/ 89, Table 1)
Option 300 – surface mount classification is Class A in accordance with CECC 00802.
5
IEC/ EN/ DIN EN 60747-5-2 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/ 1.89, Table 1
for rated mains voltage ≤300 V rms
I-IV
I-III
for rated mains voltage ≤450 V rms
Climatic Classification
55/ 85/ 21
2
Pollution Degree (DIN VDE 0110/ 1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
IORM
630
V peak
Vpeak
V
x 1.875 = V , 100% Production Test with t = 1 sec,
V
PR
1181
945
IORM
PR
m
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
x 1.5 = V , Type and sample test,
V
PR
Vpeak
Vpeak
IORM
PR
t = 60 sec, Partial Discharge < 5 pC
m
Highest Allowable Overvoltage*
(Transient Overvoltage, t = 10 sec)
V
IOTM
6000
ini
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 12, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
T
175
230
600
°C
mA
mW
S
I
S,INPUT
P
S,OUTPUT
9
Insulation Resistance at T , V = 500 V
R
S
≥10
Ω
S
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/ EN/ DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
6
Absolute Maximum Ratings
(No Derating Required up to 70°C)
Parameter
Symbol
Min.
-55
Max.
125
85
Units
°C
Note
Storage Temperature
Operating Temperature
Average Forward Input Current
T
S
T
A
-40
°C
1
I
10
mA
A
F(AVG)
Peak Transient Input Current
I
1.0
F(TRAN)
(≤1 µs Pulse Width, 300 pps)
Reverse Input Voltage
V
5
25
20
20
20
210
V
mA
V
R
Average Output Current
Supply Voltage
I
O
V
CC
0
Three State Enable Voltage
Output Voltage
V
E
-0.5
-0.5
V
V
O
V
Total Package Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
P
T
mW
1
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
Min.
4.5
2.0
0
Max.
20
Units
Power Supply Voltage
Enable Voltage High
Enable Voltage Low
Forward Input Current
Forward Input Current
Operating Temperature
Fan Out
V
CC
V
V
V
EH
20
V
EL
0.8
5
V
IF(ON)
IF(OFF)
1.6*
–
mA
0.1
85[1]
4
mA
T
A
0
°C
N
TTL Loads
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit
at least a 20% CTR degradation guardband.
7
Electrical Specifications
For 0°C ≤ T [1] ≤ 85°C, 4.5 V ≤ V ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 2.0 V ≤ V ≤ 20 V, 0.0 V ≤ V ≤ 0.8 V, 0 mA ≤ IF(OFF) ≤ 0.1 mA.
A
CC
EH
EL
All Typicals at T = 25°C, V = 5 V, IF(ON) = 3 mA unless otherwise specified. See Note 7.
A
CC
Parameter
Sym.
Min. Typ. Max. Units
Test Conditions
Fig. Note
Logic Low
V
OL
0.5
V
IOL = 6.4 mA (4 TTL Loads)
1
Output Voltage
Logic High
Output Voltage
V
2.4
2.0
*
V
IOH = -2.6 mA *V = V - 2.1 V
2
OH
OH
CC
Output Leakage
Current (VOUT > V )
IOHH
100
500
µA V = 5.5 V
IF = 5 mA
O
V = 4.5 V
CC
CC
µA
V
V = 20 V
O
Logic High Enable
Voltage
V
EH
Logic Low Enable
Voltage
V
EL
0.8
V
Logic High Enable
Current
IEH
20
µA V = 2.7 V
EN
100
µA V = 5.5 V
EN
0.004 250
µA
VEN = 20 V
Logic Low Enable
Current
IEL
-0.32 mA V = 0.4 V
EN
Logic Low Supply
Current
ICCL
IF = 0 mA
IO = Open
V = Don’t Care
E
4.5
5.25
2.7
6.0
7.5
mA V = 5.5 V
CC
mA V =20V
CC
Logic High Supply
Current
ICCH
IF = 5 mA
IO = Open
V = Don’t Care
E
4.5
6.0
-20
mA V =5.5V
CC
mA V =20V
3.1
CC
High Impedance
State Output Current
IOZL
IOZH
µA V = 0.4 V
V = 2 V,
O
EN
IF = 5 mA
20
µA V = 2.4 V
V = 2 V,
EN
O
IF = 5 mA
100
500
µA V = 5.5 V
O
µA V = 20 V
O
Logic Low Short
Circuit Output
Current
IOSL
IOSH
IHYS
2
2
25
40
mA V =V = 5.5 V
IF = 0 mA
O
CC
mA V =V = 20V
O
CC
Logic High Short
Circuit Output
Current
I = 5 mA,
F
mA V =5.5 V
-10
-25
CC
V = GND
O
mA V = 20 V
CC
Input Current
Hysteresis
0.12
1.5
mA V = 5 V
3
4
CC
Input Forward
Voltage
V
F
1.7
V
V
T = 25°C
IF = 5 mA
A
1.75
Input Reverse
BV
5
IR = 10 µA
R
Breakdown Voltage
Input Diode
Temperature
Coefficient
∆V
∆T
A
-1.7
60
mV/ °C IF = 5 mA
F
Input Capacitance
C
IN
pF
f = 1 MHz, V = 0 V, Pins 2 and 3
F
8
Switching Specifications (AC)
For 0°C ≤ T [1] ≤ 85°C, 4.5 V ≤ V ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 0.0 mA ≤ IF(OFF) ≤ 0.1 mA.
A
CC
All Typicals at T = 25°C, V = 5 V, IF(ON) = 3 mA unless otherwise specified.
A
CC
Parameter
Sym. Min. Typ. Max. Units
Test Conditions
Without Peaking Capacitor
With Peaking Capacitor
Without Peaking Capacitor
With Peaking Capacitor
Fig. Note
Propagation Delay Time to
Logic Low Output Level
tPHL
210
160
170
115
25
ns
5, 6
4, 5
300
300
Propagation Delay Time to
Logic High Output Level
tPLH
ns
5, 6
4, 5
Output Enable Time to
Logic High
tPZH
tPZL
tPHZ
tPLZ
ns
ns
ns
ns
7, 9
7, 8
7, 9
7, 8
Output Enable Time to
Logic Low
28
105
60
Output Disable Time from
Logic High
Output Disable Time from
Logic Low
Output Rise Time (10-90%)
Output Fall Time (90-10%)
tr
tf
55
15
ns
ns
5, 10
5, 10
Parameter
Sym.
Device
Min.
Units
Test Conditions
Fig.
Note
Logic High
Common Mode
Transient
| CMH|
IF = 1.6 mA
11
6
HCPL-2200
1,000
2,500
1,000
2,500
V/ µs
| V | = 50 V
CM
V = 5 V
CC
TA = 25°C
HCPL-2219
HCPL-2200
HCPL-2219
V/ µs
V/ µs
V/ µs
| V | = 400 V
CM
Immunity
Logic Low
Common Mode
Transient
| CML|
V = 0 V
11
6
F
| V | = 50 V
CM
V = 5 V
CC
TA = 25°C
| V | = 400 V
CM
Immunity
Package Characteristics
Parameter
Sym.
Min.
3750
Typ. Max. Units
Test Conditions
Fig. Note
Input-Output Momentary
Withstand Voltage*
V
ISO
V rms
RH ≤50%, t = 1 min.,
T = 25°C
3, 8
A
Input-Output Resistance
Input-Output Capacitance
R
1012
0.6
Ω
V = 500 VDC
3
3
I-O
I-O
C
I-O
pF
f = 1 MHz, V = 0 VDC
I-O
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For
the continuous voltage rating refer to the IEC/ EN/ DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level safety specification
or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
9
Notes:
50% point on the trailing edge of the input
pulse to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase by
100 ns.
6. CML is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (VO < 0.8 V). CMH is the
maximum rate of fall of the common mode
voltage that can be sustained with the
output voltage in the logic high state
(VO > 2.0 V).
7. Use of a 0.1 µF bypass capacitor connected
between pins 5 and 8 is recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying an
insulation test voltage ≥4500 V rms for one
second (leakage detection current limit, II-O
≤5 µA). This test is performed before the
100% production test for partial discharge
(Method b) shown in the IEC/ EN/ DIN EN
60747-5-2 Insulation Characteristics Table, if
applicable.
1. Derate total package power dissipation, PT,
linearly above 70°C free air temperature at a
rate of 4.5 mW/ °C.
2. Duration of output short circuit time should
not exceed 10 ms.
3. Device considered a two-terminal device:
pins 1, 2, 3, and 4 shorted together and pins
5, 6, 7, and 8 shorted together.
4. The tPLH propagation delay is measured
from the 50% point on the leading edge of
the input pulse to the 1.3 V point on the
leading edge of the output pulse. The tPHL
propagation delay is measured from the
0
5
1.0
V
T
= 4.5 V
V
I
= 4.5 V
CC
= 25 °C
V
I
= 4.5 V
CC
= 0 mA
CC
= 5 mA
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-1
-2
-3
-4
A
F
F
4
3
V
= 6.4 mA
O
V
= 2.7 V
O
I
= -2.6 mA
OH
2
1
0
-5
-6
V
= 2.4 V
O
-7
-8
I
= 6.4 mA
0.5
OL
0.1
0
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
0
1.0
1.5
2.0
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
I
– INPUT CURRENT – mA
A
A
F
Figure 1. Typical logic low output voltage vs.
temperature.
Figure 2. Typical logic high output current vs.
temperature.
Figure 3. Output voltage vs. forward input
current.
V
CC
PULSE GEN.
t
= t = 5 ns
r
f
OUTPUT V
MONITORING
NODE
f = 100 kHz
10 % DUTY
CYCLE
O
5 V
HCPL-2200
V
V
= 5 V
O
1
2
3
4
8
7
6
5
CC
619 Ω
D
1
I
F
INPUT
MONITORING
NODE
D
D
D
2
3
4
C
15 pF
=
2
GND
5 kΩ
1000
R
1
C
=
1
T
= 25 °C
120 pF
A
100
10
I
F
+
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C AND
V
F
C
.
1
2
–
R
2.15 kΩ 1.10 kΩ 681 Ω
1.0
I
I
(ON) 1.6 mA 3 mA
5 mA
F
0.1
0.01
ALL DIODES ARE 1N916 OR 1N3064.
I
(ON)
F
INPUT I
F
50 % I (ON)
F
0 mA
0.001
1.1
1.2
1.3
1.4
1.5
t
t
PHL
PLH
V
– FORWARD VOLTAGE – V
V
F
OH
OUTPUT
1.3 V
V
O
V
OL
Figure 4. Typical input diode forward
characteristic.
Figure 5. Test circuit for t , t , t , and t .
PLH PHL
r
f
10
250
C = 15 pF INCLUDING PROBE
V
= 5 V
L
CC
PULSE
GENERATOR
AND JIG CAPACITANCES
.
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
I
(mA)
5
3
F
+5 V
V
Z
= 50 Ω
CC
O
200
150
t
= t = 5 ns
r
f
1.6
V
HCPL-2200
V
O
S1
1.6
3
5
1
2
3
4
8
7
6
5
CC
619 Ω
D
t
1
PHL
I
F
D
2
100
50
C
L
5 kΩ
D
3
t
PLH
GND
INPUT V
D
4
C
-60 -40 -20
0
20 40 60 80 100
MONITORING
NODE
T
– TEMPERATURE – °C
A
S2
D
ARE 1N916 OR 1N3064.
1-4
Figure 6. Typical propagation delays vs.
temperature.
3.0 V
INPUT
1.3 V
0 V
V
E
t
t
PLZ
PZL
S1 AND
S2 CLOSED
0.5 V
0.5 V
OUTPUT
S1 CLOSED
S2 OPEN
1.3 V
V
O
V
V
OL
OH
t
PZH
OUTPUT
1.3 V
0 V
≈1.5 V
V
O
S1 OPEN
S2 CLOSED
S1 AND
S2 CLOSED
t
PHZ
Figure 7. Test circuit for t , t , t , and t
.
PZL
PHZ PZH PLZ
100
200
120
V
20 V
C
= 15 pF
CC
V
C
= 5 V
= 15 pF
L
CC
2
C
= 15 pF
L
V
CC
100
80
80
60
40
150
100
4.5 V
20 V
t
PHZ
t
PLZ
PZL
4.5 V
20 V
60
t
t
r
4.5 V
40
t
20 V
50
0
20
0
4.5 V
20
0
t
PZH
f
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
A
Figure 8. Typical logic low enable
propagation delay vs. temperature.
Figure 9. Typical logic high enable
propagation delay vs. temperature.
Figure 10. Typical rise, fall time vs.
temperature.
11
V
CC
HCPL-2219 OPTION 060 ONLY
(mW)
HCPL-2200
V
800
700
600
500
400
300
200
100
0
P
OUTPUT V
MONITORING
NODE
S
1
2
3
4
8
7
6
5
O
CC
A
B
I
(mA)
S
R
IN
0.1 µF
BYPASS
V
FF
GND
V
CM
+
–
PULSE GENERATOR
50 V
SWITCH AT A: I = 1.6 mA
V
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
CM
0 V
T
S
F
V
OH
V
(MIN.)*
O
Figure 12. Thermal derating curve,
dependence of safety limiting value with case
temperature per IEC/ EN/ DIN EN 60747-5-2.
OUTPUT
SWITCH AT B: I = 0 mA
F
V
O
V
(MAX.)*
O
V
OL
* SEE NOTE 6.
Figure 11. Test circuit for common mode transient immunity and typical waveforms.
V
CC1
(+5 V)
V
CC2
120 pF (OPTIONAL*)
HCPL-2200
(4.5 TO 20 V)
V
V
CC2
CC1
(+5 V)
120 pF
(+5 V)
HCPL-2200
1.1
DATA
OUTPUT
kΩ
1.1
kΩ
R
L
V
CC
1
2
3
4
8
7
6
5
V
1
2
3
4
8
7
6
5
CC
DATA
OUTPUT
CMOS
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
DATA
INPUT
DATA
INPUT
TTL OR
LSTTL
GND
TTL OR
LSTTL
GND
TOTEM
TOTEM
POLE
OUTPUT
GATE
POLE
OUTPUT
GATE
V
5 V
10 V
15 V
20 V
R
L
CC2
2
1.1 K
2.37 K
3.83 K
5.11 K
1
1
2
Figure 13. Recommended LSTTL to LSTTL circuit.
Figure 14. LSTTL to CMOS interface circuit.
V
(+5 V)
CC
120 pF (OPTIONAL*)
HCPL-2200
1.1
kΩ
HCPL-2200
V
(+5 V)
CC1
1.1 kΩ
V
V
CC
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
DATA
INPUT
7
6
5
4.7 kΩ
D1
DATA
INPUT
TTL OR
LSTTL
TTL OR
LSTTL
GND
GND
OPEN
COLLECTOR
GATE
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
Figure 15. Recommended LED drive circuit.
Figure 16. Series LED drive with open collector gate (4.7 kΩ resistor
dhunts I from the LED).
OH
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
12
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2124EN
AV01-0557EN July 5, 2007
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