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HCPL-2400#300

更新时间：2024-09-18 19:10:50

品牌：AVAGO

描述：1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps, SURFACE MOUNT, DIP-8

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HCPL-2400#300 概述

1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps, SURFACE MOUNT, DIP-8 光耦合器/光隔离器光耦合器

HCPL-2400#300 规格参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	包装说明：	SURFACE MOUNT, DIP-8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8541.40.80.00	风险等级：	5.18
Is Samacsys：	N	其他特性：	CMOS COMPATIBLE, UL RECOGNIZED
配置：	SINGLE	标称数据速率：	40 MBps
最大正向电流：	0.01 A	最大绝缘电压：	3750 V
JESD-609代码：	e0	安装特点：	SURFACE MOUNT
元件数量：	1	最大通态电流：	0.025 A
最高工作温度：	70 °C	最低工作温度：
光电设备类型：	LOGIC IC OUTPUT OPTOCOUPLER	最大功率耗散：	0.04 W
标称响应时间：	6e-8 ns	子类别：	Optocoupler - IC Outputs
最小供电电压：	4.75 V	标称供电电压：	5.25 V
表面贴装：	YES	端子面层：	Tin/Lead (Sn/Pb)
Base Number Matches：	1

HCPL-2400#300 数据手册

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HCPL-2400, HCPL-2430

20 MBd High CMR Logic Gate Optocouplers

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

Features

The HCPL-2400 and HCPL-2430 high speed opto-cou-

plers combine an 820 nm AlGaAs light emitting diode

with a high speed photodetector. This combina-tion re-

sults in very high data rate capability and low input cur-

rent. The totem pole output (HCPL-2430) or three state

output (HCPL-2400) eliminates the need for a pull up re-

sistor and allows for direct drive of data buses.

•

High speed: 40 MBd typical data rate

High common mode rejection:

HCPL-2400: 10 kV/µs at V_CM= 300 V (typical)

•

AC performance guaranteed over temperature

High speed AlGaAs emitter

Compatible with TTL, STTL, LSTTL, and HCMOS logic

families

The detector has optical receiver input stage with built-

in Schmitt trigger to provide logic compatible wave-

forms, eliminating the need for additional waveshaping.

The hysteresis provides diﬀerential mode noise immuni-

ty and minimizes the potential for output signal chatter.

•

Totem pole and tri state output (no pull up resistor

required)

Safety approval

– UL recognized – 3750 V rms for 1 minute per

UL1577

The electrical and switching characteristics of the HCPL-

2400 and HCPL-2430 are guaranteed over the tempera-

ture range of 0°C to70°C.

– IEC/EN/DIN EN 60747-5-2 approved with

V_IORM= 630 V _peak(Option 060) for HCPL-2400

Functional Diagram

– CSA approved

•

High power supply noise immunity

HCPL-2400/11

HCPL-2430

ANODE 1

CATHODE 1

CATHODE 2

ANODE 2

MIL-PRF-38534 hermetic version available

(HCPL-5400/1 and HCPL-5430/1)

Applications

•

Isolation of high speed logic systems

Computer-peripheral interfaces

Switching power supplies

4 NC

GND

TRUTH TABLE

(POSITIVE LOGIC)

LED ENABLE OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

Isolated bus driver (networking applications)

Ground loop elimination

OFF

LED

OUTPUT

OFF

High speed disk drive I/O

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

Digital isolation for A/D, D/A conversion

Pulse transformer replacement

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

These optocouplers are compatible with TTL, STTL, LSTTL, and HCMOS logic families. When Schottky type TTL devices

(STTL) are used, a data rate performance of 20 MBd over temperature is guaranteed when using the application cir-

cuit of Figure 13. Typical data rates are 40MBd.

Selection Guide

8-Pin DIP (300 Mil)

Minimum CMR

Single

Dual

Minimum Input

On Current

(mA)

Maximum

Propagation Delay

(ns)

Channel

Package

Channel

Package

dV/dt

(V/µs)

1000

500

Hermetic

Package

(V)

300

HCPL-2400

HCPL-2430

HCPL-540X*

HCPL-543X*

HCPL-643X*

*Technical data for the Hermetic HCPL-5400/01, HCPL-5430/31, and HCPL-6430/31 are on separate Avago publications.

Ordering Information

HCPL-2400 and HCPL-2430 are UL Recognized with 3750 Vrms for 1 minute per UL1577.

Option

Part

number

RoHS

Non RoHS

Surface

Mount

Gull

Wing

Tape

& Reel

UL 5000 Vrms/1 IEC/EN/DIN EN

Compliant Compliant

Package

Minute rating

60747-5-2

Quantity

-000E

-300E

-500E

-060E

-360E

-000E

-300E

-500E

-020E

-060E

No option

#300

#500

#060

-360

No option

#300

#500

50 per tube

1000 per reel

50 per tube

50 per reel

50 per tube

1000 per reel

50 per tube

HCPL-2400

300mil

DIP-8

300mil

DIP-8

HCPL-2430

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

HCPL-2430-500E to order product of Gull Wing Surface Mount package in Tape in RoHS compliant.

Example 2:

HCPl-2400 to order product of 8-Pin DIP package in tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and

RoHS compliant option will use ‘-XXXE‘.

Schematic

–

ANODE

–

CATHODE

GND

–

GND

TRUTH TABLE

(POSITIVE LOGIC)

SHIELD

LED ENABLE OUTPUT

TRUTH TABLE

(POSITIVE LOGIC)

LED

OUTPUT

OFF

Package Outline Drawings

8-Pin DIP Package (HCPL-2400, HCPL-2430)

7.62 0.25

(0.300 0.010)

9.65 0.25

(0.380 0.010)

TYPE NUMBER

6.35 0.25

(0.250 0.010)

OPTION CODE*

DATE CODE

A XXXXZ

YYWW

U R

RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076

- 0.051

0.254

5° TYP.

+ 0.003)

- 0.002)

(0.010

3.56 0.13

(0.140 0.005)

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

*MARKING CODE LETTER FOR OPTION NUMBERS.

"V" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

1.080 0.320

0.65 (0.025) MAX.

(0.043 0.013)

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

2.54 0.25

(0.100 0.010)

8-Pin DIP Package with Gull Wing Surface Mount Option 300

(HCPL-2400, HCPL-2430)

LAND PATTERN RECOMMENDATION

1.016 (0.040)

9.65 0.25

(0.380 0.010)

6.350 0.25

(0.250 0.010)

10.9 (0.430)

2.0 (0.080)

1.27 (0.050)

9.65 0.25

1.780

(0.070)

MAX.

(0.380 0.010)

1.19

(0.047)

MAX.

7.62 0.25

(0.300 0.010)

+ 0.076

0.254

- 0.051

3.56 0.13

(0.140 0.005)

+ 0.003)

- 0.002)

(0.010

1.080 0.320

(0.043 0.013)

0.635 0.25

(0.025 0.010)

12° NOM.

0.635 0.130

(0.025 0.005)

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

Solder Reﬂow Thermal Proﬁle

300

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.

REFLOW HEATING RATE 2.5°C 0.5°C/SEC.

PEAK

TEMP.

245°C

PEAK

TEMP.

240°C

PEAK

TEMP.

230°C

200

100

2.5°C 0.5°C/SEC.

SOLDERING

TIME

160°C

150°C

140°C

200°C

SEC.

3°C + 1°C/–0.5°C

PREHEATING TIME

150°C, 90 + 30 SEC.

50 SEC.

TIGHT

TYPICAL

LOOSE

ROOM

TEMPERATURE

100

150

200

250

TIME (SECONDS)

Note: Non-halide ﬂux should be used.

Recommended Pb-Free IR Proﬁle

TIMEWITHIN 5 °C of ACTUAL

PEAKTEMPERATURE

20-40 SEC.

260 +0/-5 °C

217 °C

RAMP-UP

3 °C/SEC. MAX.

150 - 200 °C

RAMP-DOWN

6 °C/SEC. MAX.

smax

smin

60 to 150 SEC.

PREHEAT

60 to 180 SEC.

t 25 °C to PEAK

TIME

NOTES:

THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.

= 200 °C, T = 150 °C

smax

smin

Note: Non-halide ﬂux should be used.

Regulatory Information

The HCPL-24XX has been approved by the following organizations:

IEC/EN/DIN EN 60747-5-2

VDE

Approved under:

Approved according to VDE 0884/06.92 (Option 060

only).

IEC 60747-5-2:1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884

Teil 2):2003-01.

Recognized under UL 1577, Component Recognition

Program, File E55361.

(Option 060 only)

Insulation and Safety Related Speciﬁcations

Parameter

Symbol

Value

Units

Conditions

Minimum External

Air Gap (External

Clearance)

L(101)

7.1

Measured from input terminals to output

terminals, shortest distance through air.

Minimum External

Tracking (External

Creepage)

Minimum Internal

Plastic Gap

(Internal Clearance)

L(102)

CTI

7.4

Measured from input terminals to output

terminals, shortest distance path along body.

0.08

Through insulation distance, conductor to

conductor, usually the direct distance between the

photoemitter and photodetector inside the

optocoupler cavity.

Tracking Resistance

(Comparative

Tracking Index)

200

IIIa

Volts

DIN IEC 112/VDE 0303 Part 1

Isolation Group

Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classiﬁcation is Class A in accordance with CECC 00802.

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics

(HCPL-2400 OPTION 060 ONLY)

Description

Symbol

Characteristic

Units

Installation classiﬁcation per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤300 V rms

for rated mains voltage ≤450 V rms

Climatic Classiﬁcation

I-IV

I-III

55/85/21

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b*

630

V _peak

IORM

_IORMx 1.875 = V , 100% Production Test with t_m= 1 sec,

V_PR

1181

945

Partial Discharg^Pe^R< 5 pC

Input to Output Test Voltage, Method a*

x 1.5 = V_PR, Type and sample test,

V _peak

t_m^IO=^RM60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*

(Transient Overvoltage, t_ini= 10 sec)

V_IOTM

6000

V _peak

Safety Limiting Values

(Maximum values allowed in the event of a failure,

also see Figure 12, Thermal Derating curve.)

Case Temperature

T_S

175

230

600

≥10⁹

°C

Input Current

I_S,INPUT

Output Power

P_S,OUTPUT

Insulation Resistance at T_S, V = 500 V

R_S

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2 for a

detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits in applica-

tion.

Absolute Maximum Ratings

(No derating required up to 70°C)

Parameter

Symbol

T_S

Minimum

-55

Maximum

Units

°C

Note

Storage Temperature

125

Operating Temperature

Average Forward Input Current

Peak Forward Input Current

Reverse Input Voltage

T_A

-40

°C

I_F(AVG)

I_FPK

Three State Enable Voltage

(HCPL-2400 Only)

-0.5

Supply Voltage

Average Output Collector Current

Output Collector Voltage

Output Voltage

I_O

-25

-0.5

Output Collector Power Dissipation

(Each Channel)

P_O

Total Package Power Dissipation

(Each Channel)

P_T

350

Lead Solder Temperature

(for Through Hole Devices)

260°C for 10 sec., 1.6 mm below seating plane

Reﬂow Temperature Proﬁle

(Option #300)

See Package Outline Drawings section

Recommended Operating Conditions

Parameter

Symbol

Minimum

4.75

Maximum

Units

Power Supply Voltage

Forward Input Current (ON)

Forward Input Voltage (OFF)

Fan Out

5.25

I_F(ON)

0.8

F(OFF)

TTL Loads

Enable Voltage (Low)

HCPL-2400 Only)

0.8

Enable Voltage (High)

HCPL-2400 Only)

V_EH

T_A

Operating Temperature

°C

Electrical Speciﬁcations

0°C ≤T ≤70°C, 4.75 V ≤V_CC≤5.25 V, 4 mA ≤I_F(ON)≤8 mA, 0 V ≤V_F(OFF)≤0.8 V. All typicals at T_A=25°C, V_CC= 5 V, I_F(ON)= 6.0

mA, V_F^A_(OFF)= 0 V, except where noted. See Note 11.

Device

HCPL-

Parameter

Symbol

V_OL

Min. Typ.*

Max. Units

Test Conditions

Fig.

Note

Logic Low Output Voltage

0.5

I_OL= 8.0 mA (5 TTL Loads)

Logic High Output

Voltage

V_OH

2.4

2.7

I_OH= -4.0 mA

I_OH= -0.4 mA

Output Leakage Current

Logic High Enable Current

Logic Low Enable Voltage

Logic High Enable

I_OHH

V_EH

V_EL

I_EH

100

µA

V_O= 5.25 V, V_F= 0.8 V

2400

2.0

0.8

µA

V_E= 2.4 V

V_E= 5.25 V

V_E= 0.4 V

Current

100

Logic Low Enable Current

Logic Low Supply Current

I_EL

2400

-0.28 -0.4

I_CCL

V = 5.25 V, V_E= 0 V,

I_O^CC= Open

2430

2400

V = 5.25 V, I_O= Open

Logic High Supply

Current

I_CCH

V = 5.25 V, V_E= 0 V,

I_O^CC= Open

2430

2400

V = 5.25 V, I_O= Open

High Impedance State

Supply Current

I_CCZ

V = 5.25 V, V_E= 5.25 V

High Impedance State

Output Current

I_OZL

I_OZH

I_OSL

2400

µA

V_O= 0.4 V

V_O= 2.4 V

V_O= 5.25 V

V_E= 2 V

100

Logic Low Short Circuit

Output Current

V_O= V = 5.25 V,

I_F= 8 mA

Logic High Short Circuit

Output Current

I_OSH

-45

V = 5.25 V, I_F= 0 mA,

V = GND

Input Current Hysteresis

Input Forward Voltage

I_HYS

V_F

0.25

1.1

1.0

3.0

2.0

V_CC= 5 V

1.3

5.0

1.5

T = 25°C

I_F= 8 mA

1.55

Input Reverse Breakdown

Voltage

BV_R

T = 25°C

I_R= 10 µA

Temperature

Coeﬃcient of

Forward Voltage

∆V_F

∆T_A

-1.44

mV/°C I_F= 6 mA

Input Capacitance

C_IN

f = 1 MHz, V = 0 V

*All typical values at T = 25°C and V_CC= 5 V, unless otherwise noted.

Switching Speciﬁcations

0°C ≤ T ≤ 70°C, 4.75 V ≤ V_CC≤ 5.25 V, 4 mA ≤ I_F(ON)≤ 8 mA, 0 V ≤ V_F(OFF)≤ 0.8 V. All typicals at T = 25°C, V_CC= 5 V,

I_F(ON)= 6.0 mA, V_F(OFF)= 0 V, except where noted. See Note 11.

Device

HCPL-

Parameter

Symbol

Min.

Typ.*

Max.

Units

Test Conditions

Figure

Note

Propagation Delay

Time to Logic Low

Output Level

t_PHL

I_F(ON)= 7 mA

5, 6, 7

1, 4,

5, 6

Propagation Delay

Time to Logic High

Output Level

t_PLH

|t_PHL-t_PLH

t_PSK

I_F(ON)= 7 mA

5, 6, 7

5, 8

1, 4,

5, 6

Pulse Width

Distortion

I_F(ON)= 7 mA

Propagation Delay

Skew

Per Notes & Text

15, 16

Output Rise Time

Output Fall Time

t_r

t_f

Output Enable Time

to Logic High

t_PZH

2400

9, 10

Output Enable Time

to Logic Low

t_PZL

9, 10

Output Disable Time

from Logic High

t_PHZ

Output Disable Time

from Logic Low

t_PLZ

Logic High Common

Mode Transient

Immunity

|CM_H|

1000 10,000

0.5

V/µs

V_CM= 300 V, T = 25°C,

I_F= 0 mA

Logic Low Common

Mode Transient

Immunity

|CM_L|

PSNI

V/µs

V_CM= 300 V, T = 25°C,

I_F= 4 mA

Power Supply Noise

Immunity

V_CC= 5.0 V,

p-p

48 Hz ≤ = F ≤50 MHz

*All typical values at T = 25°C and V_CC= 5 V, unless otherwise noted.

Package Characteristics

Parameter

Sym.

Device

Min.

Typ.*

Max. Units Test Conditions

Fig.

Note

Input-Output

3750

V rms

RH ≤50%,

t = 1 min.,

3, 13

ISO

Momentary

Withstand Voltage**

T = 25°C

Input-Output

Resistance

Input-Output

Capacitance

Input-Input

Insulation Leakage

Current

R_I-O

C_I-O

I_I-I

10¹²

0.6

V_I-O= 500 Vdc

µA

f = 1 MHz

V_I-O= 0 Vdc

RH ≤45%

t = 5 s,

V_I-I= 500 Vdc

2430

0.005

Resistance

R_I-I

C_I-I

2430

10¹¹

0.25

V_I-I= 500 Vdc

f = 1 MHz

(Input-Input)

Capacitance

(Input-Input)

*All typical values are at T = 25°C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment lev-

el safety speciﬁcation or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,”publication number 5963-2203E.

Notes:

1. Each channel.

2. Duration of output short circuit time not to exceed 10 ms.

3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

4. t_PHLpropagation delay is measured from the 50% level on the rising edge of the input current pulse to the 1.5 V level on the falling edge of the

output pulse. The t_PLHpropagation delay is measured from the 50% level on the falling edge of the input current pulse to the 1.5 V level on the

rising edge of the output pulse.

5. The typical data shown is indicative of what can be expected using the application circuit in Figure 13.

6. This speciﬁcation simulates the worst case operating conditions of the HCPL-2400 over the recommended operating temperature and V_CCrange

with the suggested application circuit of Figure 13.

7. Propagation delay skew is discussed later in this data sheet.

8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.

9. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV_CM/dt of the common mode pulse, V_CM, to assure

that the output will remain in a Logic High state (i.e., V_O> 2.0 V). Common mode transient immunity in a Logic Low level is the maximum toler-

able (negative) dV_CM/dt of the common mode pulse, V_CM, to assure that the output will remain in a Logic Low state (i.e., V_O< 0.8 V).

10. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on theV_CCline that the device will withstand and still remain

in the desired logic state. For desired logic high state, V_OH(MIN)> 2.0 V, and for desired logic low state, V_OL(MAX)< 0.8 V.

11. Use of a 0.1 µF bypass capacitor connected between pins 8 and 5 adjacent to the device is required.

12. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.

13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500Vrms for one second (leakage detec-

tion current limit, I_I-O≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insulation Related

Characteristics Table, if applicable.

Figure 1. Typical logic low output voltage vs. logic low

output current.

Figure 2. Typical logic high output voltage vs. logic

high output current.

Figure 3. Typical output voltage vs. input forward

current.

Figure 4. Typical diode input forward current charac-

teristic.

Figure 5. Test circuit for t_PLH, t_PHL, t_r, and t_f.

Figure 6. Typical propagation delay vs. ambient

temperature.

Figure 7. Typical propagation delay vs. input forward

current.

Figure 8. Typical pulse width distortion vs. ambient

temperature.

Figure 9. Test circuit for t_PHZ, t_PZH, t_PLZand t_PZL.

Figure 10. Typical enable propagation delay vs. ambi-

ent temperature.

HCPL-2400/11

1 NC

0.1 µF *

OUTPUT V

MONITORING NODE

–

†

4 NC

GND

= 15 pF

800

(mW)

700

600

500

400

300

200

100

–

(mA)

PULSE GENERATOR

25 50 75 100 125 150 175 200

– CASE TEMPERATURE – °C

Figure 11. Test diagram for common mode transient immunity and typical waveforms.

Figure 12. Thermal derating curve, dependence of

safety limiting value with case temperature per

IEC/EN/DIN EN 60747-5-2.

Applications

Figure 13. Recommended 20 MBd HCPL-2400/30 interface circuit.

Figure 14. Alternative HCPL-2400/30 interface circuit.

DATA

INPUTS

CLOCK

50%

1.5 V

DATA

OUTPUTS

PSK

1.5 V

CLOCK

PSK

Figure 15. Illustration of propagation delay skew – t_PSK

Figure 16. Parallel data transmission example.

Figure 17. Modulation code selections.

Figure 18. Typical HCPL-2400/30 output schematic.

Propagation delay skew represents the uncertainty of

where an edge might be after being sent through an

optocoupler. Figure16 shows that there will be uncer-

tainty in both the data and the clock lines. It is impor-

tant that these two areas of uncertainty not overlap,

otherwise the clock signal might arrive before all of the

data outputs have settled, or some of the data outputs

may start to change before the clock signal has arrived.

From these considerations, the absolute minimum pulse

width that can be sent through optocouplers in a par-

allel application is twice t_PHZ. A cautious design should

use a slightly longer pulse width to ensure that any addi-

tional uncertainty in the rest of the circuit does not cause

a problem.

Propagation Delay, Pulse-Width Distortion and Propa-

gation Delay Skew

Propagation delay is a ﬁgure of merit which describes

how quickly a logic signal propagates through a sys-

tem. The propagation delay from low to high (t_PLH) is the

amount of time required for an input signal to propa-

gate to the output, causing the output to change from

low to high. Similarly, the propagation delay from high

to low (t_PHL) is the amount of time required for the input

signal to propagate to the output, causing the output to

change from high to low (see Figure 5).

Pulse-width distortion (PWD) results when t_PLHand t_PHL

diﬀer in value. PWD is deﬁned as the diﬀerence between

t_PLHand t_PHLand often determines the maximum data

rate capability of a transmission system. PWD can be ex-

pressed in percent by dividing the PWD (in ns) by the

minimum pulse width (in ns) being transmitted. Typi-

cally, PWD on the order of 20-30% of the minimum pulse

width is tolerable; the exact ﬁgure depends on the par-

ticular application (RS232, RS422, T-1, etc.).

The HCPL-2400/30 optocouplers oﬀer the advantages of

guaranteed speciﬁcations for propagation delays, pulse-

width distortion, and propagation delay skew over the

recommended temperature, input current, and power

supply ranges.

Application Circuit

A recommended LED drive circuit is shown in Figure 13.

This circuit utilizes several techniques to minimize the

total pulse-width distortion at the output of the opto-

coupler. By using two inverting TTL gates connected in

series, the inherent pulse-width distortion of each gate

cancels the distortion of the other gate. For best results,

the two series-connected gates should be from the same

package.

Propagation delay skew, t_PSK, is an important param-

eter to consider in parallel data applications where

synchronization of signals on parallel data lines is a con-

cern. If the parallel data is being sent through a group

of optocouplers, diﬀerences in propagation delays will

cause the data to arrive at the outputs of the optocou-

plers at diﬀerent times. If this diﬀerence in propagation

delays is large enough, it will determine the maximum

rate at which parallel data can be sent through the op-

tocouplers.

The circuit in Figure 13 also uses techniques known as

prebias and peaking to enhance the performance of the

optocoupler LED. Prebias is a small forward voltage ap-

plied to the LED when the LED is oﬀ. This small prebias

voltage partially charges the junction capacitance of the

LED, allowing the LED to turn on more quickly. The speed

of the LED is further increased by applying momentary

current peaks to the LED during the turn-on and turn-oﬀ

transitions of the drive current. These peak currents help

to charge and discharge the capacitances of the LED

more quickly, shortening the time required for the LED

to turn on and oﬀ.

Propagation delay skew is deﬁned as the diﬀerence be-

tween the minimum and maximum propagation delays,

either t_PLHor t_PHL, for any given group of optocouplers

which are operating under the same conditions (i.e., the

same drive current, supply voltage, output load, and op-

erating temperature). As illustrated in Figure15, if the in-

puts of a group of optocouplers are switched either ON

or OFF at the same time, t_PSKis the diﬀerence between

the shortest propagation delay, either t_PLHor t_PHL, and the

longest pro-pagation delay, either t_PLHor t_PHL

As mentioned earlier, t_PSKcan determine the maximum

parallel data transmission rate. Figure 16 is the timing

diagram of a typical parallel data application with both

the clock and the data lines being sent through opto-

couplers. The ﬁgure shows data and clock signals at the

inputs and outputs of the optocouplers. To obtain the

maximum data transmission rate, both edges of the

clock signals are being used to clock the data; if only one

edge were used, the clock signal would need to be twice

as fast.

Switching performance of the HCPL-2400/30 optocou- the output of the optocoupler, but will not necessarily

plers is not sensitive to the TTL logic family used in the result in lower pulse-width distortion or propagation de-

recommended drive circuit. The typical and worst-case lay skew. This reduction in overall propagation delay is

switching parameters given in the data sheet can be due to shorter delays in the drive circuit, not to changes

met using common 74LS TTL inverting gates or buﬀers.

Use of faster TTL families will slightly reduce the overall

propagation delays from the input of the drive circuit to

in the propagation delays of the optocoupler; optocou-

pler propagation delays are not aﬀected by the speed of

the logic used in the drive circuit.

For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.

AV02-0962EN - January 4, 2008

HCPL-2400#300 替代型号

型号	制造商	描述	替代类型	文档
HCPL-2400#500	AVAGO	1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps, DIP-8	类似代替

HCPL-2400#300 相关器件

型号	制造商	描述	价格	文档
HCPL-2400#500	AVAGO	1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps, DIP-8	获取价格
HCPL-2400-000E	AVAGO	20 MBd High CMR Logic Gate Optocouplers	获取价格
HCPL-2400-060E	AVAGO	20 MBd High CMR Logic Gate Optocouplers	获取价格
HCPL-2400-300E	AVAGO	20 MBd High CMR Logic Gate Optocouplers	获取价格
HCPL-2400-360E	AVAGO	20 MBd High CMR Logic Gate Optocouplers	获取价格
HCPL-2400-500	AVAGO	暂无描述	获取价格
HCPL-2400-500E	AVAGO	20 MBd High CMR Logic Gate Optocouplers	获取价格
HCPL-2411	AVAGO	1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps	获取价格
HCPL-2411-000E	AVAGO	1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40Mbps	获取价格
HCPL-2411-300E	AVAGO	20 m baud high cmr logic gate optocoupler	获取价格