HCPL-2611 [AVAGO]
High CMR, High Speed TTL Compatible Optocouplers; 高CMR ，高速TTL兼容光电耦合器
| 型号： | HCPL-2611 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | High CMR, High Speed TTL Compatible Optocouplers |
| 文件： | 总22页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6N137, HCNW137, HCNW2601, HCNW2611, HCPL-0600,
HCPL-0601, HCPL-0611, HCPL-0630, HCPL-0631, HCPL-0661,
HCPL-2601, HCPL-2611, HCPL-2630, HCPL-2631, HCPL-4661
High CMR, High Speed TTL Compatible Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
ꢀꢁ 15 kV/μs minimum Common Mode Rejection (CMR)
at VCM = 1KV for HCNW2611, HCPL-2611, HCPL-4661,
HCPL-0611, HCPL-0661
ꢀꢁ High speed: 10 MBd typical
ꢀꢁ LSTTL/TTL compatible
The 6N137, HCPL-26XX/06XX/4661, HCNW137/26X1 are
optically coupled gates that combine a GaAsP light emit-
ting diode and an integrated high gain photo detector.
An enable input allows the detector to be strobed. The
output of the detector IC is an open collector Schottky-
clamped transistor. The internal shield provides a guar-
anteed common mode transient immunity specification
up to 15,000 V/μs at Vcm=1000V.
ꢀꢁ Low input current capability: 5 mA
ꢀꢁ Guaranteed ac and dc performance over temperature:
-40°C to +85°C
Thisuniquedesignprovidesmaximumacanddccircuitiso-
lation while achievingTTL compatibility.The optocoupler
ac and dc operational parameters are guaranteed from -
40°C to +85°C allowing troublefree system performance.
ꢀꢁ Available in 8-Pin DIP, SOIC-8, widebody packages
ꢀꢁ Strobable output (single channel products only)
ꢀꢁ Safety approval
UL recognized - 3750 V rms for 1 minute and 5000
Vrms* for 1 minute per UL1577 CSA approved
IEC/EN/DIN EN 60747-5-2 approved with
Functional Diagram
V
IORM = 560 V peak for 06xx Option 060
6N137, HCPL-2601/2611
HCPL-0600/0601/0611
HCPL-2630/2631/4661
HCPL-0630/0631/0661
VIORM = 630 V peak for 6N137/26xx Option 060
VIORM =1414 V peak for HCNW137/26X1
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
NC
CC
CC
O1
O2
1
1
ꢀꢁ MIL-PRF-38534 hermetic version available
(HCPL-56XX/66XX)
ANODE
E
V
CATHODE
NC
3
4
6
5
3
4
6
5
O
2
2
Applications
GND
GND
SHIELD
SHIELD
ꢀꢁ Isolated line receiver
ꢀꢁ Computer-peripheral interfaces
ꢀꢁ Microprocessor system interfaces
ꢀꢁ Digital isolation for A/D, D/A conversion
ꢀꢁ Switching power supply
ꢀꢁ Instrument input/output isolation
ꢀꢁ Ground loop elimination
TRUTH TABLE
TRUTH TABLE
(POSITIVE LOGIC)
(POSITIVE LOGIC)
LED ENABLE OUTPUT
LED OUTPUT
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
ON
L
OFF
H
H
ꢀꢁ Pulse transformer replacement
ꢀꢁ Power transistor isolation in motor drives
ꢀꢁ Isolation of high speed logic systems
A 0.1 ꢂF bypass capacitor must be connected between pins 5 and 8.
*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020
(6N137, HCPL-2601/11/30/31, HCPL-4661) products only.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
The6N137,HCPL-26XX,HCPL-06XX,HCPL-4661,HCNW137,
and HCNW26X1 are suitable for high speed logic interfac-
ing, input/output buffering, as line receivers in environ-
ments that conventional line receivers cannot tolerate
and are recommended for use in extremely high ground
or induced noise environments.
Selection Guide
Widebody
(400 Mil)
Minimum CMR
8-Pin DIP (300 Mil)
Small-Outline SO-8
Hermetic
Input
On-
Current Output
(mA)
Single
and Dual
Channel
Packages
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
dV/dt
(V/μs)
V
(V)
CM
Enable
YES
YES
NO
1000
10
5
5
6N137
5,000
1,000
HCPL-0600
HCPL-0601
HCPL-0611
HCNW137
HCNW2601
HCNW2611
HCPL-2630
HCPL-2631
HCPL-4661
HCPL-0630
HCPL-0631
HCPL-0661
10,000
15,000
1,000
1,000
YES
NO
HCPL-2601
HCPL-2611
YES
NO
1,000
3, 500
1,000
50
300
50
YES
YES
YES
NO
HCPL-2602[1]
HCPL-2612[1]
HCPL-261A[1]
3
HCPL-061A[1]
HCPL-061N[1]
HCPL-263A[1]
HCPL-263N[1]
HCPL-063A[1]
HCPL-063N[1]
1,000[2]
1,000
1,000
50
YES
HCPL-261N[1]
NO
[3]
12.5
HCPL-193X[1]
HCPL-56XX[1]
HCPL-66XX[1]
Notes:
1. Technical data are on separate Avago publications.
2. 15 kV/μs with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
2
Ordering Information
HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577.
HCNWxxxx is UL Rcognized with 5000 Vrms for 1 minute per UL1577.
Option
UL 5000 Vrms/
1 Minute
Part
RoHS
Non RoHS
Surface Gull Tape &
IEC/EN/DIN
Number
Compliant Compliant
Package
Mount Wing
Reel
Rating
EN 60747-5-2 Quantity
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-560E
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-300E
-500E
-020E
-320E
-520E
-000E
-300E
-500E
-020E
-320E
-520E
No option
#300
50 per tube
X
X
X
X
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
#500
X
#020
X
X
X
6N137
300mil
DIP-8
#320
X
X
X
X
#520
X
X
#060
X
X
-560
X
X
No option
#300
X
X
X
X
#500
X
X
#020
X
X
X
300mil
DIP-8
HCPL-2601
#320
X
X
X
X
#520
#060
X
X
-
X
X
No option
#300
X
X
X
X
#500
X
X
X
X
X
X
X
#020
X
X
X
HCPL-2611
300mil
DIP-8
#320
X
X
X
X
#520
#060
X
X
X
#360
X
X
X
X
#560
No option
#300
X
X
X
X
#500
HCPL-2630
300mil
DIP-8
#020
X
X
X
#320
X
X
X
X
-520
No option
#300
X
X
X
X
#500
HCPL-2631
HCPL-4661
300mil
DIP-8
#020
X
X
X
#320
X
X
X
X
#520
3
Option
UL 5000 Vrms/
1 Minute
Part
RoHS
Non RoHS
Surface Gull Tape &
IEC/EN/DIN
Number
Compliant Compliant
Package
Mount Wing
Reel
Rating
EN 60747-5-2 Quantity
-000E
-500E
-060E
-560E
-000E
-500E
No option
#500
X
X
X
X
X
X
100 per tube
HCPL-0600
HCPL-0601
HCPL-0611
X
1500 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
SO-8
#060
X
X
#560
X
HCPL-0630
HCPL-0631
HCPL-0661
No option
#500
SO-8
X
-000E
-300E
-500E
No option
#300
X
X
X
X
X
X
42 per tube
42 per tube
750 per reel
HCNW137
HCNW2601
HCNW2611
400 mil
DIP-8
X
X
X
X
#500
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
HCPL-2611-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packag
ing with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-2630 to order product of 300mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Notes:
The notation ‘#XXX’is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘.
Schematic
HCPL-2630/2631/4661
HCPL-0630/0631/0661
6N137, HCPL-2601/2611
I
CC
I
HCPL-0600/0601/0611
V
V
CC
O1
8
7
HCNW137, HCNW2601/2611
I
F
1
+
I
I
F1
CC
V
V
O1
CC
O
8
6
2+
I
O
V
F1
–
2
V
F
SHIELD
–
3
3
–
GND
I
F2
5
I
O2
SHIELD
I
V
E
7
E
O2
6
5
V
V
F2
USE OF A 0.1 μF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
+
4
GND
SHIELD
4
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
7.62 0.25
(0.300 0.010)
9.65 0.25
(0.380 0.010)
8
1
7
6
5
6.35 0.25
(0.250 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
3.56 0.13
(0.140 0.005)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 0.320
(0.043 0.013)
0.65 (0.025) MAX.
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
**JEDEC Registered Data (for 6N137 only).
8-pin DIP Package with Gull Wing Surface Mount Option 300
(6N137, HCPL-2601/11/30/31, HCPL-4661)
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 0.25
(0.380 0.010)
6
5
8
1
7
6.350 0.25
(0.250 0.010)
10.9 (0.430)
2
3
4
2.0 (0.080)
1.27 (0.050)
9.65 0.25
1.780
(0.070)
MAX.
(0.380 0.010)
1.19
(0.047)
MAX.
7.62 0.25
(0.300 0.010)
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 0.320
(0.043 0.013)
0.635 0.25
(0.025 0.010)
12° NOM.
0.635 0.130
(0.025 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
5
Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 0.203
(0.236 0.008)
XXX
YWW
3.937 0.127
(0.155 0.005)
7.49 (0.295)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
3
1.9 (0.075)
PIN ONE
0.406 0.076
(0.016 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
(0.017)
*
7°
5.080 0.127
(0.200 0.005)
45° X
3.175 0.127
(0.125 0.005)
0 ~ 7°
0.228 0.025
(0.009 0.001)
1.524
(0.060)
0.203 0.102
(0.008 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 0.254 (0.205 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)
11.ꢀꢀ
MAX.
11.23 ꢀ.15
(ꢀ.442 ꢀ.ꢀꢀ6ꢁ
(ꢀ.433ꢁ
9.ꢀꢀ ꢀ.15
(ꢀ.354 ꢀ.ꢀꢀ6ꢁ
7
6
5
8
TYPE NUMBER
DATE CODE
A
HCNWXXXX
YYWW
1
3
2
4
1ꢀ.16 (ꢀ.4ꢀꢀꢁ
TYP.
1.55
(ꢀ.ꢀ61ꢁ
MAX.
7° TYP.
+ ꢀ.ꢀ76
- ꢀ.ꢀꢀ51
ꢀ.254
+ ꢀ.ꢀꢀ3ꢁ
- ꢀ.ꢀꢀ2ꢁ
(ꢀ.ꢀ1ꢀ
5.1ꢀ
(ꢀ.2ꢀ1ꢁ
MAX.
3.1ꢀ (ꢀ.122ꢁ
3.9ꢀ (ꢀ.154ꢁ
ꢀ.51 (ꢀ.ꢀ21ꢁ MIN.
2.54 (ꢀ.1ꢀꢀꢁ
TYP.
1.8ꢀ ꢀ.15
(ꢀ.ꢀ71 ꢀ.ꢀꢀ6ꢁ
ꢀ.4ꢀ (ꢀ.ꢀ16ꢁ
ꢀ.56 (ꢀ.ꢀ22ꢁ
DIMENSIONS IN MILLIMETERS (INCHESꢁ.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.25 mm (1ꢀ milsꢁ MAX.
6
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300
(HCNW137, HCNW2601/11)
11.23 ꢀ.15
(ꢀ.442 ꢀ.ꢀꢀ6ꢁ
LAND PATTERN RECOMMENDATION
7
6
5
8
9.ꢀꢀ ꢀ.15
(ꢀ.354 ꢀ.ꢀꢀ6ꢁ
13.56
(ꢀ.534ꢁ
1
3
2
4
2.29
(ꢀ.ꢀ9ꢁ
1.3
(ꢀ.ꢀ51ꢁ
12.3ꢀ ꢀ.3ꢀ
1.55
(ꢀ.ꢀ61ꢁ
MAX.
(ꢀ.484 ꢀ.ꢀ12ꢁ
11.ꢀꢀ
MAX.
(ꢀ.433ꢁ
4.ꢀꢀ
MAX.
(ꢀ.158ꢁ
1.8ꢀ ꢀ.15
(ꢀ.ꢀ71 ꢀ.ꢀꢀ6ꢁ
1.ꢀꢀ ꢀ.15
(ꢀ.ꢀ39 ꢀ.ꢀꢀ6ꢁ
ꢀ.75 ꢀ.25
(ꢀ.ꢀ3ꢀ ꢀ.ꢀ1ꢀꢁ
+ ꢀ.ꢀ76
- ꢀ.ꢀꢀ51
2.54
ꢀ.254
(ꢀ.1ꢀꢀꢁ
+ ꢀ.ꢀꢀ3ꢁ
- ꢀ.ꢀꢀ2ꢁ
BSC
(ꢀ.ꢀ1ꢀ
DIMENSIONS IN MILLIMETERS (INCHESꢁ.
7° NOM.
LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢁ.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.25 mm (1ꢀ milsꢁ MAX.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C 0.5 °C/SEC.
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
PEAK
TEMP.
230 °C
200
100
0
2.5 C 0.5 °C/SEC.
SOLDERING
30
TIME
160 °C
150 °C
140 °C
SEC.
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
ROOM
TEMPERATURE
LOOSE
0
50
100
150
200
250
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
7
Recommended Pb-free IR Profile
TIMEWITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
15 SEC.
* 260 +0/-5 °C
Tp
TL
217 °C
NOTES:
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
THETIME FROM 25 °C to PEAK
TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
150 - 200 °C
Tsmax
Tsmin
NOTE: NON-HALIDE FLUX SHOULD BE USED.
ts
tL
PREHEAT
60 to 180 SEC.
60 to 150 SEC.
* RECOMMENDED PEAK TEMPERATURE FOR
WIDEBODY 400mils PACKAGE IS 245 °C
25
t 25 °C to PEAK
TIME
Regulatory Information
The 6N137, HCPL-26XX/06XX/46XX, and HCNW137/26XX have been approved by the following organizations:
UL
IEC/EN/DIN EN 60747-5-2
Recognized under UL 1577, Component Recognition
Program, File E55361.
Approved under
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
(Option 060 and HCNW only)
CSA
Approved under CSA Component Acceptance Notice
#5, File CA 88324.
Insulation and Safety Related Specifications
8-pin DIP
Widebody
(400 Mil)
Value
(300 Mil)
Value
SO-8
Value
Parameter
Symbol
Units Conditions
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
7.4
4.9
9.6
mm
mm
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking (External
Creepage)
L(102)
4.8
10.0
1.0
Measured from input terminals
to output terminals, shortest
distance path along body.
Minimum Internal
Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
Minimum Internal
Tracking (Internal
Creepage)
NA
200
IIIa
NA
200
IIIa
4.0
200
IIIa
mm
Measured from input terminals
to output terminals, along
internal cavity.
Tracking Resistance
(Comparative
Tracking Index)
CTI
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
8
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
(HCPL-06xx Option 060 Only)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
I-IV
I-III
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 600 V rms
Climatic Classification
I-III
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
V
567
Vpeak
Vpeak
IORM
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
VPR
1063
851
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage, tini = 10 sec)
VIOTM
6000
Vpeak
Safety Limiting Values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current**
TS
IS,INPUT
PS,OUTPUT
150
150
600
°C
mA
mW
Output Power**
Insulation Resistance at TS, V = 500 V
RS
≥109
ꢃ
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in applica-
tion.
9
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
(HCPL-26xx; 46xx; 6N13x Option 060 Only)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
I-IV
I-III
for rated mains voltage ≤ 450 V rms
Climatic Classification
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
V
630
Vpeak
Vpeak
IORM
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
VPR
1181
945
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test,
Vpeak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
VIOTM
6000
Vpeak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, V = 500 V
RS
≥109
ꢃ
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in applica-
tion.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (HCNW137/2601/2611 Only)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤600 V rms
I-IV
I-III
for rated mains voltage ≤1000 V rms
Climatic Classification (DIN IEC 68 part 1)
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
55/100/21
2
V
1414
Vpeak
Vpeak
IORM
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
VPR
2651
2121
8000
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test,
Vpeak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
VIOTM
Vpeak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
150
400
700
°C
mA
mW
Insulation Resistance at TS, V = 500 V
RS
≥109
ꢃ
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in applica-
tion.
10
Absolute Maximum Ratings* (No Derating Required up to 85°C)
Parameter
Symbol
Package**
Min.
-55
-40
Max.
125
85
Units
°C
Note
Storage Temperature
Operating Temperature†
Average Forward Input Current
TS
T
°C
A
IF
Single 8-Pin DIP
Single SO-8
Widebody
20
mA
2
Dual 8-Pin DIP
Dual SO-8
15
1, 3
1
Reverse Input Voltage
Input Power Dissipation
VR
PI
8-Pin DIP, SO-8
Widebody
5
3
V
Widebody
40
7
mW
V
Supply Voltage
V
CC
(1 Minute Maximum)
Enable Input Voltage (Not to
Exceed VCC by more than
500 mV)
VE
Single 8-Pin DIP
Single SO-8
Widebody
V + 0.5
V
CC
Enable Input Current
IE
IO
5
50
7
mA
mA
V
Output Collector Current
Output Collector Voltage
1
1
VO
PO
Output Collector Power
Dissipation
Single 8-Pin DIP
Single SO-8
Widebody
85
mW
Dual 8-Pin DIP
Dual SO-8
60
1, 4
Lead Solder Temperature
(Through Hole Parts Only)
TLS
8-Pin DIP
260°C for 10 sec.,
1.6 mm below seating plane
Widebody
260°C for 10 sec.,
up to seating plane
Solder Reflow Temperature
Profile (Surface Mount Parts Only)
SO-8 and
Option 300
See Package Outline
Drawings section
*JEDEC Registered Data (for 6N137 only).
**Ratings apply to all devices except otherwise noted in the Package column.
†0°C to 70°C on JEDEC Registration.
Recommended Operating Conditions
Parameter
Symbol
Min.
0
Max.
250
15
Units
μA
mA
V
Input Current, Low Level
Input Current, High Level[1]
Power Supply Voltage
Low Level Enable Voltage†
High Level Enable Voltage†
Operating Temperature
Fan Out (at RL = 1 kΩ)[1]
Output Pull-up Resistor
IFL*
IFH**
5
V
4.5
0
5.5
CC
VEL
VEH
TA
0.8
V
2.0
-40
V
V
CC
85
5
°C
N
TTL Loads
RL
330
4 k
ꢃ
*The off condition can also be guaranteed by ensuring that VFL ≤0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20%
LED degradation guardband.
†For single channel products only.
11
Electrical Specifications
Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V, TA = 25°C.
All enable test conditions apply to single channel products only. See note 5.
Parameter
Sym.
Package
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
High Level Output
Current
IOH*
All
5.5
100
μA
V = 5.5 V, VE = 2.0 V,
1
1, 6,
19
CC
V = 5.5 V, IF = 250 mA
O
Input Threshold
Current
ITH
Single Channel
Widebody
2.0
5.0
0.6
mA
V
V = 5.5 V, VE = 2.0 V,
2, 3
19
1, 19
7
CC
VO = 0.6 V,
Dual Channel
2.5
IOL (Sinking) = 13 mA
Low Level Output
Voltage
VOL*
8-Pin DIP
SO-8
0.35
VCC = 5.5 V, VE = 2.0 V,
IF = 5 mA,
2, 3,
4, 5
Widebody
0.4
IOL (Sinking) = 13 mA
High Level Supply
Current
ICCH
Single Channel
7.0
6.5
10
10.0*
15
mA
VE = 0.5 V
VE = VCC
Both
V = 5.5 V
CC
IF = 0 mA
Dual Channel
Channels
Low Level Supply
Current
ICCL
Single Channel
Dual Channel
9.0
8.5
13
13.0*
21
mA
VE = 0.5 V
VE = VCC
Both
V = 5.5 V
8
CC
IF = 10 mA
Channels
High Level Enable
Current
IEH
IEL*
VEH
VEL
VF
Single Channel
-0.7
-0.9
-1.6
-1.6
mA
mA
V
VCC = 5.5 V, V = 2.0 V
E
Low Level Enable
Current
VCC = 5.5 V, V = 0.5 V
9
E
High Level Enable
Voltage
2.0
19
Low Level Enable
Voltage
0.8
V
Input Forward
Voltage
8-Pin DIP
SO-8
1.4
1.3
1.5
1.75*
1.80
1.85
2.05
V
TA = 25°C
TA = 25°C
IF = 10 mA
6, 7
1
Widebody
1.25
1.2
1.64
Input Reverse
Breakdown
Voltage
BV *
8-Pin DIP
SO-8
5
V
IR = 10 ꢀA
1
1
1
R
Widebody
3
IR = 100 μA, TA = 25°C
Input Diode
Temperature
Coefficient
DV /
8-Pin DIP
SO-8
-1.6
mV/°C IF = 10 mA
7
F
∆T
A
Widebody
-1.9
60
Input Capacitance
CIN
8-Pin DIP
SO-8
pF
f = 1 MHz, VF = 0 V
Widebody
70
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.
12
Switching Specifications (AC)
Over Recommended Temperature (T = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
A
All Typicals at T = 25°C, VCC = 5 V.
A
Parameter
Sym.
Package**
Min. Typ. Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
Time to High
tPLH
20
48
75*
100
ns
T = 25°C
RL = 350 ꢃ
CL = 15 pF
8, 9, 1, 10,
A
10
19
Output Level
Propagation Delay
Time to Low
Output Level
tPHL
25
50
75*
100
ns
ns
T = 25°C
1, 11,
19
A
Pulse Width
Distortion
|tPHL - tPLH
|
8-Pin DIP
SO-8
Widebody
3.5
35
8, 9, 13, 19
10,
11
40
40
Propagation Delay
Skew
tPSK
tr
ns
ns
ns
ns
12, 13,
19
Output Rise
Time (10-90%)
24
10
30
12
12
1, 19
1, 19
14
Output Fall
Time (90-10%)
tf
Propagation Delay
Time of Enable
from VEH to VEL
tELH
Single Channel
Single Channel
RL = 350 ꢃ,
CL = 15 pF,
VEL = 0 V, VEH = 3 V
13,
14
Propagation Delay
Time of Enable
from VEL to VEH
tEHL
20
ns
15
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter
Sym.
Device
Min.
Typ.
Units
Test Conditions
Fig.
Note
Logic High
Common
Mode
Transient
Immunity
|CMH| 6N137
1,000 10,000 V/μs |V | = 10 V
VCC = 5 V, IF = 0 mA,
VO(MIN) = 2 V,
15
1, 16,
18, 19
CM
HCPL-2630
HCPL-0600/0630
HCNW137
HCPL-2601/2631 10,000 15,000
HCPL-0601/0631
HCNW2601
5,000 10,000
|VCM| = 1 kV
|VCM| = 1 kV
|VCM| = 1 kV
RL = 350 ꢀ, T = 25°C
A
HCPL-2611/4661 15,000 25,000
HCPL-0611/0661
HCNW2611
Logic Low
Common
Mode
Transient
Immunity
|CML| 6N137
HCPL-2630
1,000 10,000 V/μs |V | = 10 V
VCC = 5 V, IF = 7.5 mA,
VO(MAX) = 0.8 V,
15
1, 17,
18, 19
CM
5,000 10,000
|V | = 1 kV
CM
HCPL-0600/0630
HCNW137
HCPL-2601/2631 10,000 15,000
HCPL-0601/0631
HCNW2601
HCPL-2611/4661 15,000 25,000
HCPL-0611/0661
RL = 350 ꢀ, T = 25°C
A
|VCM| = 1 kV
|VCM| = 1 kV
HCNW2611
13
Package Characteristics
All Typicals at T = 25°C.
A
Parameter
Sym.
Package
Min.
Typ.
Max.
Units
Test Conditions
45% RH, t = 5 s,
I-O = 3 kV dc, T = 25°C
Fig.
Note
Input-Output
Insulation
II-O*
VISO
Single 8-Pin DIP
Single SO-8
1
ꢁA
20, 21
V
A
Input-Output
Momentary With-
stand Voltage**
8-Pin DIP, SO-8
Widebody
OPT 020†
3750
5000
5000
V rms RH ≤ 50%, t = 1 min,
20, 21
20, 22
T = 25°C
A
Input-Output
Resistance
RI-O
8-Pin DIP, SO-8
Widebody
1012
1013
ꢀ
VI-O = 500 V dc
1, 20,
23
1012
1011
T = 25°C
A
T = 100°C
A
Input-Output
Capacitance
CI-O
II-I
8-Pin DIP, SO-8
Widebody
0.6
0.5
pF
f = 1 MHz, T = 25°C
1, 20,
23
A
0.6
Input-Input
Insulation
Dual Channel
0.005
ꢁA
RH ≤ 45%, t = 5 s,
24
V = 500 V
I-I
Leakage Current
Resistance
(Input-Input)
RI-I
CI-I
Dual Channel
1011
ꢀ
24
24
Capacitance
(Input-Input)
Dual 8-Pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. Avago specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous volt-
age rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment
level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 μA. Avago guarantees a maximum IOH of 100 ꢁA.
7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. Avago guarantees a maximum ICCH of 10 mA.
8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. Avago guarantees a maximum ICCL of 13 mA.
9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. Avago guarantees a maximum IEL of -1.6 mA.
10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions.
13. See application section titled“Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew”for more information.
14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge
of the output pulse.
15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge
of the output pulse.
16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V).
17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V).
18. For sinusoidal voltages, (|dVCM | / dt)max = ꢂfCMVCM(p-p).
19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR
performance. For single channel products only.
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for one second (leakage detection
current limit, II-O ≤ 5 ꢁA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
5-2 Insulation Characteristics Table, if applicable.
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second (leakage detection
current limit, II-O ≤ 5 ꢁA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
5-2 Insulation Characteristics Table, if applicable.
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only
14
8-PIN DIP, SO-8
WIDEBODY
6
6
15
1ꢀ
V
T
= 5 V
V
= 5 V
CC
= 25 °C
CC
T = 25 °C
A
V
V
V
= 5.5 V
= 5.5 V
= 2.ꢀ V*
= 25ꢀ μA
CC
O
E
A
5
4
3
2
5
4
3
2
I
F
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
R
= 35ꢀ Ω
= 1 KΩ
R
= 35ꢀ Ω
= 1 KΩ
L
L
R
R
L
L
5
ꢀ
R
= 4 KΩ
R = 4 KΩ
L
L
1
ꢀ
1
ꢀ
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ 6ꢀ 8ꢀ 1ꢀꢀ
ꢀ
1
2
3
4
6
ꢀ
1
2
3
4
6
5
5
T
– TEMPERATURE – °C
I
– FORWARD INPUT CURRENT – mA
I – FORWARD INPUT CURRENT – mA
F
A
F
Figure 1. Typical high level output current vs.
temperature.
Figure 2. Typical output voltage vs. forward input current.
WIDEBODY
6
8-PIN DIP, SO-8
6
V
V
= 5.ꢀ V
V
V
= 5.ꢀ V
CC
= ꢀ.6 V
CC
= ꢀ.6 V
O
O
5
4
3
2
5
4
3
2
R
= 35ꢀ Ω
L
R
= 1 KΩ
R
= 35ꢀ Ω
= 4 KΩ
L
L
R
= 1 KΩ
L
1
ꢀ
1
ꢀ
R
R
= 4 KΩ
L
L
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
6ꢀ
6ꢀ
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 3. Typical input threshold current vs. temperature.
15
8-PIN DIP, SO-8
WIDEBODY
ꢀ.8
ꢀ.7
ꢀ.8
ꢀ.7
7ꢀ
6ꢀ
5ꢀ
V
V
I
= 5.5 V * FOR SINGLE
V
V
I
= 5.5 V
V
V
V
= 5.ꢀ V
= 2.ꢀ V*
= ꢀ.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
CC
E
F
CC
E
F
CC
E
OL
= 2.ꢀ V*
= 5.ꢀ mA
CHANNEL
PRODUCTS ONLY
= 2.ꢀ V
= 5.ꢀ mA
ꢀ.6
ꢀ.5
ꢀ.4
ꢀ.3
ꢀ.2
ꢀ.6
ꢀ.5
ꢀ.4
ꢀ.3
ꢀ.2
I
= 16 mA
O
I
= 1ꢀ-15 mA
F
I
= 16 mA
I
= 12.8 mA
O
O
I
= 12.8 mA
= 6.4 mA
O
I
I
= 9.6 mA
I = 6.4 mA
O
O
I
= 9.6 mA
O
I
= 5.ꢀ mA
F
4ꢀ
2ꢀ
O
ꢀ.1
ꢀ.1
ꢀ
ꢀ
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
6ꢀ
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
6ꢀ
6ꢀ
T
– TEMPERATURE – °C
T – TEMPERATURE – °C
A
T
– TEMPERATURE – °C
A
A
Figure 4. Typical low level output voltage vs. temperature.
Figure 5. Typical low level output current vs.
temperature.
8-PIN DIP, SO-8
WIDEBODY
1ꢀꢀꢀ
1000
T
A
= 25 o
C
T
= 25 °C
A
1ꢀꢀ
1ꢀ
100
10
I
I
+
F
F
F
+
F
V
V
–
-
1.ꢀ
1.0
ꢀ.1
ꢀ.ꢀ1
0.1
0.01
ꢀ.ꢀꢀ1
0.001
1.1
1.2
1.3
1.4
1.5
1.6
1.2
1.3
1.4
1.5
1.6
1.7
V
– FORWARD VOLTAGE – V
V
- FORWARD VOLTAGE - V
F
F
Figure 6. Typical input diode forward characteristic.
WIDEBODY
8-PIN DIP, SO-8
-2.3
-2.4
-2.2
-2.ꢀ
-1.8
-1.6
-2.2
-2.1
-2.ꢀ
-1.9
-1.8
-1.4
-1.2
ꢀ.1
1
1ꢀ
1ꢀꢀ
ꢀ.1
1
1ꢀ
1ꢀꢀ
I
– PULSE INPUT CURRENT – mA
I
– PULSE INPUT CURRENT – mA
F
F
Figure 7. Typical temperature coefficient of forward voltage vs. input current.
16
PULSE GEN.
= 5ꢀ Ω
Z
f
O
t
= t = 5 ns
r
SINGLE CHANNEL
DUAL CHANNEL
V
+5 V
+5 V
I
F
I
F
PULSE GEN.
V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC
CC
Z
= 5ꢀ Ω
O
R
L
t
= t = 5 ns
f
r
INPUT
MONITORING
NODE
OUTPUT V
O
MONITORING
NODE
ꢀ.1μF
BYPASS
R
L
ꢀ.1μF
BYPASS
OUTPUT V
MONITORING
NODE
INPUT
MONITORING
NODE
O
*C
L
R
C *
L
M
R
M
GND
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
I
= 7.5ꢀ mA
= 3.75 mA
F
INPUT
I
I
F
F
t
t
PHL
PLH
OUTPUT
V
O
1.5 V
Figure 8. Test circuit for tPHL and tPLH
.
1ꢀꢀ
1ꢀ5
9ꢀ
V
I
= 5.ꢀ V
V
A
= 5.ꢀ V
CC
= 7.5 mA
CC
T
= 25°C
F
t
, R = 4 KΩ
L
8ꢀ
t
, R = 4 KΩ
PLH
PLH
L
t
, R = 35ꢀ Ω
L
PHL
1 KΩ
4 KΩ
6ꢀ
4ꢀ
75
6ꢀ
t
, R = 35ꢀ Ω
L
PLH
t
, R = 1 KΩ
L
PLH
t
, R = 1 KΩ
L
PLH
t
, R = 35ꢀ Ω
L
PLH
45
3ꢀ
2ꢀ
ꢀ
t
, R = 35ꢀ Ω
PHL
L
1 KΩ
4 KΩ
5
7
9
11
13
15
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ
8ꢀ 1ꢀꢀ
6ꢀ
I
– PULSE INPUT CURRENT – mA
T
– TEMPERATURE – °C
F
A
Figure 9. Typical propagation delay vs. tem-
perature.
Figure 10. Typical propagation delay vs. pulse
input current.
40
V
I
= 5.ꢀ V
t
t
CC
= 7.5 mA
RISE
FALL
R
= 4 kΩ
L
F
30
20
10
0
V
I
= 5.0 V
CC
= 7.5 mA
R
= 4 kΩ
= 1 kΩ
3ꢀꢀ
29ꢀ
6ꢀ
F
L
R
= 350Ω
L
R
L
4ꢀ
R
R
= 35ꢀ Ω
L
2ꢀ
ꢀ
R
= 1 kΩ
L
= 35ꢀ Ω, 1 kΩ, 4 kΩ
2ꢀ 4ꢀ 6ꢀ 8ꢀ 1ꢀꢀ
L
ꢀ
-10
-60
-40 -20
0
20 40
80 100
-6ꢀ -4ꢀ -2ꢀ
60
- TEMPERATURE - oC
T
– TEMPERATURE – °C
A
T
A
Figure 11. Typical pulse width distortion vs.
temperature.
Figure 12. Typical rise and fall time vs. tempera-
ture.
17
PULSE GEN.
= 5ꢀ Ω
Z
f
O
t
= t = 5 ns
r
INPUT V
E
MONITORING NODE
+5 V
V
3.ꢀ V
1.5 V
1
2
3
4
8
7
6
5
CC
INPUT
V
7.5 mA
E
ꢀ.1 μF
BYPASS
R
L
I
F
t
t
EHL
ELH
OUTPUT V
MONITORING
NODE
O
OUTPUT
V
O
1.5 V
*C
L
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
Figure 13. Test circuit for tEHL and tELH.
12ꢀ
V
V
V
= 5.ꢀ V
= 3.ꢀ V
= ꢀ V
CC
EH
EL
I
= 7.5 mA
F
9ꢀ
6ꢀ
t
, R = 4 kΩ
L
ELH
t
, R = 1 kΩ
ELH
L
3ꢀ
ꢀ
t
, R = 35ꢀ Ω
ELH
L
t
, R = 35ꢀ Ω, 1 kΩ, 4 kΩ
EHL
L
-6ꢀ -4ꢀ -2ꢀ
ꢀ
2ꢀ 4ꢀ 6ꢀ 8ꢀ 1ꢀꢀ
T
– TEMPERATURE – °C
A
Figure 14. Typical enable propagation delay vs.
temperature.
I
F
SINGLE CHANNEL
DUAL CHANNEL
B
I
F
V
1
2
3
4
8
7
6
5
+5 V
V
CC
1
2
3
4
8
+5 V
CC
A
R
B
A
L
OUTPUT V
MONITORING
NODE
ꢀ.1 μF
BYPASS
O
R
7
6
5
L
V
FF
OUTPUT V
MONITORING
NODE
O
V
FF
ꢀ.1 μF
BYPASS
GND
GND
V
CM
V
CM
+
–
+
–
PULSE
GENERATOR
= 5ꢀ Ω
PULSE
GENERATOR
= 5ꢀ Ω
Z
Z
O
O
V
(PEAKꢁ
CM
V
CM
ꢀ V
5 V
SWITCH AT A: I = ꢀ mA
F
CM
H
V
O
V
(MIN.ꢁ
O
SWITCH AT B: I = 7.5 mA
F
V
(MAX.ꢁ
O
V
O
ꢀ.5 V
CM
L
Figure 15. Test circuit for common mode transient immunity and typical waveforms.
18
HCNWXXXX
(mWꢁ
HCPL-2611 OPTION ꢀ6ꢀ
8ꢀꢀ
7ꢀꢀ
6ꢀꢀ
5ꢀꢀ
4ꢀꢀ
3ꢀꢀ
2ꢀꢀ
1ꢀꢀ
ꢀ
P
P
I
(mWꢁ
S
S
I
(mAꢁ
(mAꢁ
S
S
8ꢀꢀ
7ꢀꢀ
6ꢀꢀ
5ꢀꢀ
4ꢀꢀ
3ꢀꢀ
2ꢀꢀ
1ꢀꢀ
ꢀ
ꢀ
25
5ꢀ 75 1ꢀꢀ 125 15ꢀ 175
ꢀ
25 5ꢀ 75 1ꢀꢀ 125 15ꢀ 175 2ꢀꢀ
– CASE TEMPERATURE – °C
T
– CASE TEMPERATURE – °C
T
S
S
Figure 16. Thermal derating curve, dependence of safety limiting value with case temperature
per IEC/EN/DIN EN 60747-5-2.
GND BUS (BACKꢁ
V
BUS (FRONTꢁ
NC
CC
ENABLE
OUTPUT
ꢀ.1μF
NC
1ꢀ mm MAX.
(SEE NOTE 5ꢁ
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 17. Recommended printed circuit board layout.
19
SINGLE CHANNEL DEVICE
5 V
5 V
8
6
V
CC1
V
CC2
39ꢀ Ω
47ꢀ Ω
I
F
+
2
3
D1*
V
ꢀ.1 μF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
V
E
7
1
2
*DIODE D1 (1N916 OR EQUIVALENTꢁ IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
5 V
5 V
8
7
V
CC1
V
CC2
39ꢀ Ω
47ꢀ Ω
I
F
+
1
2
D1*
V
ꢀ.1 μF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
1
2
Figure 18. Recommended TTL/LSTTL to TTL/LSTTL interface circuit.
20
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
puts of a group of optocouplers are switched either ON
or OFF at the same time, tPSK is the difference between
the shortest propagation delay, either tPLH or tPHL, and the
Propagation delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(tPHL) is the amount of time required for the input signal
to propagate to the output causing the output to change
from high to low (see Figure8).
longest propagation delay, either tPLH or tPHL
.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 20 is the timing
diagram of a typical parallel data application with both
the clock and the data lines being sent through opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. To obtain the
maximum data transmission rate, both edges of the
clock signal are being used to clock the data; if only one
edge were used, the clock signal would need to be twice
as fast.
Pulse-width distortion (PWD) results when tPLH and tPHL
differ in value. PWD is defined as the difference be-
tween tPLH and tPHL and often determines the maximum
data rate capability of a transmission system. PWD can
be expressed in percent by dividing the PWD (in ns) by
the minimum pulse width (in ns) being transmitted. Typi-
cally, PWD on the order of 20-30% of the minimum pulse
width is tolerable; the exact figure depends on the par-
ticular application (RS232, RS422, T-l, etc.).
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an
optocoupler. Figure 20 shows that there will be uncer-
tainty in both the data and the clock lines. It is important
that these two areas of uncertainty not overlap, other-
wise the clock signal might arrive before all of the data
outputs have settled, or some of the data outputs may
start to change before the clock signal has arrived. From
these considerations, the absolute minimum pulse width
that can be sent through optocouplers in a parallel appli-
cation is twice tPSK. A cautious design should use a slightly
longer pulse width to ensure that any additional uncer-
tainty in the rest of the circuit does not cause a problem.
Propagation delay skew, tPSK, is an important parameter to
consider in parallel data applications where synchroniza-
tion of signals on parallel data lines is a concern. If the
parallel data is being sent through a group of optocou-
plers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at differ-
ent times. If this difference in propagation delays is large
enough, it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
The tPSK specified optocouplers offer the advantages of
guaranteed specifications for propagation delays, pulse-
width distortion and propagation delay skew over the
recommended temperature, input current, and power
supply ranges.
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
either tPLH or tPHL, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and op-
erating temperature). As illustrated in Figure 19, if the in-
DATA
INPUTS
CLOCK
I
F
5ꢀ%
1.5 V
V
O
DATA
I
5ꢀ%
F
OUTPUTS
t
PSK
V
1.5 V
CLOCK
O
t
PSK
t
PSK
Figure 19. Illustration of propagation delay skew - tPSK.
Figure 20. Parallel data transmission example.
21
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies Limited. All rights reserved. Obsoletes AV02-0170EN
AV02-0940EN - March 29, 2010
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