HCPL-J454-500 [AVAGO]
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.300 INCH, SURFACE MOUNT, DIP-8;
| 型号： | HCPL-J454-500 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.300 INCH, SURFACE MOUNT, DIP-8 输出元件 |
| 文件： | 总19页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-4504/J454/0454, HCNW4504
High CMR, High Speed Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
•ꢀShortꢀpropagationꢀdelaysꢀforꢀTTLꢀandꢀIPMꢀapplications
Theꢀ HCPL-4504ꢀ andꢀ HCPL-0454ꢀ containꢀ aꢀ GaAsPꢀ LEDꢀ
whileꢀtheꢀHCPL-J454ꢀandꢀHCNW4504ꢀcontainꢀanꢀAlGaAsꢀ •ꢀ15ꢀkV/µsꢀminimumꢀCommonꢀModeꢀTransientꢀimmu-
LED.ꢀTheꢀLEDꢀisꢀopticallyꢀcoupledꢀtoꢀanꢀintegratedꢀhighꢀ
gainꢀphotoꢀdetector.
nityꢀatꢀVCMꢀ=ꢀ1500ꢀVꢀforꢀTTL/loadꢀdrive
•ꢀHighꢀCTRꢀatꢀTAꢀ=ꢀ25°Cꢀ
ꢀꢀꢀꢀ>25%ꢀforꢀHCPL-4504/0454ꢀ
ꢀꢀꢀꢀ>23%ꢀforꢀHCNW4504ꢀꢀ
ꢀꢀꢀꢀ>19%ꢀforꢀHCPL-J454
TheꢀHCPL-4504ꢀseriesꢀhasꢀshortꢀpropagationꢀdelaysꢀandꢀ
highꢀCTR.ꢀTheꢀHCPL-4504ꢀseriesꢀalsoꢀhasꢀaꢀguaranteedꢀ
propagationꢀ delayꢀ differenceꢀ (tPLH-tPHL).ꢀTheseꢀ featuresꢀ
makeꢀtheꢀHCPL-4504ꢀseriesꢀanꢀexcellentꢀsolutionꢀtoꢀIPMꢀ
•ꢀElectricalꢀspecificationsꢀforꢀcommonꢀIPMꢀapplications
inverterꢀdeadꢀtimeꢀandꢀotherꢀswitchingꢀproblems.ꢀTheꢀ •ꢀTTLꢀcompatible
CTR,ꢀpropagationꢀdelay,ꢀandꢀCMRꢀareꢀspecifiedꢀbothꢀforꢀ
TTLꢀandꢀIPMꢀconditionsꢀwhichꢀareꢀprovidedꢀforꢀeaseꢀofꢀ
application.ꢀTheseꢀsingleꢀchannel,ꢀdiode-transistorꢀopto-
couplersꢀareꢀavailableꢀinꢀ8-PinꢀDIP,ꢀSO-8,ꢀandꢀWidebodyꢀ
packageꢀconfigurations.ꢀAnꢀinsulatingꢀlayerꢀbetweenꢀaꢀ
LEDꢀandꢀanꢀintegratedꢀphotodetectorꢀprovideꢀelectricalꢀ
insulationꢀbetweenꢀinputꢀandꢀoutput.ꢀSeparateꢀconnec-
tionsꢀforꢀtheꢀphotodiodeꢀbiasꢀandꢀoutput-transistorꢀcol-
lectorꢀincreaseꢀtheꢀspeedꢀupꢀtoꢀaꢀhundredꢀtimesꢀthatꢀofꢀ
aꢀconventionalꢀphototransistorꢀcouplerꢀbyꢀreducingꢀtheꢀ
baseꢀcollectorꢀcapacitance.
•ꢀGuaranteedꢀperformanceꢀfromꢀ0°Cꢀtoꢀ70°Cꢀ
•ꢀOpenꢀcollectorꢀoutput
•ꢀSafetyꢀapproval:ꢀ
ULꢀrecognized
ꢀ –ꢀ3750ꢀVꢀrms/1min.ꢀforꢀHCPL-4504/0454/J454ꢀ
–ꢀ5000ꢀVꢀrms/1min.ꢀforꢀHCPL-4504ꢀOptionꢀ020ꢀandꢀ
HCNW4504
ꢀ ꢀCSAꢀapprovedꢀꢀ
ꢀ
IEC/EN/DINꢀENꢀ60747-5-2ꢀapproved
ꢀ –ꢀVIORMꢀ=ꢀ560ꢀVpeakꢀforꢀHCPL-0454ꢀOptionꢀ060
ꢀ –ꢀVIORMꢀ=ꢀ630ꢀVpeakꢀforꢀHCPL-4504ꢀOptionꢀ060
ꢀ –ꢀVIORMꢀ=ꢀ891ꢀVpeakꢀforꢀHCPL-J454
Functional Diagram
ꢀ –ꢀVIORMꢀ=ꢀ1414ꢀVpeakꢀforꢀHCNW4504
8
7
6
5
NC
ANODE
CATHODE
NC
1
2
3
4
V
CC
Applications
TRUTH TABLE
NC
•ꢀꢀInverterꢀcircuitsꢀandꢀIntelligentꢀPowerꢀModuleꢀ(IPM)ꢀ
interfacing:ꢀHighꢀCommonꢀModeꢀTransientꢀimmunityꢀ
(>ꢀ10ꢀkV/µsꢀforꢀanꢀIPMꢀload/drive)ꢀandꢀ(tPLHꢀ-ꢀtPHL)ꢀ
Specifiedꢀ(seeꢀPowerꢀInverterꢀDeadꢀTimeꢀsection)
LED
V
O
ON
OFF
LOW
HIGH
V
O
GND
•ꢀLineꢀreceivers:ꢀShortꢀpropagationꢀdelaysꢀandꢀlowꢀin-
put-outputꢀcapacitance
•ꢀHighꢀspeedꢀlogicꢀgroundꢀisolation:ꢀTTL/TTL,ꢀTTL/
CMOS,ꢀTTL/LSTTL
Aꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀbetweenꢀpinsꢀ5ꢀandꢀ8ꢀisꢀrecommended.
Schematic
•ꢀReplacesꢀpulseꢀtransformers:ꢀSaveꢀboardꢀspaceꢀandꢀ
weight
I
CC
8
V
CC
•ꢀAnalogꢀsignalꢀgroundꢀisolation:ꢀIntegratedꢀphotode-
tectorꢀprovidesꢀimprovedꢀlinearityꢀoverꢀphototransis-
tors
I
F
+
2
ANODE
V
F
I
O
6
5
–
3
V
O
CATHODE
SHIELD
GND
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-0454,ꢀHCPL-4504ꢀandꢀHCPL-J454ꢀareꢀULꢀRecognizedꢀwithꢀ3750ꢀVrmsꢀforꢀ1ꢀminuteꢀperꢀUL1577.
HCNW4504ꢀisꢀULꢀRecognizedꢀwithꢀ5000ꢀVrmsꢀforꢀ1ꢀminuteꢀperꢀUL1577.ꢀHCPL-0454,ꢀHCPL-4504,ꢀHCPL-J454ꢀandꢀ
HCNW4504ꢀareꢀapprovedꢀunderꢀCSAꢀComponentꢀAcceptanceꢀNoticeꢀ#5,ꢀFileꢀCAꢀ88324.
UL 1577
Option
non RoHS
Compliant Compliant
5000 Vrms/
1 Minute
rating
Part
Number
RoHS
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2 Quantity
Package
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-300E
-400E
-500E
-600E
-000E
-500E
-060E
-560E
-000E
-300E
-500E
noꢀoption
#300
50ꢀperꢀtube
X
X
X
X
50ꢀperꢀtube
1000ꢀperꢀreel
50ꢀperꢀtube
50ꢀperꢀtube
1000ꢀperꢀreel
50ꢀperꢀtube
50ꢀperꢀtube
1000ꢀperꢀreel
50ꢀperꢀtube
50ꢀperꢀtube
50ꢀperꢀtube
1000ꢀperꢀreel
750ꢀperꢀreel
100ꢀperꢀtube
1500ꢀperꢀreel
100ꢀperꢀtube
1500ꢀperꢀreel
42ꢀperꢀtube
42ꢀperꢀtube
750ꢀperꢀreel
#500
X
X
X
#020
X
X
X
300ꢀmilꢀ
DIP-8
HCPL-4504
#320
X
X
X
X
#520
#060
X
X
X
X
X
X
X
X
#360
X
X
X
X
#560
noꢀoption
#300
X
X
X
X
X
X
X
X
X
X
X
X
300ꢀmilꢀ
DIP-8
HCPL-J454
NA
#500
X
X
NA
noꢀoption
#500
X
X
HCPL-0454
HCNW4504
SO-8
#060
X
X
X
X
X
#560
noꢀoption
#300
X
X
X
400ꢀmil
Widebody
DIP-8
X
X
X
X
#500
X
Toꢀorder,ꢀchooseꢀaꢀpartꢀnumberꢀfromꢀtheꢀpartꢀnumberꢀcolumnꢀandꢀcombineꢀwithꢀtheꢀdesiredꢀoptionꢀfromꢀtheꢀoptionꢀ
columnꢀtoꢀformꢀanꢀorderꢀentry.ꢀ
Exampleꢀ1:
HCPL-4504-560Eꢀtoꢀorderꢀproductꢀofꢀ300ꢀmilꢀDIPꢀGullꢀWingꢀSurfaceꢀMountꢀpackageꢀinꢀTapeꢀandꢀReelꢀpackagingꢀ
withꢀIEC/EN/DINꢀENꢀ60747-5-2ꢀSafetyꢀApprovalꢀandꢀRoHSꢀcompliant.
Exampleꢀ2:
HCPL-4504ꢀtoꢀorderꢀproductꢀofꢀ300ꢀmilꢀDIPꢀpackageꢀinꢀTubeꢀpackagingꢀandꢀnonꢀRoHSꢀcompliant.
Optionꢀdatasheetsꢀareꢀavailable.ꢀContactꢀyourꢀAvagoꢀsalesꢀrepresentativeꢀorꢀauthorizedꢀdistributorꢀforꢀinformation.
Remarks:ꢀTheꢀnotationꢀ‘#XXX’ꢀisꢀusedꢀforꢀexistingꢀproducts,ꢀwhileꢀ(new)ꢀproductsꢀlaunchedꢀsinceꢀJulyꢀ15,ꢀ2001ꢀandꢀ
RoHSꢀcompliantꢀwillꢀuseꢀ‘–XXXE.’
2
Package Outline Drawings
HCPL-4504 Outline Drawing
7.62 0.25
(0.300 0.010ꢀ
9.65 0.25
(0.380 0.010ꢀ
8
1
7
6
5
6.35 0.25
(0.250 0.010ꢀ
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070ꢀ MAX.
1.19 (0.047ꢀ MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003ꢀ
- 0.002ꢀ
3.56 0.13
(0.140 0.005ꢀ
(0.010
4.70 (0.185ꢀ MAX.
0.51 (0.020ꢀ MIN.
2.92 (0.115ꢀ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢀ.
1.080 0.320
(0.043 0.013ꢀ
0.65 (0.025ꢀ MAX.
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010ꢀ
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
HCPL-4504 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
1.016 (0.040ꢀ
9.65 0.25
(0.380 0.010ꢀ
6
5
8
1
7
6.350 0.25
(0.250 0.010ꢀ
10.9 (0.430ꢀ
2
3
4
2.0 (0.080ꢀ
1.27 (0.050ꢀ
9.65 0.25
1.780
(0.070ꢀ
MAX.
(0.380 0.010ꢀ
1.19
(0.047ꢀ
MAX.
7.62 0.25
(0.300 0.010ꢀ
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005ꢀ
+ 0.003ꢀ
- 0.002ꢀ
(0.010
1.080 0.320
(0.043 0.013ꢀ
0.635 0.25
(0.025 0.010ꢀ
12° NOM.
0.635 0.130
(0.025 0.005ꢀ
2.54
(0.100ꢀ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
3
Package Outline Drawings
HCPL-J454 Outline Drawing
7.62 0.25
(0.300 0.010ꢀ
9.80 0.25
(0.386 0.010ꢀ
8
7
6
5
6.35 0.25
(0.250 0.010ꢀ
TYPE NUMBER
DATE CODE
A XXXX
YYWW
U R
UL
1
2
3
4
RECOGNITION
1.78 (0.070ꢀ MAX.
1.19 (0.047ꢀ MAX.
+ 0.076
- 0.051
0.254
5 TYP.
+ 0.003ꢀ
- 0.002ꢀ
3.56 0.13
(0.140 0.005ꢀ
(0.010
4.70 (0.185ꢀ MAX.
0.51 (0.020ꢀ MIN.
2.92 (0.115ꢀ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢀ.
1.080 0.320
(0.043 0.013ꢀ
0.65 (0.025ꢀ MAX.
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010ꢀ
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 milsꢀ MAX.
HCPL-J454 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
1.016 (0.040ꢀ
9.80 0.25
(0.386 0.010ꢀ
6
5
8
1
7
6.350 0.25
(0.250 0.010ꢀ
10.9 (0.430ꢀ
2
3
4
2.0 (0.080ꢀ
1.27 (0.050ꢀ
9.65 0.25
1.780
(0.070ꢀ
MAX.
(0.380 0.010ꢀ
1.19
(0.047ꢀ
MAX.
7.62 0.25
(0.300 0.010ꢀ
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005ꢀ
+ 0.003ꢀ
- 0.002ꢀ
(0.010
1.080 0.320
(0.043 0.013ꢀ
0.635 0.25
(0.025 0.010ꢀ
12° NOM.
0.635 0.130
(0.025 0.005ꢀ
2.54
(0.100ꢀ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 milsꢀ MAX.
4
HCPL-J454-400E/600E Widelead Gullwing Surface Mount Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ±0.25
0.386 ±0.010
1.016
0.040
TYPE NUMBER
12.9
0.508
A XXXX
6.35 ±0.25
0.250 ±0.010
YYWW R U
DATE CODE
1.27
0.050
UL
RECOGNITION
2.0
0.08
[0.65] 0.025 MAX
[11.75 0.25]
0.460 0.010
[1.19]
0.047
MAX.
7.62 ±0.51
0.300±0.020
[0.20] 0.008
[0.33] 0.013
3.56 ±0.13
0.140 ±0.005
[0.152] 0.006
[0.406] 0.016
[1.080] 0.320
0.043 0.013
0.625 ±0.254
0.025 ±0.010
2.54
0.100
BSC
30° NOM.
LEAD COPLANARITY
MAXIMUM: [0.102] 0.004
DIMENSIONS IN [MILLIMETERS] INCHES
OPTION NUMBERS 400 AND 600 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
HCPL-0454 Outline Drawing (8-Pin Small Outline Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
7.49 (0.295ꢀ
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
3
1.9 (0.075ꢀ
PIN ONE
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025ꢀ
0.432
(0.017)
*
7
5.080 ± 0.127
(0.200 ± 0.005)
45 X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
5
HCNW4504 Outline Drawing (8-Pin Widebody Package)
11.00
(0.433ꢀ
11.15 0.15
(0.442 0.006ꢀ
MAX.
9.00 0.15
(0.354 0.006ꢀ
7
6
5
8
TYPE NUMBER
DATE CODE
A
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400ꢀ
TYP.
1.55
(0.061ꢀ
MAX.
7° TYP.
+ 0.076
- 0.0051
0.254
+ 0.003ꢀ
- 0.002ꢀ
(0.010
5.10
(0.201ꢀ
MAX.
3.10 (0.122ꢀ
3.90 (0.154ꢀ
0.51 (0.021ꢀ MIN.
2.54 (0.100ꢀ
TYP.
1.78 0.15
(0.070 0.006ꢀ
0.40 (0.016ꢀ
0.56 (0.022ꢀ
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
HCNW4504 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 0.15
(0.442 0.006ꢀ
LAND PATTERN RECOMMENDATION
7
6
5
8
9.00 0.15
(0.354 0.006ꢀ
13.56
(0.534ꢀ
1
3
2
4
2.29
(0.09ꢀ
1.3
(0.051ꢀ
12.30 0.30
1.55
(0.061ꢀ
MAX.
(0.484 0.012ꢀ
11.00
MAX.
(0.433ꢀ
4.00
MAX.
(0.158ꢀ
1.78 0.15
(0.070 0.006ꢀ
1.00 0.15
(0.039 0.006ꢀ
0.75 0.25
(0.030 0.010ꢀ
+ 0.076
- 0.0051
2.54
(0.100ꢀ
BSC
0.254
+ 0.003ꢀ
- 0.002ꢀ
(0.010
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
6
Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C 0.5 °C/SEC.
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
PEAK
TEMP.
230 °C
200
100
0
2.5 C 0.5 °C/SEC.
SOLDERING
30
TIME
160 °C
150 °C
140 °C
SEC.
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
Recommended Pb-Free IR Profile
TIMEWITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
tp
15 SEC.
* 260 +0/-5 °C
RAMP-UP
Tp
217 °C
TL
RAMP-DOWN
6 °C/SEC. MAX.
3 °C/SEC. MAX.
150 - 200 °C
Tsmax
Tsmin
ts
tL
PREHEAT
60 to 150 SEC.
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THETIME FROM 25 °C to PEAKTEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAKTEMPERATURE FORWIDEBODY 400mils PACKAGE IS 245 °C
7
Regulatory Information
Theꢀdevicesꢀcontainedꢀinꢀthisꢀdataꢀsheetꢀhaveꢀbeenꢀapprovedꢀbyꢀtheꢀfollowingꢀagencies:
Agency/Standard
HCPL-4504
HCPL-J454
HCPL-0454
HCNW4504
UL1577
3750ꢀVrmsꢀ/ꢀꢀ
1ꢀminute,ꢀ
Optionꢀ020ꢀ5000ꢀ
Vrmsꢀ/ꢀ1ꢀminute
3750ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
3750ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
5000ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
Underwriters Laboratories (UL)
RecognizedꢀunderꢀUL1577,ꢀꢀ
ComponentꢀRecognitionꢀProgram,ꢀꢀ
CategoryꢀFPQU2,ꢀFileꢀE55361
Component 3750ꢀVrmsꢀ/ꢀꢀ
3750ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
3750ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
5000ꢀVrmsꢀ/ꢀꢀ
1ꢀminute
Canadian Standards Association (CSA)
FileꢀCA88324
Acceptance
Noticeꢀ#5
1ꢀminute,ꢀ
Optionꢀ020ꢀ5000ꢀ
Vrmsꢀ/ꢀ1ꢀminute
Optionꢀ060ꢀꢀꢀ
VIORMꢀ=ꢀ630ꢀVpeak
VIORMꢀ=ꢀ891ꢀ
Vpeak
Optionꢀ060ꢀꢀ
VIORMꢀ=ꢀ560ꢀ
Vpeak
VIORMꢀ=ꢀ1414ꢀ
Vpeak
IEC/EN/DIN EN 60747-5-2
Approvedꢀunder:
IECꢀ60747-5-2:1997ꢀ+ꢀA1:2002
ENꢀ60747-5-2:2001ꢀ+ꢀA1:2002
DINꢀENꢀ60747-5-2ꢀ(VDEꢀ0884ꢀTeilꢀ2):2003-01
Insulation and Safety Related Specifications
Value
HCPL-
J454
HCPL-J454
All other
HCPL-
HCPL-
0454
HCNW
Parameter
Symbol
4504 -400E/-600E options
4504 Units Conditions
MinimumꢀExternalꢀ
AirꢀGapꢀ
(ExternalꢀClearance)
L(101)
7.1
8.0
7.4
8.0
4.9
9.6
mm Measuredꢀfromꢀinputꢀter-
minalsꢀtoꢀoutputꢀterminals,ꢀ
shortestꢀdistanceꢀthroughꢀair.
MinimumꢀExternalꢀ
Trackingꢀ
(ExternalꢀCreepage)
L(102)
7.4
8.0
4.8
10.0
mm Measuredꢀfromꢀinputꢀter-
minalsꢀtoꢀoutputꢀterminals,ꢀ
shortestꢀdistanceꢀpathꢀalongꢀ
body.
MinimumꢀInternalꢀ
PlasticꢀGapꢀ
(InternalꢀClearance)
0.08
0.5
0.5
0.08
1.0
mm Throughꢀinsulationꢀdistance,ꢀ
conductorꢀtoꢀconductor,ꢀ
usuallyꢀtheꢀdirectꢀdistanceꢀ
betweenꢀtheꢀphotoemitterꢀ
andꢀphotodetectorꢀinsideꢀtheꢀ
optocouplerꢀcavity.
MinimumꢀInternalꢀ
Trackingꢀ(Internalꢀ
Creepage)
NA
≥175
IIIa
NA
≥175
IIIa
NA
≥175
IIIa
NA
≥175
IIIa
4.0
mm Measuredꢀfromꢀinputꢀter-
minalsꢀtoꢀoutputꢀꢀterminals,ꢀ
alongꢀinternalꢀcavity.
TrackingꢀResistanceꢀ CTI
(Comparativeꢀ
TrackingꢀIndex)
≥200 Volts DINꢀIECꢀ112/VDEꢀ0303ꢀPartꢀ1
IsolationꢀGroup
IIIa
MaterialꢀGroupꢀ(DINꢀVDEꢀ
0110,ꢀ1/89,ꢀTableꢀ1)
AllꢀAvagoꢀdataꢀsheetsꢀreportꢀtheꢀcreepageꢀandꢀclearanceꢀ creepage,ꢀtheꢀshortestꢀdistanceꢀpathꢀalongꢀtheꢀsurfaceꢀ
inherentꢀtoꢀtheꢀoptocouplerꢀcomponentꢀitself.ꢀTheseꢀdi-
mensionsꢀareꢀneededꢀasꢀaꢀstartingꢀpointꢀforꢀtheꢀequip-
ofꢀaꢀprintedꢀcircuitꢀboardꢀbetweenꢀtheꢀsolderꢀfilletsꢀofꢀ
theꢀinputꢀandꢀoutputꢀleadsꢀmustꢀbeꢀconsidered.ꢀThereꢀ
mentꢀdesignerꢀwhenꢀdeterminingꢀtheꢀcircuitꢀinsulationꢀ areꢀrecommendedꢀtechniquesꢀsuchꢀasꢀgroovesꢀandꢀribsꢀ
requirements.
whichꢀmayꢀbeꢀusedꢀonꢀaꢀprintedꢀcircuitꢀboardꢀtoꢀachieveꢀ
desiredꢀ creepageꢀ andꢀ clearances.ꢀ Creepageꢀ andꢀ clear-
anceꢀ distancesꢀ willꢀ alsoꢀ changeꢀ dependingꢀ onꢀ factorsꢀ
suchꢀasꢀpollutionꢀdegreeꢀandꢀinsulationꢀlevel.
However,ꢀonceꢀmountedꢀonꢀaꢀprintedꢀcircuitꢀboard,ꢀmini-
mumꢀ creepageꢀ andꢀ clearanceꢀ requirementsꢀ mustꢀ beꢀ
metꢀasꢀspecifiedꢀforꢀindividualꢀequipmentꢀstandards.ꢀForꢀ
8
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
HCPL-0454
OPTION 060
HCPL-4504
OPTION 060
Description
Symbol
HCPL-J454
HCNW4504
Unit
Installationꢀclassificationꢀper
DINꢀVDEꢀ0110/1.89,ꢀTableꢀ1
ꢀ forꢀratedꢀmainsꢀvoltageꢀ≤150ꢀVꢀrms
ꢀ forꢀratedꢀmainsꢀvoltageꢀ≤300ꢀVꢀrms
ꢀ forꢀratedꢀmainsꢀvoltageꢀ≤450ꢀVꢀrms
ꢀ forꢀratedꢀmainsꢀvoltageꢀ≤600ꢀVꢀrms
ꢀ forꢀratedꢀmainsꢀvoltageꢀ≤1000ꢀVꢀrms
I-IV
I-III
I-IV
I-IV
I-III
I-IV
I-IV
I-III
I-III
I-IV
I-IV
I-IV
I-IV
I-III
ClimaticꢀClassification
55/100/21
55/100/21
55/100/21
55/85/21
2
PollutionꢀDegreeꢀ(DINꢀVDEꢀ0110/1.89)
MaximumꢀWorkingꢀInsulationꢀVoltage
2
2
2
V
IORM
560
630
891
1414
Vꢀpeak
Vꢀpeak
InputꢀtoꢀOutputꢀTestꢀVoltage,ꢀMethodꢀb*
ꢀ VIORMꢀxꢀ1.875ꢀ=ꢀVPR,ꢀ100%ꢀProduction
ꢀ Testꢀwithꢀtmꢀ=ꢀ1ꢀsec,
VPR
1050
840
1181
945
1670
1336
6000
2652
2121
8000
ꢀ PartialꢀDischargeꢀ<ꢀ5ꢀpC
InputꢀtoꢀOutputꢀTestꢀVoltage,ꢀMethodꢀa*
ꢀ VIORMꢀxꢀ1.5ꢀ=ꢀVPR,ꢀTypeꢀandꢀSample
ꢀ Test,ꢀtmꢀ=ꢀ60ꢀsec,
VPR
Vꢀpeak
ꢀ PartialꢀDischargeꢀ<ꢀ5ꢀpC
HighestꢀAllowableꢀOvervoltage*
(TransientꢀOvervoltage,ꢀtiniꢀ=ꢀ10ꢀsec)
SafetyꢀLimitingꢀValuesꢀ-ꢀMaximum
ValuesꢀAllowedꢀinꢀtheꢀEventꢀofꢀaꢀFailure,
alsoꢀseeꢀꢀThermalꢀDeratingꢀcurve
VIOTM
4000
6000
Vꢀpeak
ꢀ CaseꢀTemperature
ꢀ InputꢀCurrent
TS
150
150
600
≥109
175
230
600
≥109
175
400
600
≥109
150
400
700
≥109
°C
IS,INPUT
PS,OUTPUT
RS
mA
mW
Ω
ꢀ OutputꢀPower
InsulationꢀResistanceꢀatꢀTS,
ꢀ V ꢀ=ꢀ500ꢀV
IO
*ReferꢀtoꢀtheꢀoptocouplerꢀsectionꢀofꢀtheꢀDesigner'sꢀCatalog,ꢀunderꢀregulatoryꢀinformationꢀ(IEC/EN/DINꢀENꢀ60747-5-2)ꢀforꢀaꢀdetailedꢀdescriptionꢀofꢀ
MethodꢀaꢀandꢀMethodꢀbꢀpartialꢀdischargeꢀtestꢀprofiles.
NOTE:ꢀTheseꢀoptocouplersꢀareꢀsuitableꢀforꢀ"safeꢀelectricalꢀisolation"ꢀonlyꢀwithinꢀtheꢀsafetyꢀlimitꢀdata.ꢀMaintenanceꢀofꢀtheꢀsafetyꢀdataꢀshallꢀbeꢀensuredꢀ
byꢀmeansꢀofꢀprotectiveꢀcircuits.
NOTE:ꢀInsulationꢀCharacteristicsꢀareꢀperꢀIEC/EN/DINꢀENꢀ60747-5-2.
NOTE:ꢀSurfaceꢀmountꢀclassificationꢀisꢀClassꢀAꢀinꢀaccordanceꢀwithꢀCECCꢀ00802.
9
Absolute Maximum Ratings
Parameter
Symbol
TS
Device
Min.
-55
-55
Max.
125
100
Units
°C
Note
StorageꢀTemperature
OperatingꢀTemperature
TA
HCPL-4504
HCPL-0454
HCPL-J454
°C
HCNW4504
-55
85
25
50
AverageꢀForwardꢀInputꢀCurrent
PeakꢀForwardꢀInputꢀCurrent
IF(AVG)
mA
mA
1
2
IF(PEAK)
HCPL-4504
HCPL-0454
ꢀ
ꢀ
(50%ꢀdutyꢀcycle,ꢀ1ꢀmsꢀpulseꢀwidth)
HCPL-J454
HCNW4504
40
1
PeakꢀTransientꢀInputꢀCurrent
ꢀ
ꢀ
IF(TRANS)
HCPL-4504
HCPL-0454
A
(≤1ꢀµsꢀpulseꢀwidth,ꢀ300ꢀpps)
HCPL-J454
HCNW4504
0.1
5
ReverseꢀLEDꢀInputꢀVoltageꢀ(Pinꢀ3-2)
ꢀ
ꢀ
VR
HCPL-4504
HCPL-0454
V
HCPL-J454
HCNW4504
3
InputꢀPowerꢀDissipation
ꢀ
ꢀ
PIN
HCPL-4504
HCPL-0454
45
40
mW
3
HCPL-J454
HCNW4504
AverageꢀOutputꢀCurrentꢀ(Pinꢀ6)
PeakꢀOutputꢀCurrent
IO(AVG)
IO(PEAK)
VCC
8
mA
mA
V
16
30
20
100
260
SupplyꢀVoltageꢀ(Pinꢀ8-5)
OutputꢀVoltageꢀ(Pinꢀ6-5)
OutputꢀPowerꢀDissipation
-0.5
-0.5
VO
V
PO
mW
°C
4
LeadꢀSolderꢀTemperature
(Through-HoleꢀPartsꢀOnly)
TLS
HCPL-4504
HCPL-J454
ꢀ
ꢀ
1.6ꢀmmꢀbelowꢀseatingꢀplane,ꢀ10ꢀseconds
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀUpꢀtoꢀseatingꢀplane,ꢀ10ꢀseconds
HCNW4504
260
ReflowꢀTemperatureꢀProfile
TRP
HCPL-0454,
SeeꢀPackage Outline Drawingsꢀ
Optionꢀ300ꢀ,
Optionꢀ500,ꢀ
Optionꢀ400E
&ꢀOptionꢀ600E.
section
10
Electrical Specifications (DC)
Overꢀrecommendedꢀtemperatureꢀ(TAꢀ=ꢀ0°Cꢀtoꢀ70°C)ꢀunlessꢀotherwiseꢀspecified.ꢀSeeꢀnoteꢀ12.
Parameter
Symbol Device
Min. Typ.*
Max. Units
Test Conditions
Fig.
Note
Current
Transfer
Ratio
CTR
CTR
VOL
HCPL-4504
HCPL-0454
25
21
19
13
23
19
26
22
21
16
25
21
32
34
37
39
29
31
35
37
43
45
33
35
0.2
60
60
%
%
V
TAꢀ=ꢀ25°C
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
IFꢀ=ꢀ16ꢀmA,
VCCꢀ=ꢀ4.5ꢀV
1,ꢀ2,
4
5
HCPL-J454
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
VOꢀ=ꢀ0.4ꢀV
VOꢀ=ꢀ0.5ꢀV
IOꢀ=ꢀ4.0ꢀmA
IOꢀ=ꢀ3.3ꢀmA
IOꢀ=ꢀ3.6ꢀmA
IOꢀ=ꢀ3.0ꢀmA
IOꢀ=ꢀ3.6ꢀmA
IOꢀ=ꢀ3.0ꢀmA
VOꢀ=ꢀVCCꢀ=ꢀ5.5ꢀV
VOꢀ=ꢀVCCꢀ=ꢀ15ꢀV
HCNW4504
60
63
65
Current
Transfer
Ratio
HCPL-4504
HCPL-0454
IFꢀ=ꢀ12ꢀmA,
VCCꢀ=ꢀ4.5ꢀV
1,ꢀ2,
4
5
HCPL-J454
65
HCNW4504
65
68
LogicꢀLow
Output
Voltage
HCPL-4504
HCPL-0454
0.4
0.5
0.4
IFꢀ=ꢀ16ꢀmA,
VCCꢀ=ꢀ4.5ꢀV
HCPL-J454
0.2
0.5
0.2
0.5
HCNW4504
0.4
LogicꢀHigh
Output
Current
IOH
0.003 0.5
µA
µA
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
IFꢀ=ꢀ0ꢀmA
5
0.01
1
50
200
LogicꢀLow
Supply
Current
ICCL
HCPL-4504
HCPL-0454
HCNW4504
50
IFꢀ=ꢀ16ꢀmA,ꢀVOꢀ=ꢀOpen,ꢀVCCꢀ=ꢀ15ꢀV
12
HCPL-J454
70
LogicꢀHigh
SupplyꢀCurrent
ICCH
0.02
1.5
1
µA
V
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
IRꢀ=ꢀ10ꢀµA
IRꢀ=ꢀ100ꢀµA
IFꢀ=ꢀ0ꢀmA,ꢀVOꢀ=ꢀOpen,
12
3
2
VCCꢀ=ꢀ15ꢀV
IFꢀ=ꢀ16ꢀmA
InputꢀForward
Voltage
VF
HCPL-4504
HCPL-0454
1.7
1.8
1.85
1.95
HCPL-J454
HCNW4504
1.45 1.59
IFꢀ=ꢀ16ꢀmA
1.35
5
InputꢀReverse
Breakdown
Voltage
BVR
HCPL-4504
HCPL-0454
V
HCPL-J454
HCNW4504
3
Temperature
Coefficient
ofꢀForward
Voltage
∆VF
∆TA
HCPL-4504
HCPL-0454
-1.6
-1.4
60
mV/°C IFꢀ=ꢀ16ꢀmA
HCPL-J454
HCNW4504
Input
Capacitance
CIN
HCPL-4504
HCPL-0454
pF
fꢀ=ꢀ1ꢀMHz,ꢀVFꢀ=ꢀ0ꢀV
HCPL-J454
HCNW4504
70
*AllꢀtypicalsꢀatꢀTAꢀ=ꢀ25°C.
11
AC Switching Specifications
Overꢀrecommendedꢀtemperatureꢀ(TAꢀ=ꢀ0°Cꢀtoꢀ70°C)ꢀunlessꢀotherwiseꢀspecified.
Parameter
Symbol Device Min.
Typ.
0.2
0.2
Max. Units
Test Conditions
Fig.
Note
PropagationꢀDelayꢀ tPHL
TimeꢀtoꢀLogicꢀLowꢀ
atꢀOutputꢀ
0.3
0.5
µs
µs
µs
µs
µs
TAꢀ=ꢀ25°C
Pulse:ꢀꢀfꢀ=ꢀ20ꢀkHz,
DutyꢀCycleꢀ=ꢀ10%,
IFꢀ=ꢀ16ꢀmA,ꢀVCCꢀ=ꢀ5.0ꢀV,
RLꢀ=ꢀ1.9ꢀkΩ,ꢀCLꢀ=ꢀ15ꢀpF,
VTHHLꢀ=ꢀ1.5ꢀV
6,
8,ꢀ9
9
tPHL
0.2
0.5
0.7
1.0
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
TAꢀ=ꢀ25°C
Pulse:ꢀꢀfꢀ=ꢀ10ꢀꢀkHz,
DutyꢀCycleꢀ=ꢀ50%,
IFꢀ=ꢀ12ꢀmA,ꢀVCCꢀ=ꢀ15.0ꢀV,
RLꢀ=ꢀ20ꢀkΩ,ꢀCLꢀ=ꢀ100ꢀpF,
VTHHLꢀ=ꢀ1.5ꢀV
6,
10-14
10
9
HCPL- 0.05
J454
Others 0.1
PropagationꢀDelayꢀ tPLH
TimeꢀtoꢀLogicꢀHighꢀ
atꢀOutput
0.3
0.3
0.5
0.7
Pulse:ꢀꢀfꢀ=ꢀ20ꢀꢀkHz,
DutyꢀCycleꢀ=ꢀ10%,
IFꢀ=ꢀ16ꢀmA,ꢀVCCꢀ=ꢀ5.0ꢀV,
RLꢀ=ꢀ1.9ꢀkΩ,ꢀCLꢀ=ꢀ15ꢀpF,
VTHLHꢀ=ꢀ1.5ꢀV
6,
8,ꢀ9
tPLH
0.3
0.2
0.8
0.8
1.1
1.4
Pulse:ꢀꢀfꢀ=ꢀ10ꢀꢀkHz,
DutyꢀCycleꢀ=ꢀ50%,
IFꢀ=ꢀ12ꢀmA,ꢀVCCꢀ=ꢀ15.0ꢀV,
RLꢀ=ꢀ20ꢀkΩ,ꢀCLꢀ=ꢀ100ꢀpF,
VTHLHꢀ=ꢀ2.0ꢀV
6,
10-14
10
17
PropagationꢀDelayꢀ tPLH
DifferenceꢀBe-
tweenꢀAnyꢀ2ꢀParts
-
-0.4
-0.7
0.3
0.3
0.9
1.3
TAꢀ=ꢀ25°C Pulse:ꢀꢀfꢀ=ꢀ10ꢀꢀkHz,
DutyꢀCycleꢀ=ꢀ50%,
6,
10-14
tPHL
IFꢀ=ꢀ12ꢀmA,ꢀVCCꢀ=ꢀ15.0ꢀV,
RLꢀ=ꢀ20ꢀkΩ,ꢀCLꢀ=ꢀ100ꢀpF,
VTHHLꢀ=ꢀ1.5ꢀV,ꢀVTHLHꢀ=ꢀ2.0ꢀV
CommonꢀModeꢀꢀ
TransientꢀImmu-
nityꢀatꢀLogicꢀHigh
|CMH|
15
15
15
30
30
30
30
kV/µs TAꢀ=ꢀ25°C
VCMꢀ=
VCCꢀ=ꢀ5.0ꢀV,ꢀRLꢀ=ꢀ1.9ꢀkΩ,
CLꢀ=ꢀ15ꢀpF,ꢀIFꢀ=ꢀ0ꢀmA
7
7
7
7
7,ꢀ9
1500ꢀVP-P
|CMH|
ꢀ
kV/µs
VCCꢀ=ꢀ15.0ꢀV,ꢀRLꢀ=ꢀ20ꢀkΩ,
CLꢀ=ꢀ100ꢀpF,ꢀIFꢀ=ꢀ0ꢀmA
8,ꢀ10
7,ꢀ9
LevelꢀOutputꢀꢀ
|CML|
kV/µs TAꢀ=ꢀ25°C
VCMꢀ=
VCCꢀ=ꢀ5.0ꢀV,ꢀRLꢀ=ꢀ1.9ꢀkΩ,
CLꢀ=ꢀ15ꢀpF,ꢀIFꢀ=ꢀ16ꢀmA
CommonꢀModeꢀ
TransientꢀImmu-
nityꢀatꢀꢀLogicꢀLowꢀ
LevelꢀOutput
1500ꢀVP-P
|CML| HCPL- 15
J454
kV/µs
VCCꢀ=ꢀ15.0ꢀV,ꢀRLꢀ=ꢀ20ꢀkΩ,
CLꢀ=ꢀ100ꢀpF,ꢀIFꢀ=ꢀ12ꢀmA
8,ꢀ10
Others 10
|CML|
15
30
kV/µs
VCCꢀ=ꢀ15.0ꢀV,ꢀRLꢀ=ꢀ20ꢀkΩ,
CLꢀ=ꢀ100ꢀpF,ꢀIFꢀ=ꢀ16ꢀmA
7
8,ꢀ10
*AllꢀtypicalsꢀatꢀTAꢀ=ꢀ25°C.
12
Package Characteristics
Overꢀrecommendedꢀtemperatureꢀ(TAꢀ=ꢀ0°Cꢀtoꢀ25°C)ꢀunlessꢀotherwiseꢀspecified.
Parameter
Symbol
Device
Min.
Typ.*
Max.
Units
Test Conditions
Figure
Note
Input-Output
Momentary
Withstand
Voltage†
V
ISO
HCPL-4504
HCPL-0454
3750
Vꢀrms
RHꢀ≤50%,
tꢀ=ꢀ1ꢀmin.,
TAꢀ=ꢀ25°C
6,ꢀ13,
16
HCPL-J454
3750
5000
5000
6,ꢀ14,
16
HCPL-4504
Optionꢀ020
ꢀꢀ6,ꢀ11,
15
HCNW4504
6,ꢀ15,
16
Input-Output
Resistance
RI-O
HCPL-4504
HCPL-0454
HCPL-J454
1012
Ω
VI-Oꢀ=ꢀ500ꢀVdc
6
6
HCNW4504
1012
1011
1013
0.6
TAꢀ=ꢀ25°C
TAꢀ=ꢀ100°C
fꢀ=ꢀ1ꢀMHz
Capacitance
(Input-Output)
CI-O
HCPL-4504
HCPL-0454
pF
HCPL-J454
HCNW4504
0.8
0.5
0.6
AllꢀtypicalsꢀatꢀTAꢀ=ꢀ25°C..
†TheꢀInput-OutputꢀMomentaryꢀWithstandꢀVoltageꢀisꢀaꢀdielectricꢀvoltageꢀratingꢀthatꢀshouldꢀnotꢀbeꢀinterpretedꢀasꢀanꢀinput-outputꢀcontinuousꢀ
voltageꢀrating.ꢀForꢀtheꢀcontinuousꢀvoltageꢀratingꢀreferꢀtoꢀtheꢀIEC/EN/DINꢀENꢀ60747-5-2ꢀInsulationꢀRelatedꢀCharacteristicsꢀTableꢀ(ifꢀapplicable),ꢀyourꢀ
equipmentꢀlevelꢀsafetyꢀspecificationꢀorꢀAvagoꢀApplicationꢀNoteꢀ1074ꢀentitledꢀ“OptocouplerꢀInput-OutputꢀEnduranceꢀVoltage.”
Notes:
1.ꢀ Derateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ0.8ꢀmA/°Cꢀ(8-PinꢀDIP).ꢀ
Derateꢀlinearlyꢀaboveꢀ85°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ0.5ꢀmA/°Cꢀ(SO-8).
2.ꢀ Derateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ1.6ꢀmA/°Cꢀ(8-PinꢀDIP).ꢀ
Derateꢀlinearlyꢀaboveꢀ85°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ1.0ꢀmA/°Cꢀ(SO-8).
3.ꢀ Derateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ0.9ꢀmW/°Cꢀ(8-PinꢀDIP).ꢀ
Derateꢀlinearlyꢀaboveꢀ85°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ1.1ꢀmW/°Cꢀ(SO-8).
4.ꢀ Derateꢀlinearlyꢀaboveꢀ70°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ2.0ꢀmW/°Cꢀ(8-PinꢀDIP).ꢀ
Derateꢀlinearlyꢀaboveꢀ85°Cꢀfree-airꢀtemperatureꢀatꢀaꢀrateꢀofꢀ2.3ꢀmW/°Cꢀ(SO-8).
5.ꢀ CURRENTꢀTRANSFERꢀRATIOꢀinꢀpercentꢀisꢀdefinedꢀasꢀtheꢀratioꢀofꢀoutputꢀcollectorꢀcurrent,ꢀIO,ꢀtoꢀtheꢀforwardꢀLEDꢀinputꢀcurrent,ꢀIF,ꢀtimesꢀ100.
6.ꢀ Deviceꢀconsideredꢀaꢀtwo-terminalꢀdevice:ꢀPinsꢀ1,ꢀ2,ꢀ3,ꢀandꢀ4ꢀshortedꢀtogetherꢀandꢀPinsꢀ5,ꢀ6,ꢀ7,ꢀandꢀ8ꢀshortedꢀtogether.
7.ꢀ UnderꢀTTLꢀloadꢀandꢀdriveꢀconditions:ꢀCommonꢀmodeꢀtransientꢀimmunityꢀinꢀaꢀLogicꢀHighꢀlevelꢀisꢀtheꢀmaximumꢀtolerableꢀ(positive)ꢀdVCM/dtꢀonꢀ
theꢀleadingꢀedgeꢀofꢀtheꢀcommonꢀmodeꢀpulse,ꢀVCM,ꢀtoꢀassureꢀthatꢀtheꢀoutputꢀwillꢀremainꢀinꢀaꢀLogicꢀHighꢀstateꢀ(i.e.,ꢀV ꢀ>ꢀ2.0ꢀV).ꢀCommonꢀmodeꢀ
O
transientꢀimmunityꢀinꢀaꢀLogicꢀLowꢀlevelꢀisꢀtheꢀmaximumꢀtolerableꢀ(negative)ꢀdVCM/dtꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀcommonꢀmodeꢀpulseꢀsignal,ꢀ
VCM,ꢀtoꢀassureꢀthatꢀtheꢀoutputꢀwillꢀremainꢀinꢀaꢀLogicꢀLowꢀstateꢀ(i.e.,ꢀVOꢀ<ꢀ0.8ꢀV).
8.ꢀꢀ UnderꢀIPMꢀ(IntelligentꢀPowerꢀModule)ꢀloadꢀandꢀLEDꢀdriveꢀconditions:ꢀCommonꢀmodeꢀtransientꢀimmunityꢀinꢀaꢀLogicꢀHighꢀlevelꢀisꢀtheꢀmaximumꢀ
tolerableꢀdVCM/dtꢀonꢀtheꢀleadingꢀedgeꢀofꢀtheꢀcommonꢀmodeꢀpulse,ꢀVCM,ꢀtoꢀassureꢀthatꢀtheꢀoutputꢀwillꢀremainꢀinꢀaꢀLogicꢀHighꢀstateꢀ(i.e.,ꢀVOꢀ>ꢀ3.0ꢀ
V).ꢀCommonꢀmodeꢀtransientꢀimmunityꢀinꢀaꢀLogicꢀLowꢀlevelꢀisꢀtheꢀmaximumꢀtolerableꢀdVCM/dtꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀcommonꢀmodeꢀpulseꢀ
signal,ꢀVCM,ꢀtoꢀassureꢀthatꢀtheꢀoutputꢀwillꢀremainꢀinꢀaꢀLogicꢀLowꢀstateꢀ(i.e.,ꢀVOꢀ<ꢀ1.0ꢀV).
9.ꢀꢀ Theꢀ1.9ꢀkΩꢀloadꢀrepresentsꢀ1ꢀTTLꢀunitꢀloadꢀofꢀ1.6ꢀmAꢀandꢀtheꢀ5.6ꢀkΩꢀpull-upꢀresistor.
10.ꢀꢀTheꢀRLꢀ=ꢀ20ꢀkΩ,ꢀCLꢀ=ꢀ100ꢀpFꢀloadꢀrepresentsꢀanꢀIPMꢀ(IntelligentꢀPowerꢀModule)ꢀload.
11.ꢀꢀSeeꢀOptionꢀ020ꢀdataꢀsheetꢀforꢀmoreꢀinformation.
12.ꢀꢀUseꢀofꢀaꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀconnectedꢀbetweenꢀPinsꢀ5ꢀandꢀ8ꢀisꢀrecommended.
13.ꢀꢀInꢀaccordanceꢀwithꢀULꢀ1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥4500ꢀVꢀrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetectionꢀ
currentꢀlimit,ꢀIi-oꢀ≤5ꢀµA).
14.ꢀꢀInꢀaccordanceꢀwithꢀULꢀ1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥4500ꢀVꢀrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetectionꢀ
currentꢀlimit,ꢀIi-oꢀ≤ꢀ5ꢀµA).
15.ꢀꢀInꢀaccordanceꢀwithꢀULꢀ1577,ꢀeachꢀoptocouplerꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥6000ꢀVꢀrmsꢀforꢀ1ꢀsecondꢀ(leakageꢀdetectionꢀ
currentꢀlimit,ꢀIi-oꢀ≤5ꢀµA).
16.ꢀꢀThisꢀtestꢀisꢀperformedꢀbeforeꢀtheꢀ100%ꢀProductionꢀtestꢀshownꢀinꢀtheꢀVDEꢀ0884ꢀInsulationꢀRelatedꢀCharacteristicsꢀTable,ꢀifꢀapplicable.
17.ꢀꢀTheꢀdifferenceꢀbetweenꢀtPLHꢀandꢀtPHLꢀbetweenꢀanyꢀtwoꢀdevicesꢀ(sameꢀpartꢀnumber)ꢀunderꢀtheꢀsameꢀtestꢀcondition.ꢀ(SeeꢀPowerꢀInverterꢀDeadꢀ
TimeꢀandꢀPropagationꢀDelayꢀSpecificationsꢀsection.)
13
HCPL-4504/0454
HCNW4504
HCPL-J454
= 25° C
25
20
15
10
40 mA
35 mA
T
CC
= 25°C
T = 25°C
A
CC
A
T
V
A
10
20
18
16
14
12
10
8
V
= 5.0 V
V
= 5.0 V
= 5.0 V
CC
40 mA
35 mA
40 mA
35 mA
30 mA
25 mA
20 mA
30 mA
25 mA
20 mA
30 mA
25 mA
20 mA
5
15 mA
10 mA
15 mA
10 mA
15 mA
10 mA
6
5
0
4
I
= 5 mA
F
I
= 5 mA
F
2
0
I
= 5 mA
F
0
0
20
0
20
10
– OUTPUT VOLTAGE – V
10
V – OUTPUT VOLTAGE – V
O
0
5
10
15
20
V
– OUTPUT VOLTAGE – V
O
V
O
Figure 1. DC and pulsed transfer characteristics.
HCPL-4504/0454
1.5
HCPL-J454
HCNW4504
NORMALIZED
2.0
1.5
1.0
0.5
0
NORMALIZED
2.0
1.6
1.2
0.8
0.4
0
I
= 16 mA
F
O
I
V
V
= 16 mA
F
V
= 0.4 V
= 5.0 V
= 25°C
= 0.4 V
O
V
T
CC
= 5.0 V
CC
1.0
A
T
= 25° C
A
0.5
0.0
NORMALIZED
= 16 mA
I
F
V
= 0.4 V
O
V
= 5.0 V
CC
T
= 25°C
A
0
2
4
I
6
8 10 12 14 16 18 20 22 24 26
0
5
10
15
20
25
0
5
10
15
20
25
I
– INPUT CURRENT – mA
– INPUT CURRENT – mA
F
I
– INPUT CURRENT – mA
F
F
Figure 2. Current transfer ratio vs. input current.
HCPL-4504/0454
1000
HCPL-J454/HCNW4504
= 25°C
1000
100
10
T
A
100
I
I
F
F
T
A
= 25°C
+
+
10
1.0
V
V
F
F
–
–
1.0
0.1
0.1
0.01
0.001
0.01
0.001
1.1
1.2
1.3
1.4
1.5
1.6
1.2
1.3
V – FORWARD VOLTAGE – VOLTS
F
1.4
1.5
1.6
1.7
V
– FORWARD VOLTAGE – VOLTS
F
Figure 3. Input current vs. forward voltage.
14
HCPL-4504/0454
HCNW4504
NORMALIZED
HCPL-J454
1.1
1.0
1.05
1.0
1.05
1.0
NORMALIZED
= 16 mA
I
= 16 mA
F
O
I
F
O
CC
A
V
= 0.4 V
V
V
T
= 0.4 V
= 5.0 V
= 25° C
V
= 5.0 V
= 25°C
CC
T
A
0.9
0.8
0.7
0.6
NORMALIZED
= 16 mA
0.95
0.9
0.95
0.9
I
F
V
= 0.4 V
O
V
= 5.0 V
CC
= 25°C
T
A
0.85
0.85
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100 120
T – TEMPERATURE – °C
A
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 4. Current transfer ratio vs. temperature.
4
10
3
10
I
V
= 0 mA
F
= V = 5.0 V
O
CC
2
10
1
0
10
10
-1
10
10
-2
-60 -40 -20
0
20 40 60 80 100 120
T
– TEMPERATURE – °C
A
Figure 5. Logic high output current vs. temperature.
I
F
I
PULSE
GEN.
F
8
7
6
5
1
2
3
4
V
CC
0
Z
t
= 50 Ω
O
r
= 5 ns
R
V
L
CC
V
O
V
O
V
V
THLH
THHL
0.1µF
V
I
MONITOR
F
OL
C
L
R
M
t
t
PHL
PLH
Figure 6. Switching test circuit.
8
7
6
5
V
CC
1
2
3
4
V
CM
90% 90%
I
F
0 V
10%
10%
R
L
t
r
A
t
f
B
V
O
0.1µF
V
V
O
CC
SWITCH AT A: I = 0 mA
F
C
L
V
FF
V
V
+
O
V
CM
OL
–
SWITCH AT B: I = 12 mA, 16 mA
F
PULSE GEN.
Figure 7. Test circuit for transient immunity and typical waveforms.
15
HCPL-4504/0454
= 5.0 V
R = 1.9 kΩ
HCPL-J454/HCNW4504
= 5.0 V
R = 1.9 kΩ
0.50
0.45
0.50
0.45
1.4
1.2
1.0
0.8
V
V
= 5.0 V
= 25° C
= 15 pF
= V
V
CC
CC
CC
T
L
A
L
C = 15 pF
C
V
C = 15 pF
L
L
L
0.40
0.40
V
= V
= 1.5 V
= 1.5 V
THLH
V
= V
= 1.5 V
THLH
THHL
THLH
THHL
THHL
t
t
PLH
PLH
10% DUTY CYCLE
10% DUTY CYCLE
10% DUTY CYCLE
t
0.35
0.30
0.25
0.35
0.30
0.25
PLH
t
PHL
t
0.6
0.4
0.2
0.0
PHL
I
= 10 mA
= 16 mA
F
t
PHL
I
F
0.20
0.20
I
= 10 mA
= 16 mA
I
= 10 mA
= 16 mA
F
F
0.15
0.10
0.15
0.10
I
I
F
F
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120
0
2
4
6
8
– LOAD RESISTANCE – kΩ
L
10 12 14 16 18 20
R
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 8. Propagation delay time vs. temperature.
Figure 9. Propagation delay time vs. load resis-
tance.
HCPL-4504/0454
HCPL-J454/HCNW4504
1.1
2.6
2.4
1.1
1.0
V
= 15.0 V
V
= 5.0 V
= 25° C
= 100 pF
I
= 10 mA
I = 16 mA
F
V
R
= 15.0 V
= 20 kΩ
I
= 10 mA
I = 16 mA
F
CC
CC
F
CC
L
F
R
= 20 kΩ
T
1.0
0.9
L
A
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
C = 100 pF
C
C = 100 pF
L
L
L
0.9
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
50% DUTY CYCLE
THHL
THLH
THHL
THLH
THHL
THLH
t
t
PLH
PLH
0.8
0.7
0.6
0.8
0.7
0.6
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
I
= 10 mA
I = 16 mA
F
F
t
PHL
8
0.5
0.5
t
t
PHL
PHL
0.4
0.3
0.4
0.3
0.2
0.0
-60 -40 -20
0
20 40
-60 -40 -20
0
20 40
60 80 100 120
60 80 100 120
T – TEMPERATURE – °C
A
0
2
4
6
10 12 14 16 18 20
T
– TEMPERATURE – °C
R – LOAD RESISTANCE – kΩ
A
L
Figure 10. Propagation delay time vs. load
resistance.
Figure 11. Propagation delay time vs. temperature.
1.8
3.5
1.2
1.1
1.0
V
= 15.0 V
V
= 15.0 V
= 25° C
T = 25° C
A
L
CC
= 25° C
CC
t
PLH
PHL
1.6
1.4
T
T
R = 20 kΩ
A
A
3.0
2.5
2.0
1.5
1.0
0.5
C = 100 pF
R = 20 kΩ
C = 100 pF
L
L
L
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
THHL
THLH
THHL
THLH
THHL
THLH
0.9
0.8
0.7
1.2
1.0
0.8
0.6
0.4
t
PLH
50% DUTY CYCLE
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
t
t
0.6
0.5
0.4
0.3
0.2
PHL
t
PHL
I
I
= 10 mA
= 16 mA
F
I
I
= 10 mA
= 16 mA
F
I
I
= 10 mA
= 16 mA
F
F
0.2
0.0
F
F
0.0
0
100 200 300 400 500 600 700 800 9001000
– LOAD CAPACITANCE – pF
10 11 12 13 14 15 16 17 18 19 20
– SUPPLY VOLTAGE – V
0
5
10 15 20 25 30 35 40 45 50
C
R
– LOAD RESISTANCE – kΩ
V
CC
L
L
Figure 12. Propagation delay time vs. load
resistance.
Figure 13. Propagation delay time vs. load
capacitance.
Figure 14. Propagation delay time vs. supply
voltage.
16
HCPL-4504 OPTION 060/HCPL-J454
HCPL-0454 OPTION 060/HCNW4504
1000
800
700
600
500
400
300
P
(mWꢀ for HCNW4504
(mAꢀ for HCNW4504
(mWꢀ for HCPL-0454
S
P
(mWꢀ
S
900
800
700
600
500
400
300
I
P
S
I
(mAꢀ for HCPL-4504
OPTION 060
(mAꢀ for HCPL-J454
S
S
OPTION 060
I
S
I
(mAꢀ for HCPL-0454
S
OPTION 060
(230ꢀ
200
200
(150ꢀ
100
100
0
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25
50 75 100 125 150 175
T
T – CASE TEMPERATURE – °C
S
S
Figure 15. Thermal derating curve, dependence of safety limiting valve with case temperature per
IEC/EN/DIN EN 60747-5-2.
+HV
+
HCPL-4504/0454/J454
HCNW4504
8
7
6
2
3
LED 1
BASE/GATE
DRIVE CIRCUIT
Q1
OUT 1
5
+
HCPL-4504/0454/J454
HCNW4504
8
7
6
2
3
LED 2
BASE/GATE
DRIVE CIRCUIT
Q2
OUT 2
5
–HV
Figure 16. Typical power inverter.
17
Figure 17. LED delay and dead time diagram.
Power Inverter Dead Time and Propagation Delay Specifica-
tions
Theꢀ HCPL-4504/0454/J454ꢀ andꢀ HCNW4504ꢀ includeꢀ aꢀ
specificationꢀintendedꢀtoꢀhelpꢀdesignersꢀminimizeꢀ“deadꢀ
time”ꢀinꢀtheirꢀpowerꢀinverterꢀdesigns.ꢀTheꢀnewꢀ“propaga-
tionꢀdelayꢀdifference”ꢀspecificationꢀ(tPLHꢀ-ꢀtPHL)ꢀisꢀusefulꢀforꢀ
determiningꢀ notꢀ onlyꢀ howꢀ muchꢀ optocouplerꢀ switch-
ingꢀdelayꢀisꢀneededꢀtoꢀpreventꢀ“shoot-through”ꢀcurrent,ꢀ
butꢀalsoꢀforꢀdeterminingꢀtheꢀbestꢀachievableꢀworst-caseꢀ
deadꢀtimeꢀforꢀaꢀgivenꢀdesign.
Theꢀamountꢀofꢀturn-onꢀdelayꢀneededꢀdependsꢀonꢀtheꢀ
propagationꢀdelayꢀcharacteristicsꢀofꢀtheꢀoptocoupler,ꢀasꢀ
wellꢀasꢀtheꢀcharacteristicsꢀofꢀtheꢀtransistorꢀbase/gateꢀdriveꢀ
circuit.ꢀConsideringꢀonlyꢀtheꢀdelayꢀcharacteristicsꢀofꢀtheꢀ
optocouplerꢀ(theꢀcharacteristicsꢀofꢀtheꢀbase/gateꢀdriveꢀ
circuitꢀcanꢀbeꢀanalyzedꢀinꢀtheꢀsameꢀway),ꢀitꢀisꢀimportantꢀ
toꢀknowꢀtheꢀminimumꢀandꢀmaximumꢀturn-onꢀ(tPHL)ꢀandꢀ
turnoffꢀ (tPLH)ꢀ propagationꢀ delayꢀ specifications,ꢀ prefer-
ablyꢀoverꢀtheꢀdesiredꢀoperatingꢀtemperatureꢀrange.ꢀTheꢀ
importanceꢀofꢀtheseꢀspecificationsꢀisꢀillustratedꢀinꢀFigureꢀ
17.ꢀTheꢀ waveformsꢀ labeledꢀ“LED1”,ꢀ“LED2”,ꢀ“OUT1”,ꢀ andꢀ
“OUT2”ꢀareꢀtheꢀinputꢀandꢀoutputꢀvoltagesꢀofꢀtheꢀopto-
couplerꢀcircuitsꢀdrivingꢀQ1ꢀandꢀQ2ꢀrespectively.ꢀMostꢀin-
vertersꢀareꢀdesignedꢀsuchꢀthatꢀtheꢀpowerꢀtransistorꢀturnsꢀ
onꢀwhenꢀtheꢀoptocouplerꢀLEDꢀturnsꢀon;ꢀthisꢀensuresꢀthatꢀ
bothꢀpowerꢀtransistorsꢀwillꢀbeꢀoffꢀinꢀtheꢀeventꢀofꢀaꢀpowerꢀ
lossꢀinꢀtheꢀcontrolꢀcircuit.ꢀInvertersꢀcanꢀalsoꢀbeꢀdesignedꢀ
suchꢀthatꢀtheꢀpowerꢀtransistorꢀturnsꢀoffꢀwhenꢀtheꢀopto-
couplerꢀLEDꢀturnsꢀon;ꢀthisꢀtypeꢀofꢀdesign,ꢀhowever,ꢀre-
quiresꢀadditionalꢀfail-safeꢀcircuitryꢀtoꢀturnꢀoffꢀtheꢀpowerꢀ
transistorꢀ ifꢀ anꢀ over-currentꢀ conditionꢀ isꢀ detected.ꢀTheꢀ
timingꢀillustratedꢀinꢀFigureꢀ17ꢀassumesꢀthatꢀtheꢀpowerꢀ
transistorꢀturnsꢀonꢀwhenꢀtheꢀoptocouplerꢀLEDꢀturnsꢀon.
Whenꢀinverterꢀpowerꢀtransistorsꢀswitchꢀ(Q1ꢀandꢀQ2ꢀinꢀ
Figureꢀ17),ꢀitꢀisꢀessentialꢀthatꢀtheyꢀneverꢀconductꢀatꢀtheꢀ
sameꢀtime.ꢀExtremelyꢀlargeꢀcurrentsꢀwillꢀflowꢀifꢀthereꢀisꢀ
anyꢀoverlapꢀinꢀtheirꢀconductionꢀduringꢀswitchingꢀtran-
sitions,ꢀ potentiallyꢀ damagingꢀ theꢀ transistorsꢀ andꢀ evenꢀ
theꢀsurroundingꢀcircuitry.ꢀThisꢀ“shoot-through”ꢀcurrentꢀisꢀ
eliminatedꢀbyꢀdelayingꢀtheꢀturn-onꢀofꢀoneꢀtransistorꢀ(Q2)ꢀ
longꢀenoughꢀtoꢀensureꢀthatꢀtheꢀopposingꢀtransistorꢀ(Q1)ꢀ
hasꢀcompletelyꢀturnedꢀoff.ꢀThisꢀdelayꢀintroducesꢀaꢀsmallꢀ
amountꢀofꢀ“deadꢀtime”ꢀatꢀtheꢀoutputꢀofꢀtheꢀinverterꢀdur-
ingꢀwhichꢀbothꢀtransistorsꢀareꢀoffꢀduringꢀswitchingꢀtran-
sitions.ꢀMinimizingꢀthisꢀdeadꢀtimeꢀisꢀanꢀimportantꢀdesignꢀ
goalꢀforꢀanꢀinverterꢀdesigner.
18
Thisꢀexpressionꢀcanꢀbeꢀrearrangedꢀtoꢀobtainꢀ
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
TheꢀLEDꢀsignalꢀtoꢀturnꢀonꢀQ2ꢀshouldꢀbeꢀdelayedꢀenoughꢀ
soꢀ thatꢀ anꢀ optocouplerꢀ withꢀ theꢀ veryꢀ fastestꢀ turn-onꢀ
propagationꢀdelayꢀ(tPHLmin)ꢀwillꢀneverꢀturnꢀonꢀbeforeꢀanꢀ
optocouplerꢀwithꢀtheꢀveryꢀslowestꢀturn-offꢀpropagationꢀ
delayꢀ(tPLHmax)ꢀturnsꢀoff.ꢀToꢀensureꢀthis,ꢀtheꢀturn-onꢀofꢀtheꢀ
optocouplerꢀ shouldꢀ beꢀ delayedꢀ byꢀ anꢀ amountꢀ noꢀ lessꢀ
thanꢀ(tPLHmaxꢀ-ꢀtPHLmin),ꢀwhichꢀalsoꢀhappensꢀtoꢀbeꢀtheꢀmax-
imumꢀdataꢀsheetꢀvalueꢀforꢀtheꢀpropagationꢀdelayꢀdiffer-
enceꢀspecification,ꢀ(tPLHꢀ-ꢀtPHL).ꢀTheꢀHCPL-4504/0454/J454ꢀ
andꢀHCNW4504ꢀspecifyꢀaꢀmaximumꢀ(tPLHꢀ-ꢀtPHL)ꢀofꢀ1.3ꢀµsꢀ
overꢀanꢀoperatingꢀtemperatureꢀrangeꢀofꢀ0-70°C.
andꢀfurtherꢀrearrangedꢀtoꢀobtain
[(tPLH-tPHL max-(tPLH-tPHL)min],
)
whichꢀisꢀtheꢀmaximumꢀminusꢀtheꢀminimumꢀdataꢀsheetꢀ
valuesꢀ ofꢀ (tPLH-tPHL).ꢀTheꢀ differenceꢀ betweenꢀ theꢀ maxi-
mumꢀandꢀminimumꢀvaluesꢀdependsꢀdirectlyꢀonꢀtheꢀtotalꢀ
spreadꢀinꢀpropagationꢀdelaysꢀandꢀsetsꢀtheꢀlimitꢀonꢀhowꢀ
goodꢀtheꢀworst-caseꢀdeadꢀtimeꢀcanꢀbeꢀforꢀaꢀgivenꢀdesign.ꢀ
Therefore,ꢀ optocouplersꢀ withꢀ tightꢀ propagationꢀ delayꢀ
specificationsꢀ(andꢀnotꢀjustꢀshorterꢀdelaysꢀorꢀlowerꢀpulse-
widthꢀdistortion)ꢀcanꢀachieveꢀshortꢀdeadꢀtimesꢀinꢀpowerꢀ
inverters.ꢀ Theꢀ HCPL-4504/0454/J454ꢀ andꢀ HCNW4504ꢀ
specifyꢀaꢀminimumꢀ(tPLHꢀ-ꢀtPHL)ꢀofꢀ-0.7ꢀµsꢀoverꢀanꢀoperat-
ingꢀtemperatureꢀrangeꢀofꢀ0-70°C,ꢀresultingꢀinꢀaꢀmaximumꢀ
deadꢀtimeꢀofꢀ2.0ꢀµsꢀwhenꢀtheꢀLEDꢀturn-onꢀdelayꢀisꢀequalꢀ
Althoughꢀ(tPLH-tPHL maxꢀtellsꢀtheꢀdesignerꢀhowꢀmuchꢀdelayꢀ
)
isꢀneededꢀtoꢀpreventꢀshoot-throughꢀcurrent,ꢀitꢀisꢀinsuffi-
cientꢀtoꢀtellꢀtheꢀdesignerꢀhowꢀmuchꢀdeadꢀtimeꢀaꢀdesignꢀ
willꢀhave.ꢀAssumingꢀthatꢀtheꢀoptocouplerꢀturn-onꢀdelayꢀ
isꢀexactlyꢀequalꢀtoꢀ(tPLHꢀ-ꢀtPHL max,ꢀtheꢀminimumꢀdeadꢀtimeꢀ
)
isꢀzeroꢀ(i.e.,ꢀthereꢀisꢀzeroꢀtimeꢀbetweenꢀtheꢀturnoffꢀofꢀtheꢀ
veryꢀ slowestꢀ optocouplerꢀ andꢀ theꢀ turn-onꢀ ofꢀ theꢀ veryꢀ
fastestꢀoptocoupler).
toꢀ(tPLH-tPHL max
ItꢀisꢀimportantꢀtoꢀmaintainꢀaccurateꢀLEDꢀturn-onꢀdelaysꢀ
becauseꢀ delaysꢀ shorterꢀ thanꢀ (tPLHꢀ-ꢀtPHL maxꢀ mayꢀ allowꢀ
)
,ꢀorꢀ1.3ꢀµs.
Calculatingꢀ theꢀ maximumꢀ deadꢀ timeꢀ isꢀ slightlyꢀ moreꢀ
complicated.ꢀAssumingꢀthatꢀtheꢀLEDꢀturn-onꢀdelayꢀisꢀstillꢀ
)
shoot-throughꢀcurrents,ꢀwhileꢀlongerꢀdelaysꢀwillꢀincreaseꢀ
theꢀworst-caseꢀdeadꢀtime.
exactlyꢀequalꢀtoꢀ(tPLHꢀ-ꢀtPHL max,ꢀitꢀcanꢀbeꢀseenꢀinꢀFigureꢀ17ꢀ
)
thatꢀtheꢀmaximumꢀdeadꢀtimeꢀisꢀtheꢀsumꢀofꢀtheꢀmaximumꢀ
differenceꢀinꢀturn-onꢀdelayꢀplusꢀtheꢀmaximumꢀdifferenceꢀ
inꢀturnoffꢀdelay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].
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Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0552EN
AV02-0867EN - June 20, 2008
相关型号：
HCPL-J456-300E
Logic IC Output Optocoupler, 1-Element, 3750V Isolation, 0.300 INCH, SURFACE MOUNT, DIP-8
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