HSMP-3860-BLKG [AVAGO]
Unique Configurations in Surface Mount Packages;
| 型号： | HSMP-3860-BLKG |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Unique Configurations in Surface Mount Packages 衰减器 开关 测试 光电二极管 |
| 文件： | 总10页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSMP-386x
Surface Mount PIN Diodes
Data Sheet
Description/Applications
Features
The HSMP-386x series of general purpose PIN diodes are • Unique Configurations in Surface Mount Packages
designed for two classes of applications. The first is attenu-
ators where current consumption is the most important
design consideration. The second application for this
series of diodes is in switches where low capacitance is the
driving issue for the designer.
– Add Flexibility
– Save Board Space
– Reduce Cost
• Switching
– Low Distortion Switching
– Low Capacitance
The HSMP-386x series Total Capacitance (CT) and Total
Resistance (RT) are typical specifications. For applications
that require guaranteed performance, the general purpose
HSMP-383x series is recommended.
• Attenuating
–
Low Current Attenuating for Less Power
Consumption
• Matched Diodes for Consistent Performance
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, carrier
lifetime.
• Better Thermal Conductivity for Higher Power
Dissipation
• Low Failure in Time (FIT) Rate[1]
Pin Connections and Package Marking, SOT-363
• Lead-free
Note:
1
2
3
6
5
4
1. For more information see the Surface Mount PIN Reliability Data
Sheet.
Notes:
1. Package marking provides orientation, identification, and date code.
2. See “Electrical Specifications”for appropriate package marking.
Package Lead Code Identification,
SOT-23, SOT-143
(Top View)
Package Lead Code Identification,
SOT-323
(Top View)
Package Lead Code Identification,
SOT-363
(Top View)
SERIES
SINGLE
SERIES
SINGLE
UNCONNECTED
TRIO
6
5
4
#0
#2
B
C
1
2
3
L
COMMON
ANODE
COMMON
CATHODE
COMMON
ANODE
COMMON
CATHODE
#3
E
#4
F
RING
QUAD
3
4
1
2
D
See separate data sheet HSMP-386D
Absolute Maximum Ratings[1] TC = +25°C
ESD WARNING:
Handling Precautions Should Be Taken To Avoid
Static Discharge.
Symbol
Parameter
Unit
Amp
V
SOT-23
1
SOT-323
1
If
Forward Current (1 µs Pulse)
Peak Inverse Voltage
Junction Temperature
Storage Temperature
Thermal Resistance[2]
PIV
50
50
Tj
°C
150
150
Tstg
qjc
°C
-65 to 150
500
-65 to 150
150
°C/W
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to
the circuit board.
Electrical Specifications TC = 25°C, each diode
PIN General Purpose Diodes, Typical Specifications TA = 25°C
Package
Marking
Code
Minimum
Breakdown
Voltage VBR (V)
Typical
Series Resistance
RS (Ω)
Typical
Total Capacitance
CT (pF)
Part Number
HSMP-
Lead
Code
Configuration
3860
3862
3863
3864
386B
386C
386E
386F
386L
L0
L2
L3
L4
L0
L2
L3
L4
LL
0
2
3
4
B
C
E
F
L
Single
50
3.0/1.5*
0.20
Series
Common Anode
Common Cathode
Single
Series
Common Anode
Common Cathode
Unconnected Trio
Test Conditions
VR = V
IF = 10 mA
f = 100 MHz
IF = 100 mA*
VR = 50 V
f = 1 MHz
MeasuBrRe
IR ≤ 10 µA
2
HSMP-386x Typical Parameters at TC = 25°C
Part Number
HSMP-
Total Resistance
Carrier Lifetime
t (ns)
Reverse Recovery Time
Trr (ns)
Total Capacitance
CT (pF)
RT (Ω)
386x
22
500
80
0.20
Test Conditions
IF = 1 mA
f = 100 MHz
IF = 50 mA
TR = 250 mA
VR = 10 V
IF = 20 mA
VR = 50 V
f = 1 MHz
90% Recovery
Typical Performance, TC = 25°C, each diode
1000
0.35
120
115
110
105
100
95
TA = +85 C
TA = +25 C
TA = –55 C
Diode Mounted as a
Series Switch in a
50 Microstrip and
Tested at 123 MHz
0.30
100
1 MHz
0.25
100 MHz
10
1
0.20
1 GHz
90
85
0.15
0
2
4
6
8
10 12 14 16 18 20
0.01
0.1
1
10
100
1
10
30
REVERSE VOLTAGE (V)
BIAS CURRENT (mA)
I
– FORWARD BIAS CURRENT (mA)
F
Figure 1. RF Capacitance vs. Reverse Bias.
Figure 2. Typical RF Resistance vs. Forward Bias
Current.
Figure 3. 2nd Harmonic Input Intercept Point
vs. Forward Bias Current for Switch Diodes.
1000
100
10
VR = 5V
V
R = 10V
1
100
10
VR = 20V
0.1
125 C 25 C –50 C
0.01
0
0.2
0.4
0.6
0.8
1.0 1.2
10
20
FORWARD CURRENT (mA)
30
V
– FORWARD VOLTAGE (mA)
F
Figure 4. Reverse Recovery Time vs. Forward
Current for Various Reverse Voltages.
Figure 5. Forward Current vs. Forward
Voltage.
Equivalent Circuit Model
HSMP-386x Chip*
R
R
s
j
RT = 1.5 + Rj
CT = CP + Cj
12
1.5 Ω
Rj =
Ω
Cj
I0.9
I = Forward Bias Current in mA
* See AN1124 for package models
0.12 pF
3
Typical Applications for Multiple Diode Products
RF COMMON
RF COMMON
RF 1
RF 2
RF 2
RF 1
BIAS 1
BIAS 2
BIAS
BIAS
Figure 6. Simple SPDT Switch, Using Only Positive Current.
Figure 7. High Isolation SPDT Switch, Dual Bias.
RF COMMON
RF COMMON
BIAS
RF 1
RF 2
RF 2
RF 1
BIAS
Figure 8. Switch Using Both Positive and Negative Current.
Figure 9. Very High Isolation SPDT Switch, Dual Bias.
VARIABLE BIAS
RF IN/OUT
INPUT
FIXED
BIAS
VOLTAGE
Figure 10. Four Diode π Attenuator. See AN1048 for details.
4
Typical Applications for Multiple Diode Products (continued)
BIAS
1
+V
0
2
0
+V
“ON”
“OFF”
1
1
6
1
5
2
4
3
RF out
RF in
2
Figure 11. High Isolation SPST Switch
(Repeat Cells as Required).
Figure 12. HSMP-386L Unconnected Trio used in a Positive Voltage,
High Isolation Switch.
1
2
3
2
1
0
0
2
+V
–V
3
4
2
5
1
6
“ON”
“OFF”
0
1
1
3
4
2
5
1
6
b1
b2
b3
RF out
RF in
Figure 14. HSMP-386L Unconnected Trio used in a Dual Voltage,
High Isolation Switch.
Figure 13. HSMP-386L used in a SP3T Switch.
5
Ordering Information
Specify part number followed by option. For example:
HSMP - 386x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLKG = Bulk, 100 pcs. per antistatic bag
-TR1G = Tape and Reel, 3000 devices per 7" reel
-TR2G = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481,
“Taping of Surface Mounted Components for Automated Placement.”
Assembly Information
SOT-323 PCB Footprint
0.026
Recommended PCB pad layouts for the miniature SOT
packages are shown in Figures 15, 16, 17. These layouts
provide ample allowance for package placement by
automated assembly equipment without adding parasitics
that could impair the performance.
0.079
0.039
0.026
0.018
Dimensions in inches
0.079
Figure16. RecommendedPCBPadLayoutforAvago’sSC706L/SOT-363Products.
0.039
1
0.039
0.039
1
0.022
Dimensions in inches
0.079
2.0
Figure 15. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323
Products.
0.035
0.9
0.031
0.8
inches
Dimensions in
mm
Figure 17. Recommended PCB Pad Layout for Avago’s SOT-23 Products.
6
SMT Assembly
preheat zones increase the temperature of the board and
components to prevent thermal shock and begin evapo-
rating solvents from the solder paste. The reflow zone
briefly elevates the temperature sufficiently to produce a
reflow of the solder.
Reliable assembly of surface mount components is a
complex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reflow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the SOT
package, will reach solder reflow temperatures faster than
those with a greater mass.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not cause
deformation of the board or damage to components due
to thermal shock. The maximum temperature in the reflow
zone (TMAX) should not exceed 260°C.
Avago’s diodes have been qualified to the time-temper-
ature profile shown in Figure 18. This profile is represen-
tative of an IR reflow type of surface mount assembly
process.
These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the circuit
board and components should be exposed only to the
minimum temperatures and times necessary to achieve a
uniform reflow of solder.
After ramping up from room temperature, the circuit board
with components attached to it (held in place with solder
paste) passes through one or more preheat zones. The
tp
Critical Zone
Tp
T
to Tp
L
Ramp-up
T
L
tL
Ts
max
Ts
min
Ramp-down
ts
Preheat
25
t 25° C to Peak
Time
Figure 18. Surface Mount Assembly Profile.
Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C)
Reflow Parameter
Lead-Free Assembly
3°C/ second max
150°C
Average ramp-up rate (Liquidus Temperature (TS(max) to Peak)
Preheat
Temperature Min (TS(min))
Temperature Max (TS(max)
)
200°C
Time (min to max) (tS)
60-180 seconds
3°C/second max
217°C
Ts(max) to TL Ramp-up Rate
Time maintained above:
Temperature (TL)
Time (tL)
60-150 seconds
260 +0/-5°C
Peak Temperature (TP)
Time within 5 °C of actual Peak temperature (tP)
Ramp-down Rate
20-40 seconds
6°C/second max
8 minutes max
Time 25 °C to Peak Temperature
Note 1: All temperatures refer to topside of the package, measured on the package body surface
7
Package Dimensions
Outline 23 (SOT-23)
Outline SOT-323 (SC-70, 3 Lead)
e1
e2
e1
E1
E
XXX
E1
E
XXX
e
L
B
e
C
L
D
DIMENSIONS (mm)
B
D
C
SYMBOL
MIN.
0.80
0.00
0.15
0.08
1.80
1.10
MAX.
1.00
0.10
0.40
0.25
2.25
1.40
A
A1
B
C
D
E1
e
e1
E
DIMENSIONS (mm)
A
SYMBOL
MIN.
0.79
0.000
0.30
0.08
2.73
1.15
0.89
1.78
0.45
2.10
0.45
MAX.
1.20
0.100
0.54
0.20
3.13
1.50
1.02
2.04
0.60
2.70
0.69
A
A1
B
C
D
E1
e
e1
e2
E
A1
A
0.65 typical
1.30 typical
Notes:
A1
1.80
0.26
2.40
0.46
XXX-package marking
Drawings are not to scale
L
Notes:
XXX-package marking
Drawings are not to scale
L
Outline 363 (SC-70, 6 Lead)
HE
E
L
e
c
D
DIMENSIONS (mm)
SYMBOL
E
D
HE
A
A2
A1
e
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
A1
A2
A
0.650 BCS
b
c
L
0.15
0.08
0.10
0.30
0.25
0.46
b
Package Characteristics
Lead Material ........................................... Copper (SOT-323/363); Alloy 42 (SOT-23)
Lead Finish.........................................................................Tin 100% (Lead-free option)
Maximum Soldering Temperature............................................ 260°C for 5 seconds
Minimum Lead Strength........................................................................... 2 pounds pull
Typical Package Inductance...................................................................................... 2 nH
Typical Package Capacitance..............................................0.08 pF (opposite leads)
8
Device Orientation
REEL
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
For Outlines SOT-23, -323
For Outline SOT-363
TOP VIEW
END VIEW
TOP VIEW
4 mm
END VIEW
4 mm
8 mm
8 mm
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Note: "AB" represents package marking code.
"C" represents date code.
Note: "AB" represents package marking code.
"C" represents date code.
Tape Dimensions and Product Orientation
For Outline SOT-23
P
P
D
2
E
F
P
0
W
D
1
t1
Ko
13.5 MAX
8
MAX
9
MAX
B
A
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
D
3.15 0.10
2.77 0.10
1.22 0.10
4.00 0.10
1.00 + 0.05
0.124 0.004
0.109 0.004
0.048 0.004
0.157 0.004
0.039 0.002
0
0
0
BOTTOM HOLE DIAMETER
1
0
PERFORATION
CARRIER TAPE
DIAMETER
PITCH
POSITION
D
P
E
1.50 + 0.10
4.00 0.10
1.75 0.10
0.059 + 0.004
0.157 0.004
0.069 0.004
WIDTH
THICKNESS
W
t1
8.00+ 0.30 - 0.10 0.315+ 0.012 - 0.004
0.229 0.013
0.009 0.0005
DISTANCE
BETWEEN
CENTERLINE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
3.50 0.05
0.138 0.002
2.00 0.05
0.079 0.002
2
9
Tape Dimensions and Product Orientation
For Outlines SOT-323, -363
P
P
D
2
P
0
E
F
W
C
D
1
t
(CARRIER TAPE THICKNESS)
T (COVER TAPE THICKNESS)
t
1
K
An
An
0
A
B
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
D
2.40 0.10
2.40 0.10
1.20 0.10
4.00 0.10
1.00 + 0.25
0.0 4 0.004
0.0 4 0.004
0.04 0.004
0.15 0.004
0.0 + 0.010
0
0
0
BOTTOM HOLE DIAMETER
1
0
PERFORATION
DIAMETER
PITCH
POSITION
D
P
E
1.55 0.05
4.00 0.10
1. 5 0.10
0.0 1 0.002
0.15 0.004
0.0
0.004
CARRIER TAPE
COVER TAPE
DISTANCE
WIDTH
W
1
.00 0. 0
0. 15 0.012
0.0100 0.000
THICKNESS
t
0.254 0.02
WIDTH
TAPE THICKNESS
C
5.4 0.10
0.0 2 0.001
0.205 0.004
0.0025 0.00004
T
t
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
.50 0.05
0.1
0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
2.00 0.05
0.0
0.002
2
ANGLE
FOR SOT 2 (SC 0 LEAD)
FOR SOT (SC 0 LEAD)
An
°
C MA
°
10 C MA
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-4028EN
AV02-0293EN - October 21, 2013
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