AV3843A 概述
LINEAR INTEGRATED CIRCUIT 线性集成电路
AV3843A 数据手册
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PDF下载@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
CURRENT MODE PWM CONTROL
CIRCUITS
DESCRIPTION
SOP-8
The @vic AV3842A/3843A provide the necessary functions
to implement off-line or DC to DC fixed frequency current
mode , controlled switching circuits with a minimal external
part count
FEATURES
*Low external part count.
*Low start up current
( Typical 0.12mA )
*Automatic feed forward compensation
*Pulse-by-Pulse current limiting
*Under-voltage lockout with hysteresis
*Double pulse Suppression
DIP-8
*High current totem pole output to drive MOSFET directly
*Internally trimmed band gap reference
*500kHz operation
BLOCK DIAGRAM
7
5
7
Vcc
GND
Vcc
Vref
8
5V REF
S/R
Internal
Bias
U.V.L.O
Vref
Good
Logic
1/2Vref
CURRENT
SENSE
1/3Vref
COMPARATOR
VFB
COMP
2
1
3
R
1V
ERROR
AMPLIFIER
PWM
LATCH
6
5
OUTPUT
GND
S
CURRENT SENSE
RT/CT
4
OSCILLATOR
ABSOLUTE MAXIMUM RATINGS(Ta=25°C)
PARAMETER
Supply Voltage(Low Impedance Source)
Supply Voltage(Icc<30mA)
Output Current ( Peak )
SYMBOL
VALUE
30
UNIT
V
VCC
Vcc
Io
Self Limiting
V
+-1
A
Output Energy(capacity Load)
Analog Inputs(pin 2,3)
5
-0.3 ~ +6.3
10
µJ
V
VI(ANA)
ISINK(EA)
PD DIP-8
SOP-8
Error Amplifier Output Sink Current
Power Dissipation
mA
W
at Tamb<=25°C 1.0
at Tamb<=25°C 0.5
300
W
Lead Temperature( Soldering 10 Sec )
Tlead
°C
QW-R103-002,B
@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
(continued)
PARAMETER
Storage Temperature
SYMBOL
Tstg
VALUE
-65 ~ +150
+150
UNIT
°C
Operating junction temperature
Tj
°C
Note 1: Ta>25°C, PD derated with 8mW/°C.
ELECTRICAL CHARACTERISTICS (0°C <=Ta<=70°C,VCC=15V,RT=10kΩ,CT=3.3nF,unless otherwise
specified)
PARAMETER
Reference Section
Output Voltage
SYMBOL
TEST CONDITIONS
MIN
4.9
TYP MAX UNIT
VREF
∆VREF
∆VREF
5
6
6
5.1
20
25
0.4
5.18
V
mV
mV
mV/°C
V
Tj=25°C,Io=1mA
12<=VIN<=25V
1<=Io=20mA
Line Regulation
Load Regulation
Temperature Stability
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
Oscillator Section
Initial Accuracy
(Note 2)
0.2
Line, Load, Temp(note 2)
10Hz<=f<=10kHz,Tj=25°C (note 2)
Ta=25°C,1000Hrs(note 2)
4.82
Vosc
ISC
50
5
-100
uV
mV
mA
25
-180
-30
47
f
52
0.2
5
57
1
kHz
%
%
Tj=25°C
12<=Vcc<=25V
Tmin<=TA<=Tmax(note 2)
Vpin 4 peak to peak
Voltage Stability
Temperature Stability
Amplitude
∆f/∆Vcc
Vosc
1.7
V
Error Amplifier Section
Input Voltage
Input Bias Current
AVOL
Unity Gain Bandwidth
PSRR
Output Sink Current
Output Source Current
Vout High
VI(EA)
IBIAS
Vpin 1=2.5V
2.42
2.50
-0.3
90
1
70
6
-0.8
6
0.7
2.58
-2
V
µA
dB
MHz
dB
mA
mA
V
2 <=Vo<=4V
Tj=25°C (note 2)
I2<=Vcc<=25V
60
0.7
60
2
-0.5
5
Isink
Isource
VOH
Vpin 2=2.7V,Vpin 1=1.1V
Vpin 2=2.3V,Vpin 1=5V
Vpin 2=2.3V, RL=15kΩ to GND
Vpin 2=2.7V,Vpin 1=1.1V
Vout Low
VOL
1.1
V
Current Sense section
Gain
Maximum Input signal
PSRR
Input Bias Current
Delay to Output
GV
VI(MAX)
(note 3,4)
Vpin 1=5V( note 3)
12<=Vcc<=25V
2.85
0.9
3
1
70
-2
3.15
1.1
V/V
V
dB
µA
ns
IBIAS
-10
300
Vpin 3=0 to 2V
150
Output Section
Output Low Level
VOL
VOH
Isink=20mA
Isink=200mA
Isource=20mA
0.1
1.5
13.5
13.5
50
0.4
2.2
V
V
V
V
ns
ns
Output High Level
13
12
Isource=200mA
Tj=25°C,CL=1nF(note 2)
Tj=25°C,CL=1nF(note 2)
Rise Time
Fall Time
tR
tF
150
150
50
Under-Voltage Lockout Output Section
Start Threshold
VTH(ST)
UTC3842A
UTC3843A
After Turn On
UTC3842A
UTC3843A
14.5
7.8
8.5
16
8.4
10
17.5
9
11.5
V
V
Min. Operating Voltage
VOPR(min)
7
7.6
8.2
V
PWM Section
QW-R103-002,B
@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
PARAMETER
Maximum Duty Cycle
Minimum Duty Cycle
SYMBOL
D(MAX)
D(MIN)
TEST CONDITIONS
MIN
95
TYP MAX UNIT
97
100
0
%
%
Total Standby Current
Start-up Current
Operating Supply Current
Vcc Zener Voltage
IST
ICC(opr)
Vz
0.12
11
34
0.3
17
mA
mA
V
Vpin 2=Vpin 3=0V
Icc=25mA
note 2:These parameters, although guaranteed ,are not 100% tested in production.
note 3:Parameters measured at trip point of latch with Vpin 2=0.
note 4:Gain defined as:
∆
∆
Vpin 1
Vpin 3
A=
; 0<=Vpin3<=0.8V
note 5:Adjust Vcc above the start threshold before setting at 15V.
OPEN-LOOP LABORATORY TEST FIXTURE
Vref
Vcc
RT
1
2
3
8
7
6
5
A
Error Amp
Adjust
1k
/ 1W
Ω
OUTPUT
5kΩ
4
CT
High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used
to sample the oscillator waveform and apply an adjustable Ramp to Pin 3.
UNDER-VOLTAGE LOCKOUT
Icc
<15mA
Vcc
ON/OFF Command
to rest of IC
7
Von=16V
Voff=10V
<1mA
Voff
Von
Vcc
During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to
GND with a bleeder resistor to prevent activating the power switch with output leakage currents.
QW-R103-002,B
@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
ERROR AMPLIFIER CONFIGURATION
2.5V
0.5mA
Zi
2
1
Zf
Error amplifier can source or sink up to 0.5mA
CURRENT SENSE CIRCUIT
Error
Amplifier
2R
Is
R
1V
1
3
5
Current Sense
Comparator
R
Rs
C
Peak current (Is) determined by the formula:
Ismax=10V/Rs.
A small RC filter be required to suppress switch transients.
SLOPE COMPENSATION
8
RT
4
3
CT
R1
Isense
R2
Rsense
C
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converts requiring duty cycles over 50%.Note that capacitor C, forms a filter with R2 to suppress
the leading edge switch spikes.
QW-R103-002,B
@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
OSCILLATOR SECTION
V4
Large RT
Small CT
8
INTERNAL
RT
CT
CLOCK
4
5
V4
Small RT
Large CT
INTERNAL
CLOCK
Dead time VS CT(RT>5kΩ)
Timing Resistance Vs Frequency
100
100
CT=1nF
td (µs)
RT (kΩ)
CT=2.2nF
10
CT=4.7nF
CT=10nF
CT=22nF
CT=47nF
CT=100nF
10
1
1
0.1
1
10
100
102
103
104
105
106
CT (nF)
Frequency (Hz)
SHUTDOWN TECHNIQUES
Shutdown
UTC
UC3842A
can
be
accomplished by two methods; either raise pin 3
above 1V or pull Pin 1 below a voltage two diode
drops above ground. Either method caused the
output of PWM comparator to be high(refer to
block diagram).The PWM latch is reset dominant
so that the output will remain low until the next
clock cycle after the shutdown condition at pins 1
1kΩ
1
8
3
Shutdown
and/or
3 is removed . In one example, an
Shutdown
To current
Sense resistor
externally latched shut –down may be
accomplished by adding an SCR which be reset
by cycling Vcc below the lower UVLO threshold.
At this point the reference turns off allowing the
SCR to reset.
QW-R103-002,B
@vic AV3842A / 3843A LINEAR INTEGRATED CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTICS
4
3
2
1
0
100
80
60
40
0
Vcc=15V
Ta=+25°C
Ta=-55°C
-45
-90
20
0
-135
-180
102
103
104
Frequency (Hz)
105
106
107
0.01
0.1
1
10
Output Current
(Sourse or Sink Current) (A)
Output Saturation Characteristics
Error Amplifier Open-Loop Frequency Response
Vref Temperature Drift
Istart Temperature Drift
5.02
Vref (V)
5.01
550
500
Vcc=15V
Io=1mA
Vcc=9V
5.00
4.99
450
400
4.98
350
4.97
4.96
300
250
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Icc Temperature Drift
15
Icc (mA)
14
Vcc=15V
Io=1mA
13
12
11
10
9
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
QW-R103-002,B
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