HV070WS1-105 [AZDISPLAYS]
color active matrix TFT LCD module; 彩色有源矩阵TFT液晶显示模块
| 型号： | HV070WS1-105 |
| 厂家： | 
AZ DISPLAYS |
| 描述： | color active matrix TFT LCD module |
| 文件： | 总34页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROPRIETARY NOTE
THIS SPECIFICATION IS THE PROPERTY OF HYDIS AND SHALL NOT BE
REPRODUCED OR COPIED WITHOUT THE WRITTEN PERMISSION OF
HYDIS AND MUST BE RETURNED TO HYDIS UPON ITS REQUEST
HYDIS Technologies
PAGE
TFT LCD
B
2012.12.20
1
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TFT LCD PRODUCT
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ISSUE DATE
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REVISION HISTORY
REV.
0
ECN NO.
DESCRIPTION OF CHANGES
DATE
PREPARED
J.H. Kim
. Initial Release
2012.04.10
. Add Line Classification on Module Label No.3
E1206-
F005
A
B
2012.06.25
2012.12.20
T.C.KANG
T.C.KANG
(TOC: T, IDS: C)
E1212-
F001
. Change Module Barcode Label
(QPN no. - AA070WS1008, MADE IN CHINA)
SPEC TITLE
HV070WS1-105 Product Specification
SPEC. NUMBER
S864-1470
PAGE
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2
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TFT LCD PRODUCT
REV
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2012.12.20
Contents
No
Item
Page
1.0
2.0
General Description
4
Absolute Maximum Ratings
Electrical Specifications
Optical Specifications
6
3.0
7
4.0
8
5.0
Interface Connections
13
16
16
19
19
26
27
28
30
31
32
34
6.0
Signal Timing Specifications
Signal Timing Waveforms
7.0
8.0
Input Signals, Basic Display Colors & Gray Scale of Colors
3-Wire Special Port Interface (SPI Interface)
Power Sequence
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
Mechanical Characteristics
Mechanical Drawing
Reliability Test
Handling & Cautions
Labels
Packing Information
SPEC TITLE
SPEC. NUMBER
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1.0 GENERAL DESCRIPTION
1.1 Introduction
HV070WS1-105 is a color active matrix TFT LCD module using amorphous silicon TFT's
(Thin Film Transistors) as an active switching devices. This module has a 7.01 inch
diagonally measured active area with WSVGA resolutions (1024 horizontal by 600 vertical
pixel array). Each pixel is divided into RED, GREEN, BLUE dots which are arranged in
vertical Stripe and this module can display 16.7M colors. The TFT-LCD panel used for this
module is a low reflection and higher color type.
DC/DC
Gamma
Vcom
VCC
VDD
LDO
Vendor[0]
Ground
VCC
TFT LCD Panel
Vendor[1]
1024 ×600
BL-PWM-IN
BL-PWM-OUT
Source Driver
LVDS Input Signal
Back Light (SMD LED Array)
CN2
LEDP & LEDN
1.2 Features
FAB site : Hydis Korea
Thin and Light Weight
3.3 V Logic Power & 16 V Back-light power Supply
1 Channel LVDS Interface
SMD LED (20EA) Array (Bottom Side/Horizontal Direction)
16.7M Colors (With Dither & HFRC)
Need SPI control (CSB, SCL, SDA) for module driving
Green Product (RoHS) & Halogen free
SPEC TITLE
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1.3 Application
E-book, etc
1.4 General Specifications
Parameter
< Table 1. General Specifications >
Specification
Unit
Remark
Active area
mm
pixels
mm
153.6(H) ×90.0(V)
Number of pixels
Pixel pitch
1024(H) ×600(V)
0.15(H) ×0.15(V)
Pixel arrangement RGB Vertical Stripe
Display colors
Display mode
Outline dimension
Weight
16.7M
colors Note 1
Normally Black
mm
g
Note 2
163.60.3(H)×102.90.3(V)× 2.470.2(D)
95 (Max.)
Back-light
Bottom edge side, 20-LEDs type
Note 1 : Support 16.7M with dither and HFRC
Note 2 : Without component
Horizontal outline dimension is some different to customer request which is
162.80.3(H)×102.90.3(V)× 2.470.2(D)
But outline dimension is confirm value between Hydis and Customer
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SPEC. NUMBER
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2.0 ABSOLUTE MAXIMUM RATINGS
The followings are maximum values which, if exceed, may cause faulty operation or
damage to the unit.
Ta=25+/-2°C
< Table 2. Absolute Maximum Ratings >
Parameter
Symbol
Min.
Max.
Unit
Remarks
Logic Power Supply Voltage
Back-light Power Supply Voltage
Back-light LED Current
VCC
VL
-0.3
-0.3
-
VCC+0.3
40
V
V
IL
30
mA
V
Note 1
Back-light LED Reverse Voltage
Operating Temperature
VR
TOP
TSP
-
5
-20
-40
+60
+70
℃
℃
Note 1,
Note 2
Storage Temperature
Note 1. Ambient temperature vs allowable forward current are shown in the figure below.
Note 2. Temperature and relative humidity range are shown in the figure below.
90% RH Max. ( 40℃ ≥ Ta)
Maximum wet - bulb temperature at 39℃ or less. ( > 40℃) No condensation.
Relative Humudity
100
(40, 90)
90
80
60
Operating Range
(50, 50)
40
(60, 27)
(70, 20)
20
5
Storage Range
-40
-20
0
20
40
60
80
Temperature (℃)
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3.0 ELECTRICAL SPECIFICATIONS
3.1 Electrical Specifications
< Table 3. Electrical Specifications >
Parameter
Logic Power Supply Voltage
Logic Power Supply Current
Logic Power Consumption
Min.
3.0
-
Typ.
3.3
Max.
3.6
Unit
Remarks
VCC
ICC
PC
VL
V
mA
W
220
0.73
16
270
0.89
17
Note 1
Back-light Power Supply Voltage
Back-light Power Supply Current
Back-light Power Consumption
-
-
-
V
Note 2
IL
20
25
mA
W
PBL
1.28
1.36
Note 2, 4
High Level Differential Input Signal
(VCM = 1.2V)
VTH
-
-
0.1
V
Low Level Differential Input Signal
Input voltage range (singled-end)
Differential input voltage
VTL
VIN
- 0.1
0
-
-
-
-
V
V
V
2.4
0.6
LVDS input
｜VID
VCM
VIN
｜
0.1
Differential input common mode
voltage
2.4-
(｜VID ｜/2)
(｜VID ｜/2)
V
Input Current
-10
50,000
-
-
-
-10
-
μA
Hrs
W
Panel unit life time
Total Power Consumption
Without BL,PCB
Note 1,2,4
Ptotal
2.01
2.25
Notes : 1. The supply voltage is measured and specified at the interface connector of LCM.
The logic current draw and power consumption specified is for 3.3V at 25℃.
a) Typ : Window XP pattern,
b) Max : White pattern
2. The supply voltage is measured and specified at the interface connector of LCM.
The Backlight current draw and power consumption specified is 16V at 25℃.
The voltage and current value means value for chain.
3. PWM frequency and voltage level is fixed by customer.
4. Backlight power consumption is calculated value for reference (VL× IL × 4 chains).
About maximum power of backlight is 17V × 20mA × 4 chains = 1.36W
SPEC TITLE
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4.0 OPTICAL SPECIFICATIONS
4.1 Overview
The test of optical specifications shall be measured in a dark room (ambient luminance 1
lux and temperature = 252℃) with the equipment of Luminance meter system (Goniometer
system and TOPCON BM-5A) and test unit shall be located at an approximate distance
50cm from the LCD surface at a viewing angle of θ and Φ equal to 0. We refer to θØ=0
(=θ3 ) as the 3 o’clock direction (the “right”), θØ=90 (= θ12 ) as the 12 o’clock direction
(“upward”), θØ=180 (= θ9 ) as the 9 o’clock direction (“left”) and θØ=270(= θ6 ) as the 6
o’clock direction (“bottom”). While scanning θ and/or Ø, the center of the measuring spot on
the Display surface shall stay fixed. VCC shall be 3.3+/- 0.3V at 25C.
4.2 Optical Specifications
<Table 4. Optical Specifications>
Parameter
Symbol Condition
Min.
Typ. Max.
Unit Remarks
Θ3
75
75
85
85
85
85
Deg.
Horizontal
Vertical
Θ9
Deg.
Viewing Angle
range
CR > 10
Θ12
Note 1
Deg.
75
Θ6
75
Deg.
Luminance Contrast ratio
CR
Θ = 0
Θ = 0
640
800
30
-
Note 2
cd/m2
Note 4
cd/m2
Luminance of
1 Points
Yw
White
340
72
400
-
-
White
Luminance
uniformity
9 Points
∆Y9
80
%
Note 5
Wx
Wy
Rx
Ry
Gx
Gy
Bx
0.280
0.310
0.563
0.323
0.283
0.559
0.121
0.099
0.301
0.330
0.593
0.353
0.313
0.589
0.151
0.129
0.340
0.370
0.623
0.383
0.343
0.619
0.181
0.159
White Chromaticity
Θ = 0
Θ = 0
Red
Note 3
Reproduction
of color
Green
Blue
By
Response
Total
(Tr + Td)
Ta= 25 C
Θ = 0
-
-
50
-
-
ms
%
Note 6
Note 7
Time
Cross Talk
CT
Θ = 0
2.0
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Notes :
1. Viewing angle is the angle at which the contrast ratio is greater than 10. The viewing
angles are determined for the horizontal or 3, 9 o’clock direction and the vertical or 6,
12 o’clock direction with respect to the optical axis which is normal to the LCD surface
(see Figure1).
2. Contrast measurements shall be made at viewing angle of Θ= 0 and at the center of
the LCD surface. Luminance shall be measured with all pixels in the view field set first
to white, then to the dark (black) state (see Figure1). Luminance Contrast Ratio (CR) is
defined mathematically as CR = Luminance when displaying a white raster / Luminance
when displaying a black raster.
3. Reference only / Standard Front Surface Treatment Measured with green cover glass.
The color chromaticity coordinates specified in Table 4 shall be calculated from the
spectral data measured with all pixels first in red, green, blue and white. Measurements
shall be made at the center of the panel.
4. The luminance value of 400 cd/m2 means the brightness of PWM is 100%. The
luminance value of 30 cd/m2 means the brightness of lower PWM. CTF means that
measure brightness at only center point at Figure 2.
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4.3 Optical Measurements
Figure 1. Measurement Set Up
Photo detector
(MINOLTA CA210)
TFT-LCD module
LCD panel
Center of the screen
Optical characteristics measurement setup
Figure 2. Uniformity Measurement Locations (9 points)
Column
34
512
990
Row
34
300
566
Note 5.
The White luminance uniformity on LCD surface is then expressed as :
∆Y = ( Minimum Luminance of 9 points / Maximum Luminance of 9 points ) * 100 Refer
Figure 2 about measurement points
* LED Condition = (Duty Ratio 100%, LED current 20mA)
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Figure 3. Response Time Testing
TFT Off(Black)
TFT On(White)
TFT Off(Black)
Td
Tr
100%
90%
10%
0%
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Figure 4. Cross Modulation Test Description
VIEW AREA
VIEW AREA
256,150
768,150
L31
YB(768, 300)
256,450
768,450
L256
YA (768, 300)
YB - YA
YB
Cross-Talk (%) =
× 100
Where:
YA = Initial luminance of measured area (cd/m2)
YB = Subsequent luminance of measured area (cd/m2)
The location measured will be exactly the same in both patterns
Note 6.
The electro-optical response time measurements shall be made as Figure 3 by
switching the “data” input signal ON and OFF. The times needed for the luminance
to change from 10% to 90% is Tr, and 90% to 10% is Td.
Note 7.
Cross-Talk of one area of the LCD surface by another shall be measured by
comparing the luminance (YA) of a 25mm diameter area, with all display pixels set
to a gray level, to the luminance (YB) of that same area when any adjacent area is
driven dark (Refer to Figure 4).
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5.0 INTERFACE CONNECTIONS
5.1 Electrical Interface Connection
CN1 Interface Connector (DF23C-30DS-0.5V(51), Manufacture by HIROSE)
<Table 5, Electrical Interface Connection >
Pin
No.
Pin
No.
Symbol
Function
Symbol
Function
1
2
VCC
GND
+3.3V Power Supply
Ground
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D1-IN-N
Vendor[1]
D1-IN-P
CSB
LDVS differential data input
Vendor distinguish pin 2
LDVS differential data input
Serial Communication Chip Select
Ground
3
VCC
+3.3V Power Supply
LVDS Clock input (Negative)
+3.3V Power Supply
LVDS Clock input (Positive)
Ground
4
CLK-IN-N
VCC
5
GND
6
CLK-IN-P
GND
SCL
Serial Communication Clock Input
LDVS differential data input
Serial Communication Data Input
LDVS differential data input
Ground
7
D2-IN-N
SDA
8
GND
Ground
9
LEDP
Power supply for LED [Anode]
LDVS differential data input
Power supply for LED [Cathode]
LDVS differential data input
Ground
D2-IN-P
GND
10
11
12
13
14
15
D0-IN-N
LEDN
GND
Ground
D0-IN-P
GND
BL-PWM-IN
D3-IN-N
BL-PWM-OUT
D3-IN-P
Brightness Control Signal
LDVS differential data input
Backlight Dimmer Signal
LDVS differential data input
GND
Ground
Vendor[0]
Vendor distinguish pin 1
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5.2 LVDS Interface
LVDS Transmitter : THC63LVDM83A
<Table 6, LVDS Interface >
AA01B-
Transmitter
Interface
Input
P030VA1
Remark
signal
Pin No
51
52
54
55
56
3
Pin No
System (Tx) TFT-LCD (Rx)
Pin No.
R0
R1
R2
48
47
OUT0-
OUT0+
D0-IN-N
D0-IN-P
10
12
R3
R4
R5
G0
4
G1
6
G2
7
G3
11
12
14
15
19
20
22
23
24
27
28
30
50
2
46
45
OUT1-
OUT1+
D1-IN-N
D1-IN-P
16
18
G4
G5
B0
B1
B2
B3
B4
42
41
OUT2-
OUT2+
D2-IN-N
D2-IN-P
22
24
B5
HSYNC
VSYNC
DE
R6
R7
G6
8
38
37
OUT3-
OUT3+
D3-IN-N
D3-IN-P
28
30
G7
10
16
18
25
B6
B7
Reserved
40
39
CLKOUT-
CLKOUT+
CLK-IN-N
CLK-IN-P
4
6
MCLK
31
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5.3 Back-light Interface
CN2 LED FPC Connector ( solder type )
<Table 7, LED FPC connection >
Pin No.
Symbol
Function
Remark
1
2
3
4
Anode1
LED Anode Power Supply
Typ. 16V
LED Cathode Power Supply
LED Cathode Power Supply
Cathode1
5.4 Data Input Format
(1023, 1) (1024, 1)
(1, 1) (2, 1)
R G B R G B
R G B R G B
1 Pixel = 3 Dots
R G B
R G B R G B
R G B R G B
(2, 600)
(1023, 600) (1024, 600)
(1, 600)
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6.0. SIGNAL TIMING SPECIFICATIONS
6.1 Timing specification at HV Mode (LVDS Transmitter Input)
<Table 8, Signal Timing >
Item
Symbol
-
Min.
Typ.
60
Max.
Unit
Hz
Frame Rate
40
73
Frame Period
T1
624
635
600
35
750
Lines
Lines
Lines
Clocks
Clocks
Clocks
MHz
Vertical Display Time
Vertical Blanking Time
1 Line Scanning Time
Horizontal Display Time
Horizontal Blanking Time
Clock Rate
T2
-
-
T3
-
1200
-
-
T4
1344
1024
320
51.2
1400
T5
-
-
T6
-
1/T7
40.8
63
7.0 SIGNAL TIMING WAVEFORMS
7.1 Vertical Input Timing Waveforms of Interface Signal
T1
VSD
T3
T2
HSD
DEN
…
…
…
…
…
7.2 Horizontal Input Timing Waveforms of Interface Signal
T4
HSD
T6
T5
T7
DCLK
DEN
…
…
…
…
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7.3 LVDS Rx Interface Timing Parameter
The specification of the LVDS Rx interface timing parameter
< Table 9, LVDS Rx Interface Timing Specification>
Item
Symbol
Min.
Typ.
19.53
0.0
Max.
Unit Remarks
CLKIN Period tRCIP
-
-
nsec
nsec
nsec
Input Data 0
Input Data 1
tRIP0
tRIP1
-0.4
+0.4
tRICP/7-0.4
tRICP/7
tRICP/7+0.4
Input Data 2
Input Data 3
Input Data 4
Input Data 5
Input Data 6
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
nsec
nsec
nsec
nsec
nsec
2 ×tRICP/7-0.4 2 ×tRICP/7 2 ×tRICP/7+0.4
3 ×tRICP/7-0.4 3 ×tRICP/7 3 ×tRICP/7+0.4
4 ×tRICP/7-0.4 4 ×tRICP/7 4 ×tRICP/7+0.4
5 ×tRICP/7-0.4 5 ×tRICP/7 5 ×tRICP/7+0.4
6 ×tRICP/7-0.4 6 ×tRICP/7 6 ×tRICP/7+0.4
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRIP1
tRIP0
RxINz +/-
Rx
Rx
Rx
Rx
Rx
Rx
Rx
Rx
Rx
Rx
Rx
* Z = 0, 1, 2
Vdiff=0[v]
Vdiff=0[v]
RxCLKIN+/-
tRCIP
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8.0 INPUT SIGNALS, BASIC DISPLAY COLORS & GRAY SCALE OF
COLORS
A total of 16.7M colors are displayed with dither & HFRC using 64 gray from 8bit input.
Data signal
Red data
Green data
Blue data
R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7
Colors & Gray Scale
Black
Blue
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
Green
Light Blue
Red
Basic
Colors
Purple
Yellow
White
Black
△
Darker
△
↓
↓
↓
↓
↓
↓
Gray Scale
of Red
▽
Brighter
▽
1
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
Red
Black
△
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
Darker
△
↓
↓
↓
↓
↓
↓
Gray Scale
of Green
▽
Brighter
▽
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
Green
Black
△
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
Darker
△
↓
↓
↓
↓
↓
↓
Gray Scale
of Blue
▽
Brighter
▽
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
↓
Blue
Black
△
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
Darker
△
Gray Scale
of
↓
↓
↓
↓
↓
↓
White &
Black
▽
Brighter
▽
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
↓
↓
↓
White
SPEC TITLE
SPEC. NUMBER
S864-1470
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ISSUE DATE
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9.0 3-WIRE SERIAL PORT INTERFACE (SPI INTERFACE)
This module use 3-wire serial port interface as function configuration and parameter setting
9.1 3-Wire command format
Next Transfer
Address[5:0]
W/R Hi-Z
Data[7:0]
Delay
CSB
SDA
D5
D4
D2
D1
D0
D8
D7
D6
D3
D11 D10 D9
D14 D13 D12
D14
D15
D15
SCL
Bit
Description
D15-D10
D9
Register Address [5:0]
W/R control bit. “0” for Write; “1” for Read
D9
Hi-z bit during read mode. Any data within this bits will be ignored during write Mode
Data for the W/R operation to the address indicated by Address phase
D7-D0
9.2 3-Wire Write format
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
0
D8
X
D7
D6
D5
D4
D3
D2
D1
D1
Register Address [5:0]
Data (Issued by external controller)
9.3 3-Wire Read format
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
1
D8
D7
D6
D5
D4
D3
D2
D1
D1
Hi-Z
Register Address [5:0]
Data (Issued by 3-wire engine)
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9.4 3-wire control register
9.4.1 R00 : System Control Register
Designation Address Description
DE/SYNC mode select.
MODE
DCKPOL
GRB
R0[0]
R0[1]
R0[2]
MODE = “0”, HSD/VSD mode.
MODE = “1”, DE mode. (Default)
DCLK polarity control bit
DCLKPOL = “0” : Data sampling at DCLK falling edge. (Default)
DCLKPOL = “1” : Data sampling at DCLK rising edge.
Global reset bit.
GRB=“0”, The controller is in reset state.
GRB=“1”, Normal operation. (Default)
Standby mode selection bit.
STBYB = “0”, Timing control, driver and DC-DC converter, are off,
and all outputs are High-Z.
STBYB = “1”, Normal operation. (Default)
STBYB
UPDN
SHLR
R0[3]
R0[4]
R0[5]
Gate Up or Down scan control.
UPDN = “0”, STV2 output vertical start pulse and UD pin output
Logical “0” to Gate driver. (Default)
UPDN = “1”, STV1 output vertical start pulse and UD pin output
Logical “1” to Gate driver. (Default)
Right/Left sequence control of source driver.
SHLR = “0”, Shift left : Last data = S1<-S2<-S3…<-S960 = First Data
SHLR = “1”, Shift left : Last data = S1->S2->S3…->S960 = Last Data
(Default)
-
R0[6]
R0[7]
Reserved
POWER enable.
PWR_EN = H, enable PWM, Charge pump and VCOM buffer.
PWR_EN
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9.4.2 R01 : System Control Register
Designation
Address
Description
R1[0]
Reserved
Display resolution selection.
RES[1:0] = “01”, for 1024(RGB)*768 display resolution.
(dual or cascade)
RES[1:0] = “00”, for 1024(RGB)*600 display resolution.
(dual or cascade) (Default)
RES[1:0]
R1[2:1]
RES[1:0] = “10”, for 800(RGB)*600 display resolution.
(dual or cascade)
RES[1:0] = “11”, for 800(RGB)*480 display resolution.
(dual or cascade) (601~936 channel disable)
Normal Operation / BIST pattern select.
BIST = H : BIST (DCLK input is not needed)
BIST = L : Normal Operation (Default)
BIST
R1[3]
R1[4]
Dithering function enable control.
DITHER = “1”, Enable internal dithering function.
DITHER
DITHER = “0”, Disable internal dithering function. (Default)
H-FRC selection
HFRC = H : H-FRC enable
HFRC = L : H-FRC disable (Default)
If DITHER = H and HFRC = L : enable only FRC/dithering function
If DITHER = L, disable dithering function
(H-FRC and FRC both disable)
HFRC
R1[5]
CABC H/W enable pin. Normally pull low.
When CABC_EN = “00”, CABC OFF. (Default mode)
When CABC_EN = “01”, User interface Image.
When CABC_EN = “10”, Still Picture.
CABC_EN[1:0]
R1[7:6]
When CABC_EN = “11”, Moving Image.
9.4.3 R02 : System Control Register
Designation
Address
Description
R2[5:0]
Reserved
Normally black or normally white setting.
NBW = H : Normally black
NBW = L : Normally white (Default)
NBW
BIST
R2[6]
R2[7]
Reserved
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9.4.4 R03 : Gate on sequence controller register
Designation
Address
Description
Gate on sequence select
SEL[0]
SEL[1]
Pin control function
1
1
0
SEL[1:0]
R3[1:0]
1
0
0
1
0
Z (Default)
Frame inverse or not select.
FRAME = “1”, Uniform
FRAME = “0”, Frame inverse (Default)
Frame
-
R3[2]
R3[7:3]
Reserved
9.4.5 R0E : test mode (1)
Designation
Address
Description
Enter test mode (1)
TEST_mode(1)
R0E[7:0]
TEST_mode = 8’h5F, enter
TEST_mode = other exit (Default)
9.4.6 R0F : test mode (2)
Designation
Address
Description
Enter test mode (2)
TEST_mode(2)
R0F[7:0]
TEST_mode = 8’hA4, enter
TEST_mode = other exit (Default)
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9.4.7 R0D : charging time control (3)
Designation
Address
Description
Inversion type select. Enter Test mode (1) and (2) first.
Then R0D setting will be active
OE_WIDTH
R0D[7:0]
TEST_mode = 8’h00, increase charge time
9.4.8 R02 : charge sharing control
Designation
Address
Description
Inversion type select. Enter Test mode (1) and (2) first.
Then R10 setting will be active
EQC_ADJ
R02[7:0]
EQC_ADJ = 8’h43, adjust charge sharing time
9.4.9 R0A : BIAS current control (5)
Designation
Address
Description
Inversion type select. Enter Test mode (1) and (2) first.
Then R10 setting will be active
BIAS_TRIG
R0A[7:0]
BIAS_TRIG = 8’h28, trigger bias reduction
9.4.10 R10 : inversion architecture
Designation
Address
Description
Inversion type select. Enter Test mode (1) and (2) first.
Then R10 setting will be active
2line / 1dot = 8’h41
INV
R10F[7:0]
1line / 1dot = 8’h01 (Default)
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ISSUE DATE
2012.12.20
9.4.11 R38 : PWM_DIV setting
Designation
Address Description
PWM Dimmer frequency step setting
R38[7:0] PWM_DIV[3:0] Register function
0x0C
0x1C
0x2C
0x3C
0x4C
0x5C
0x6C
0x7C
000
001
010
011
100
101
110
111
Don’t use.
1
2
3
4
5
6
7 (Default)
PWM Reference
Frequency (FOSC)
PWM_DIV[3:0] R38[7:0]
Real PWM Frequency of DIMO
FOSC
51.2MHz (Typical)
PWM Frequency =
256 x 128 x PWM_DIV[2:0]
In order in maintain the dimming frequency for brightness control
at different display resolution (typical 1024 x 600) at normal mode. We
will change default value of PWM_DIV to follow as table
Display Resolution Default value of PWM_DIV
RES[1:0] = “00”
RES[1:0] = “01”
RES[1:0] = “10”
RES[1:0] = “11”
111
111
110
100
Note : The R6 and R38 register will be available when the R0E and R0F register already had issued.
SPEC TITLE
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9.5 Recommend Register Setting (CABC Off mode)
Register write sequence : R00 (Reset) R00 (Into Standby mode) R01 (Enable FRC / Dither, CABC off)
R02 (Enable Normally Black) R0E (Enter Test mode (1)) R0F (Enter Test mode (2))
R0D (SDRRS on) R00 (Release standby mode)
If you don’t use register write sequence, it may cause faulty operation.
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
1
Setting
0x0029
0x0025
0x0430
0x0840
0x385F
0x3CA4
0X4041
0x3401
0x002D
Remark
R00
R00
R01
R02
R0E
R0F
R10
R0D
R00
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
2dot inv.
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
9.6 Recommend Register Setting (CABC on mode (Moving Picture)
Register write sequence : R00 (Reset) R00 (Into Standby mode) R01 (Enable FRC / Dither, CABC on)
R02 (Enable Normally Black) R0E (Enter Test mode (1)) R0F (Enter Test mode (2))
R0D (SDRRS on) R38 (PWM Frequency = 1.5KHz) R00 (Release standby mode)
If you don’t use register write sequence, it may cause faulty operation.
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
0
0
0
0
0
0
0
0
0
D8
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
1
0
0
0
0
D6
0
0
0
1
1
0
1
0
0
0
D5
1
1
1
0
0
1
0
0
0
1
D4
0
0
1
0
1
0
0
0
1
0
D3
1
0
0
0
1
0
0
0
1
1
D2
0
1
0
0
1
1
0
0
1
1
D1
0
0
0
0
1
0
0
0
0
0
D0
1
1
0
0
1
0
1
1
0
1
Setting
0x0029
0x0025
0x04F0
0x0840
0x385F
0x3CA4
0X4041
0x3401
0xE01C
0x002D
Remark
R00
R00
R01
R02
R0E
R0F
R10
R0D
R38
R00
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
0
2dot inv.
0
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
SPEC TITLE
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ISSUE DATE
2012.12.20
10.0 POWER SEQUENCE
To prevent a latch-up or DC operation of the LCD module, the power on/off sequence shall
be as shown in below
90%
10%
90%
Power Supply for LCD
VCC
10%
0V
T1
T5
T7
T6
T2
Valid Data
Interface Signal
Vi
(LVDS Signal of Transmitter)
0V
Initial 3-Wire Command
T3
T4
LED Power
OFF
OFF
LED ON
Value
Parameter
Min.
Unit
Remark
Typ.
Max.
10
T1
T2
T3
T4
T5
T6
T7
0.5
0
ms
ms
ms
ms
ms
ms
ms
16
200
200
0
3
400
Notes : 1. When the power supply VDD is 0V, Keep the level of input signals on the low or keep
high impedance.
2. Do not keep the interface signal high impedance when power is on.
3. Back Light must be turn on after power for logic and interface signal are valid.
SPEC TITLE
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11.0 MECHANICAL CHARACTERISTICS
11.1 Dimensional Requirements
Figure 5 & 6 (located in 12.0) shows mechanical outlines for the model
<Table9, Mechanical Characters >
Parameter
Active Area
Specification
153.60(H) X 90.00(V)
Unit
mm
Number of pixels
Pixel pitch
1024(H) X 600(V) (1 pixel = R + G + B dots)
0.15(H) X 0.15(V)
Pixel arrangement
Display colors
Display mode
Outline dimension
Weight
RGB Vertical stripe
16.7M
Normally Black
mm
g
163.60.3(H)×102.90.3(V)× 2.470.2(D)
95 (Max.)
Back-light
Edge side 20-LEDs type ( 5 X 4 Array)
11.2 Polarizer Hardness.
The surface of the LCD has an coating to reduce scratching.
11.3 Light Leakage
There shall not be visible light from the back-lighting system around the edges of the
screen as seen from a distance 50cm from the screen with an overhead light level of
150lux. The manufacture shall furnish limit samples of the panel showing the light leakage
acceptable.
SPEC TITLE
SPEC. NUMBER
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12.0 MECHANICAL DRAWING
Figure 5. TFT-LCD Module Outline Dimension (Front View)
SPEC TITLE
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A4(210 X 297)
Figure 6. TFT-LCD Module Outline Dimensions (Rear view)
PRODUCT GROUP
TFT LCD PRODUCT
REV
B
ISSUE DATE
2012.12.20
13.0 RELIABLITY TEST
The Reliability test items and its conditions are shown in below.
<Table10, Reliability Test>
No
Test Item
Conditions
1. Ta = 40℃/90% 24hr
2. Ta = 40℃/30% 24hr
3. Ta = 0℃ 24hr
Temperature and Humidity test
(Operation)
1
Temperature and Humidity Cycling
(Storage)
Ta = 85℃/90%RH (2H) ,-20℃(2H),Waypoint(25℃25%
RH turn off Humidity control) 12cycle. 144Hr
2
3
Ta = -40 C 85 C
(30min residence), 100 cycle
Thermal shock
4
5
Low temperature storage test
Ta = -40 C, 300 hrs
Ta = -20 C, 300hrs
Low Temperature Test (Operation)
Biased Humidity/Heat Soak Test
(Storage)
6
Ta = 85 C /85%, 300hr
7
8
9
Altitude storage
Hot Start Test
Cold Start Test
20000 ft/-40 C, 24hr
Ta = 85 C 1hr, power on/off per 5m, 5 time
Ta = -40 C 1hr, power on/off per 5m, 5 time
100 G, 6 ms, half sine wave(±X,±Y,±Z). Acceleration
measured shock table.
10
11
Mechanical shock
3.5 Grms, PSD =0.025g2/Hz, 5-500 Hz
15 minutes in all axes (X, Y, Z)
Mechanical Random vibration
1. 7 kgf deflection. Scribed edge side up
2. 4 kgf deflection. Scribed edge side down
12
13
4 Pt Bend Test
Ring on Ring Test
X kgf applied. Load rae:75mm/min
Screen: 150 pF, 330 Ohm, +/-15kV air, +/- 8 kV contact.
FPC: 100 pFm100 Ohm, +/-200V
14
15
ESD
10 points, 20times/pt
Functional Test
Page flip script, 2 m flips
Notes :
1. Except form over the conditions of the polarizer specifications.
2. ESD test condition is standard of customer system.
SPEC TITLE
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ISSUE DATE
2012.12.20
14.0 HANDLING & CAUTIONS
14.1 Cautions when taking out the module
Pick the pouch only, when taking out module from a shipping package.
14.2 Cautions for handling the module
As the electrostatic discharges may break the LCD module, handle the LCD module with
care. Peel a protection sheet off from the LCD panel surface as slowly as possible.
As the LCD panel and back - light element are made from fragile glass (epoxy) material,
impulse and pressure to the LCD module should be avoided.
As the surface of the polarizer is very soft and easily scratched, use a soft dry cloth
without chemicals for cleaning.
Do not pull the interface connector in or out while the LCD module is operating.
Put the module display side down on a flat horizontal plane.
Handle connectors and cables with care.
14.3 Cautions for the operation
When the module is operating, do not lose MCLK, DE signals. If any one of these signals
were lost, the LCD panel would be damaged.
Obey the supply voltage sequence. If wrong sequence is applied, the module would be
damaged.
14.4 Cautions for the atmosphere
Dew drop atmosphere should be avoided.
Do not store and/or operate the LCD module in a high temperature and/or humidity
atmosphere. Storage in an electro-conductive polymer packing pouch and under relatively
low temperature atmosphere is recommended.
14.5 Cautions for the module characteristics
Do not apply fixed pattern data signal to the LCD module at product aging.
Applying fixed pattern for a long time may cause image sticking.
14.6 Cautions for the digitizer assembly
When assembling FPC connector, do not flip connector past 90° due to possible damage
to connector.
When positioning digitizer underneath driver IC, do not lift driver IC past 90° due to
possible damage to drive IC pattern.
Please be warned that during assembly of digitizer, the opening or closing of FPC will
result in possible electrostatic discharge damage to the LED
14.7 Other cautions
Do not re-adjust variable resistor or switch etc.
When returning the module for repair or etc., Please pack the module not to be broken.
We recommend to use the original shipping packages.
SPEC TITLE
SPEC. NUMBER
S864-1470
PAGE
OF 34
HV070WS1-105 Product Specification
31
(3/3)
A4(210 X 297)
PRODUCT GROUP
TFT LCD PRODUCT
REV
B
ISSUE DATE
2012.12.20
15.0 LABELS
15.1 Product Label
HYDAA070WS10081133ZZZZ
HV070WS1-105
MADE IN CHINA
Customer Barcode
V V V
P P P P P P P P P P P
Y Y
W W
Z Z Z Z
01~03 : Vendor code
17~18 : Manufactured week
19~22 : Serial number (32 digit/alphabet)
04~14 : QPN
15~16 : Manufactured year
HYDIS Barcode
6
7
3
1
2
5
4
X X
X
X
X X
X
X X X X
X X X X X X
No 1. Control Number
No 2. Rank / Grade
No 5. Month (1, 2, 3,…, 9, X, Y, Z)
No 6. FG Code
No 3. Line Classification
No 7. Serial Number
(Hydis: H, TOC: T, IDS: C)
No 4. Year (5 : 2005, 6 : 2006, …)
SPEC TITLE
SPEC. NUMBER
S864-1470
PAGE
OF 34
HV070WS1-105 Product Specification
32
(3/3)
A4(210 X 297)
PRODUCT GROUP
TFT LCD PRODUCT
REV
B
ISSUE DATE
2012.12.20
15.2 Packing Label
Label Size: 108 mm (L) 56 mm (W)
Contents
Model: HV070WS1-105
Q`ty: Module Q`ty in one box
Serial No.: Box Serial No. See next figure for detail description.
Date: Packing Date
FG Code: FG Code of Product
MODEL : HV070WS1-105
Q’TY : 40
SERIAL NO. :
DATE : XXXX. XX. XX
FG CODE
RoHS Mark
SPEC TITLE
SPEC. NUMBER
S864-1470
PAGE
OF 34
HV070WS1-105 Product Specification
33
(3/3)
A4(210 X 297)
PRODUCT GROUP
TFT LCD PRODUCT
REV
B
ISSUE DATE
2012.12.20
16.0 PACKING INFORMATION
16.1 Packing order
Shield Bag
LCD Module
Bottom PAD
20EA Module per Inner-Box
Anti Static Packing BAG
Top PAD
Out Box
Cushion PAD
Packing Label
40EA Module per Inner-Box Assy
Notes : 1. Box Dimension: 350mm(W) X 265mm(D) X 320mm(H)
2. Package Quantity in one Box : 40pcs
SPEC TITLE
SPEC. NUMBER
S864-1470
PAGE
OF 34
HV070WS1-105 Product Specification
34
(3/3)
A4(210 X 297)
相关型号：
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