PD024OX8_技术文档

PD024OX8

Versionꢀ1.0

FOR MORE INFORMATION:

AZ DISPLAYS, INC.

75 COLUMBIA, ALISO VIEJO, CA, 92656

Http://www.AZDISPLAYS.com

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

1

PD024OX8

TECHNICAL SPECIFICATION

CONTENTS

NO.

ITEM

PAGE

-

Cover

Contents

1

2

3

4

-

1

2

3

4

Application

Features

Mechanical Specifications

Mechanical Drawing of TFT-LCD Module

5

6

7

8

Input / Output Terminals

Absolute Maximum Ratings

Electrical Characteristics

Pixel Arrangement

5

7

8

9

Display Color and Gary Scale Reference

Power On/Off Sequence

Register Description

AC Characteristics

9

10

11

12

13

14

15

10

12

21

24

32

35

Waveform

Optical Characteristics

Handling Cautions

16

17

Reliability Test

Packing Diagram

Revision History

36

37

39

-

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

2

PD024OX8

1. Application

This technical specification applies to a 2.36” color TFT-LCD panel.

This is designed for printer application and other electronic products which require high quality flat

panel display.

2. Features

. Pixel in delta configuration

. Enables an approximately 16,190,000 color display by approximate 8-bit function.

. Provide a 3-wire clock synchronous serial interface for various operation mode settings.

. Built-in TCON, and support serial RGB mode, YUV mode, CIR656 mode.

. Image reversion : Up/Down and Left/Right.

. Built-in control circuit for LED driving.

. Built-in power-save functions such as the stand-by mode.

. Built-in Vcom amplitude voltage output circuit.

3. Mechanical Specifications

Parameter

Screen Size

Display Format

Display colors

Active Area

Pixel Pitch

Pixel Configuration

Outline Dimension

Weight

Specifications

Unit

inch

dot

2.36 (diagonal)

J

160 ( RGB ) 234

262,144

J

mm

48.0(H) 35.685(V)

J

0.3(H) 0.1525 (V)

Delta

ꢀ

mm

g

55.20(W) 47.55 (V) 2.91(D)(typ.)

N

12 1.5

Back-light

Three LED

Surface Treatment

Display model

Anti – Glare

Normally white

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

3

PD024OX8

4. Mechanical Drawing of TFT-LCD Module

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

4

PD024OX8

5. Input / Output Terminals

FPC Down Connect , 40Pins , Pitch : 0.5 mm

PGND=GND=0V

Remark

Pin No

1

Symbol

VCOM

N/C

I/O

I

Description

Common electrode voltage

Note 5-1

2

-

3

4

5

6

7

8

9

VGL

C4P

C4N

VGH

FRP

VCAC

VSD

C3P

C3N

VDDA

C2P

C2N

VINT

C1P

C1N

PGND

PVDD

DRV

VLED

NC

I

Negative power supply for gate driver

Pins to connect capacitance for power circuitry

Positive power supply for gate driver

Frame polarity output for VCOM

Define the amplitude of the VCOM swing

C

I

O

C

I

C

I

C

I

C

I

O

I

-

I

Voltage for Source Driver and Reference Voltage

Pins to connect capacitance for power circuitry

Voltage for Source Driver and Reference Voltage

Pins to connect capacitance for power circuitry

Voltage for Source Driver and Reference Voltage

Pins to connect capacitance for power circuitry

Charge Pump Power GND

Charge Pump Power VDD

Gate signal for the power transistor of the boost converter

Supply voltage for LED backlight

-

Note 5-2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

Note 5-3

Note 5-4

FB

Main boost regulator feedback input

Digital power supply

Note 5-5

Note 5-3

VCC

GND

VCC

CS

SDA

SCL

HSYNC

VSYNC

DCLK

D7

Digital GND

Digital power supply

Serial interface chip select signal

Serial interface data input signal

Serial interface transmission clock

Horizontal sync input

Note 5-3

I

Vertical sync input

Clock input

Data input

D6

D5

D4

D3

D2

D1

D0

I

Data input

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

5

PD024OX8

Note 5-1: V_COM= +5.0 Vp-p. (Typ.)

Note 5-2: The external capacitor is required on those pins as following.

Cap No.

Pin name

Capacitor value.(µF) Recommand breakdown voltage

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C1P/C1N

C2P/C2N

C3P/C3N

C4P/C4N

VINT

1

16V

25V

16V

25V

16V

VGH

VGL

VDDA

VSD

VCAC

FRP

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

6

PD024OX8

Note 5-3: PVDD, VCC = +3.3 V (Typ.)

Note 5-4: Outputs the control signal of switching regulator for LED. Duty cycle varies according to

FB input voltage.

Note 5-5: Feedback signal of switching signal for LED. It controls DRV output duty cycle with 0.6V

input level sense.

6. Absolute Maximum Ratings

The followings are maximum values, which if exceeded, may cause faulty operation or damage to the

unit.

R

PGND=GND=0V , Ta = 25

Parameter

Power Supply Voltage

Symbol

Vcc

MIN.

-0.3

MAX. Unit Remark

7

V

PVDD

-0.3

-0.5

-0.3

-

Input Signal Voltage

Vcom

6.375

Vcc+0.3

30

V

Digital Input Voltage

Maximum clock frequency

VIN

V

Fmax

MHz

7. Electrical Characteristics

7-1 Operation condition

R

PGND=GND=0V , Ta = 25

Parameter

Symbol

Min.

Typ.

Max.

Unit

Remark

Supply Voltage for Source Driver

Vcc

PVDD

V_GH

V_GL

V_IH

V_IL

3.0

14.5

-10.5

0.7 V_CC

0

3.3

15.5

-9.5

-

3.6

16.5

-8.5

V_CC

0.3 V_CC

V_CC

0.3 V_CC

V

Supply Voltage for Gate Driver

V

Note 7-1

Digital input voltage

Digital output voltage

V_OH

V_OL

0.7 V_CC

0

AC Component

of V_COM

V_{COM AC}

V_{COM DC}

-

+5.0

1.5

-

V_P-P

V

V_COM

Note 7-2

Note 7-1: VGH and VGL supplied by internal setup-up circuit.

Note 7-2: PVI strongly suggests that the V_{COM DC}level shall be adjustable , and the adjustable level

range is 1.5$1V , every module’s V_{COM DC}level shall be carefully adjusted to show a best

image performance.

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

7

PD024OX8

7-2 Power consumption

Parameter

Symbol

V_LED

I_LED

Min TYP MAX Unit

Remark

I_LED= 20 mA

Note 7-3

Supply voltage of LED backlight

Supply current of LED backlight

Backlight Power Consumption

9.0

10.0 11.5

20

V

mA

mW

P_LED

180

200

230

Note 7-4

Note 7-3: LED B/L applied information, please refer to the appendix at the end.

Note 7-4: P_LEDV_LEDI_LED

=

*

VLED

GLED

Parameter

Symbol

Conditions

TYP. MAX. Unit

Remark

I

mA

mW

CC

5.5

15

68

7

20

90

V

CC

+3.3V

Supply current for IC driver

Total power consumption

PVDD

PVDD1 +3.3V

8. Pixel arrangement

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

8

PD024OX8

9. Display Color and Gray Scale Reference

Input Color Data

Color

Red

Green

Blue

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black

Red (255)

Green (255)

Basic Blue (255)

Colors Cyan

Magenta

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Yellow

White

Red (00)

Red (01)

Red (02)

Darker

>

Red

Green

Blue

> > > > > > > > > > > > > > > > > > > > > > > >

Brighter

Red (253)

Red (254)

Red (255)

Green (00)

Green (01)

Green (02)

Darker

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

>

> > > > > > > > > > > > > > > > > > > > > > > >

Brighter

Green (253)

Green (254)

Green (255)

Blue (00)

Blue (01)

Blue (02)

Darker

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

>

> > > > > > > > > > > > > > > > > > > > > > > >

Brighter

Blue (253)

Blue (254)

Blue (255)

0

1

0

1

0

1

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page

9

PD024OX8

10. Power On/Off Sequence

Specially take care that the large current may cause a permanent damage to the IC when voltage is

applied to the charge pump power supply in the condition that the logic power supply is floating.

Please refer to the following timing and command setting, concerning the power supply ON and the

power supply OFF.

VCC

Power on sequence timing diagram

VCC

Driver IC will write 3 VSYNC Black pattern to the LCD panel after STB mode.

Power off sequence timing diagram

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 10

PD024OX8

No DCLK

"ꢂ[EJ

Valid data

D4ꢀꢁꢂ5

Source output

Gate output

V_GL@ 0 V

During No DCLK , Hsync and Vsync can be stopped.

But in all other cases Hysnc and Vsync must be active.

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 11

PD024OX8

11.Register Description

Function Description

D15 D14 D13 D12 D11 D10 D9 D8

Register Address

D7

D6

D5

Data

[

D4

D3

D2

D1

D0

[

R00

R01

R02

R03

R04

R05

R06

R07

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

[

GRB

STB

DITB

[

SHDB

SHCB

reserved

SHL

[

reserved reserved reserved

reserved

reserved reserved

PALM

FPOL

PAL

DDL3

HDL3

[

UD

SEL1

DDL1

HOL1

VSCL1

[

SEL2

DDL2

HDL2

VSCL2

SEL0

DDL0

HDL0

VSCL0

[

DDL4

[

VDV 1

[

VDV 0

[

LPC1

[

LPC0

DCKS1 DCKS0

Register Description

Noteꢀ(1) D12 must be low.

(2) All the SPI register settings will active at the falling edge of the VSYNC except GRB

ꢁSTB and SEL42ꢀ05bits.

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 12

PD024OX8

11-1 Function Control Register (R00h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

GRB

1

STB

1

SHDB

0

SHCB

1

R00

0

[

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 13

PD024OX8

11-2 Function Control Register (R01h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

reserved reserved reserved

DITB

0

reserved

1

R01

0

1

0

1

0

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 14

PD024OX8

11-3 Function Control Register (R02h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

reserved

0

reserved reserved FPOL

[

UD

1

SHL

1

R02

0

1

0

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 15

PD024OX8

11-4 Function Control Register (R03h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

PALM

0

PAL

0

SEL2

0

SEL1

0

SEL0

0

R03

0

1

0

000.

Note : SEL [2:0] =000,010,011,101, only NTSC mode, no support PAL mode.

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 16

PD024OX8

11-5 Function Control Register (R04h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

DDL4

0

DDL3

0

DDL2

0

DDL1

0

DDL0

0

R04

1

0

Select the data delay timing, Default Setting=00000.

DDL4

0

DDL3

0

DDL2

0

DDL1

0

DDL0

0

Delay

Unit

0

1

0

1

0

1

0

2

0

1

3

0

1

0

4

0

1

0

1

5

0

1

0

6

0

1

7

0

1

0

8

0

1

0

1

9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

10

11

12

13

14

15

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

DCLK Period

1

0

1

0

1

0

1

0

1

0

1

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 17

PD024OX8

11-6 Function Control Register (R05h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

HDL3

0

HDL2

0

HOL1

0

HDL0

0

R05

1

0

1

0

[

Select the first active line delay timing, Default Setting=00000.

DDL3

DDL2

DDL1

DDL0

Delay

0

Unit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

-1

-2

-3

-4

-5

-6

-7

HSYNC.

Period.

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PD024OX8

11-7 Function Control Register (R06h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

Data

LPC1

0

D4

D3

D2

D1

D0

[

Register Address

[

VDV 1

0

VDV 0

0

LPC0

0

[

VSCL2

0

VSCL1 VSCL0

R06

1

0

1

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PD024OX8

11-8 Function Control Register (R07h)

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

[

Register Address

Data

[

DCKS1 DCKS0

[

R07

1

0

[

0

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 20

PD024OX8

12.AC Characteristics

12-1 Timing conditions

Parameter

Symbol

Thc

Twh

Th

Tvst

Tvhd

Thst

Thhd

Tdsu

Tdhd

Twv

Tv

Min.

-

1

Typ.

-

32

63.5

-

Max.

Unit

DCLK

Čs

ns

Th

1

-

67

-

Delay between Hsync and DCLK

Hysnc width

60

12

2

Hysnc period

Vsync setup time

Vsync hold time

Hsync setup time

Hsync hold time

Data set-up time

Data hold time

Vsync width for RGB mode

Vsync width for YUV mode

Vsync period NTSC

Vsync period PAL

-

4

6

5.5

-

1.5

-

1.5

262.5

312.5

0

Tv

-

Th

T_{HV_O}

-4

+4

DCLK

Th

Hsync to Vsync time for ODD field

Hsync to Vsync time for EVEN field

T_{HV_E}

0

0.5

-

Serial communication

Parameter

Symbol

Tsck

Tscw

Tssw

Tist

Tihd

Tcst

Tchd

Tcd

Min.

320

40

120

1

Typ.

Max.

Unit

ns

%

Čs

ns

Čs

-

50

-

60

-

Serial clock period

Serial clock duty cycle

Serial clock width

Serial data setup time

Serial data hold time

SPENB setup time

SPENB data hold time

Chip select distinguish

Delay between SPCK and Vsync

Tcv

1

-

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PD024OX8

12-2 Operating mode dependent AC characteristic

Serial RGB Mode, SEL42:05=40005

Parameter

DCLK frequency

DCLK period

Symbol

Fclk

Tcph

Tcw

Ths

Min.

Typ.

9.7

103

50

100

16

Max.

Unit

Mhz

ns

%Tcph

DCLK

Th

-

40

84

9

-

60

115

24

-

DCLK duty cycle

Delay from Hsync to 1,st data input

Delay from Vsync to 1,st data input

DRV output frequency

Tstv

[

-

303.1

KHz

12-3 Operating mode dependent AC characteristic

YUV Mode, SEL42:05=4011~1105

Parameter

DCLK frequency

DCLK period

Symbol

Fclk

Tcph

Tcw

Min.

Typ.

24.54/27

40.7/37

50

Max.

Unit

Mhz

ns

-

40

-

60

%Tcph

DCLK duty cycle

Delay from Vsync to 1,st data input

Tstv

[

13

16

20

-

20

23

27

28

31

35

-

Th

(NTSC)

Delay from Vsync to 1,st data input

(PAL 288Lines)

Delay from Vsync to 1,st data input

(PAL280Lines)

Th

383.4/

421.9

DRV output frequency

KHz

12-4 Operating mode dependent AC characteristic

CCIR656 Mode,SEL42:05=41115

Parameter

Symbol

Fclk

Tcph

Tcw

Min.

Typ.

27

37

Max.

Unit

Mhz

ns

-

40

-

60

DCLK frequency

DCLK period

DCLK duty cycle

50

%Tcph

Delay from V to 1,st data input

Tstv

18

20

25

27

33

35

Th

(NTSC)

Delay from V to 1,st data input

(PAL 288Lines)

Delay from V to 1,st data input

Tstv

-

24

-

31

39

-

Th

(PAL280Lines)

DRV output frequency

421.9

KHz

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 22

PD024OX8

12-5 Operating mode dependent AC characteristic

CCIR656 Mode,SEL42:05=40105

Parameter

DCLK frequency

DCLK period

DCLK duty cycle

Delay form V to 1, st data input (NTSC)

DRV output frequency

Symbol

Fclk

Tcph

Tcw

Tstv

-

Min.

Typ.

24.54

40.7

50

Max.

Unit

Mhz

ns

%Tcph

Th

-

40

18

-

60

33

-

25

383.4

KHz

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 23

PD024OX8

13.Waveform

13-1 Timing formatꢀSerial communication timing

SPI Timing Diagram

T_CV

T_CST

T_CD

T_CHD

T_IHD

T_IST

T_SSWT_SSW

T_SCK

SPI Timing Diagram V.S. Vsync

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 24

PD024OX8

13-2 Clock and Data Input Timing Diagram

Tcwh

Tcwl

70%

30%

70%

Last

Tdsu Tdhd

70%

30%

70%

Tvst

Tvhd

30%

Thhd

30%

Th

Thst

70%

Last

Thc

30%

Clock and Data Input Timing Diagram

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 25

PD024OX8

13-3 Input Data Format Timing

13-3-1 Serial RGB Data Format

Serial RGB Mode Horizontal Timing

T_d

T_h

T_WH

ODD Line Data

Invalid data

SWD=000

ODD Line Data

SWD=000

Invalid data

480T_d

T_HS

Serial RGB Mode Vertical Timing – NTSC

ODD Field = Tv

T_WV

T_STV

D[7ꢁ0]

EVEN Field = Tv

T_WV

T_STV

D[7ꢁ0]

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 26

PD024OX8

13-3-2 YUV mode Data Format

YUV mode A Horizontal timing – 24.54MHz

Th

T_WH

HSYNC

DCLK

D[7ꢀ0]

Td

Cb320

Y639

Cr320

Y640

Invalid data

Cb1 Y1 Cr1 Y2

1280Td

1440Td

1280Td

YUV mode A Horizontal timing – 27MHz

Th

HSYNC

DCLK

D[7ꢀ0]

T_WH

Td

Cb1 Y1 Cr1 Y2

Cb360

Y719

Cr360

Y720

Invalid data

YUV mode B Horizontal timing – 24.54MHz

Th

T_WH

HSYNC

DCLK

D[7ꢀ0]

Td

Invalid data

Cr320

Y639

Cb320 Y640

Cr1 Y1 Cb1 Y2

YUV mode B Horizontal timing – 27MHz

Th

T_WH

HSYNC

DCLK

D[7ꢀ0]

Td

Cr360

Y719 Cb360

Y720

Invalid data

Cr1 Y1 Cb1 Y2

1440Td

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 27

PD024OX8

YUV Mode Vertical Timing 24.54MHz & 27MHz - NTSC

EVEN field

ODD field = Tv

Line20 Line21 Line22 Line23 Line24 Line25 Line26

Line1 Line2 Line3

Line4 Line5 Line6 Line7

Line261 Line262

VSYNC

HSYNC

D[7ꢀ0]

DL239 DL240

DL1

DL2

DL3

DL4

T_STV

ODD field

EVEN field = Tv

Line264 Line265 Line266 Line267 L ine268 Line269 Line270

Line283 Line284 Line285 Line286 Line287 Line288 Line289

Line524 Line525

VSYNC

HSYNC

D[7ꢀ0]

DL239 DL240

DL1

DL2

DL3

DL4

T_STV+1

YUV Mode Vertical Timing 27MHz – PAL 288Lines

EVEN field

ODD field = Tv

Line20 Line21 Line22 Line23 Line24 Line25 Line26

Line1 Line2 Line3

Line4 Line5 Line6 Line7

Line309 Line310

VSYNC

HSYNC

T_STV

D[7ꢀ0]

DL287 DL288

DL1

DL2

DL3

DL4

EVEN field = Tv

ODD field

Line313 Line314 Line315 Line316 L ine317 Line318 Line319

Line333 Line334 Line335 Line336 Line33 7 Line338 Line339

Line622 Line623

VSYNC

HSYNC

T_STV+1

D[7ꢀ0]

DL287 DL288

DL1

DL2

DL3

DL4

YUV Mode Vertical Timing 27MHz – PAL 280Lines

EVEN field

ODD field = Tv

Line24 Line25 Line26 Line27 Line28 Line29 Line30

Line305 Line306

Line1 Line2 Line3

Line4 Line5 Line6 Line7

VSYNC

HSYNC

D[7ꢀ0]

T_STV

DL279 DL280

DL1

DL2

DL3

DL4

EVEN field = Tv

ODD field

Line313 Line314 Line315 Line316 L ine317 Line318 Line319

Line33 7 Line338 Line339 Line340 Line341 Line342 Line343

Line618 Line619

VSYNC

HSYNC

D[7ꢀ0]

T_STV+1

DL279 DL280

DL1

DL2

DL3

DL4

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 28

PD024OX8

13-3-3 CCIR656 Data Format

CCIR656 27MHz , NTSC

Td

DCLK

D[7ꢀ0]

FF

00

EAV

Invalid Data

FF

00

SAV Cb1

Y1 Cr1 Y2

Cb360 Y719 Cr360 Y720 FF

00

00 EAV

Invalid Data

276Td

720 CCIR encoded data(1440Td)

Th=1716Td

CCIR656 27MHz , PAL

Td

DCLK

D[7ꢀ0]

FF

00

EAV

Invalid Data

00 EAV

Invalid Data

288Td

FF

00

SAV Cb1

Y1 Cr1 Y2

Cb360 Y719 Cr360 Y720 FF

00

720 CCIR encoded data(1440Td)

Th=1728Td

CCIR656 24.54MHz , NTSC

Td

DCLK

D[7ꢀ0]

Invalid Data

FF

00

EAV

Invalid Data

280Td

FF

00

SAV Cb1

Y1 Cr1 Y2

Cb320 Y639 Cr320 Y640 FF

00

00 EAV

640 CCIR encoded data(1280Td)

Th=1560Td

DL238 DL239 DL240

DL1 DL2

DL3 DL4

DL239 DL240

DL1 DL2

DL3 DL4

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 29

PD024OX8

D[7ꢀ0]

DL283 DL284 DL285 DL286 DL287 DL288

DL1 DL2 DL3 DL4 DL5 DL6 DL7 DL8

T_STV

D[7ꢀ0]

DL283 DL284 DL285 DL286 DL287 DL288

T_STV+ 1

DL1 DL2 DL3 DL4 DL5 DL6 DL7

DL278 DL280

D[7ꢀ0]

T_STV

DL1 DL2 DL3 DL4

T_STV+ 1

D[7ꢀ0]

DL1 DL2 DL3

DL279 DL280

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 30

PD024OX8

13-4 The HSYNC & VSYNC timing of the ODD/EVEN field

Define the HSYNC to VSYNC timing for serial RGB mode

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 31

PD024OX8

14.Optical Characteristics

14-1 Specification

R

Ta = 25

Parameter

Symbol

Condition

MIN. TYP. MAX. Unit Remarks

Horizontal

Ĉ

45

30

10

50

35

15

---

deg

21,

Ĉ

22

Viewing

"

CR 10

Note 14-1

Note 14-2

11

12

Angle

Vertical

At optimized

Viewing angle

Contrast Ratio

Response time

Uniformity

CR

---

200 400

Rise

Fall

Tr

Tf

U

---

70

6

15

75

12

30

---

ms

%

Ĉ

#

Note 14-3

Note 14-4

=0

---

Ĉ=0#

cd/\ Note 14-5

L

X

Y

200 250

Brightness

White

Chromaticity

Ĉ

#

0.28 0.31 0.34

0.30 0.33 0.36

--- 10000 ---

=0

Note 14-5

LED Life Time

---

hrs Note 14-6

Note 14-1 : The definitions of viewing angles

Luminance when Testing point is White

Luminance when Testing point is Black

Note 14-2 : CR

Contrast ratio is measured in optimum common electrode voltage.

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 32

PD024OX8

Note 14-3 : The definition of response time :

White

Black

White

100%

90%

10%

0%

Tr

Tf

Note 14-4 : The uniformity of LCD is defined as

The Minimum Brightness of the 9 testing Points

U =

The Maximum Brightness of the 9 testing Points

Luminance meter : BM-7 fast (TOPCON)

Measurement distance : 500 mm +/- 50 mm

Ambient illumination : < 1 Lux

Measuring direction : Perpendicular to the surface of module

The test pattern is white

1/6

2/6

1/6

2/6

1/6

Note 14-5 : Topcon BM-7(fast) luminance meter 1.0# field of view is used in the testing (use PVI

backlight after 5 minutes operating), ILED = 20mA.

Note 14-6 : Constant current 20mA for each loop , and the center brightness must more than 50% of

initial brightness value .

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 33

PD024OX8

14-2 Testing configuration

BM-7(fast)

!

Caution: 1. Environmental illumination 1 lux

2. Before test CR, Vcom voltage must

be adjusted carefully to get the best

CR.

500mm

input

R,G,B signal

LCD

Backlight

Pattern

generator

ꢀ

LCD Display

Testing Point

Pattern A

R, G, B Waveform of Pattern A at Testing Point

Pattern B

RGB

waveform

Vcom

Č

63.6

s

63.6

s

Vw=1.3V +/- 0.2V

R, G, B Waveform of Pattern B at Testing Point

RGB

waveform

Vcom

Č

63.6

s

63.6

s

Vb=5.0V +/- 0.2V

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 34

PD024OX8

15. Handling Cautions

15-1) Mounting of module

a) Please power off the module when you connect the input/output connector.

b) Please connect the ground surely. If the connection is not perfect, some following problems

may happen possibly.

1.The noise from the backlight unit will increase.

2.In some cases a part of module will heat.

c) Polarizer which is made of soft material and susceptible to flaw must be handled carefully.

d) Protective film (Laminator) is applied on surface to protect it against scratches and dirt. It is

recommended to peel off the laminator before use and taking care of static electricity.

15-2) Precautions in mounting

a) Wipe off water drops or finger grease immediately. Long contact with water may cause

discoloration or spots.

b) TFT-LCD module uses glass which breaks or cracks easily if dropped or bumped on hard

surface. Please handle with care.

c) Since CMOS LSI is used in the module. So take care of static electricity and earth yourself

when handling.

15-3) Others

a) Do not expose the module to direct sunlight or intensive ultraviolet rays for many hours.

b) Store the module at a room temperature place.

c) The voltage of beginning electric discharge may over the normal voltage because of

leakage current from approach conductor by to draw lump read lead line around.

d) If LCD panel breaks, it is possibly that the liquid crystal escapes from the panel.

Avoid putting it into eyes or mouth. When liquid crystal sticks on hands, clothes or feet.

Wash it out immediately with soap.

e) Observe all other precautionary requirements in handling general electronic components.

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 35

PD024OX8

16. Reliability Test

No.

Test Item

Test Condition

Ta = +70R , 240 hrs

Ta = -20R , 240 hrs

Ta = +60R , 240 hrs

Ta = 0R , 240 hrs

1

2

3

4

High Temperature Storage Test

Low Temperature Storage Test

High Temperature Operation Test

Low Temperature Operation Test

High Temperature & High Humidity

Operation Test

Ta = +60R , 90%RH , 240 hrs

-20R @ +70R, 200 Cycles

5

6

Thermal Cycling Test

(non-operating)

30 min

Frequency : 10 ~ 55 H_Z

Amplitude : 1.0 mm

Sweep time : 11 mins

Vibration Test

(non-operating)

7

Test Period : 6 Cycles for each direction of X, Y, Z

100G , 6ms

Shock Test

(non-operating)

Direction : $X , $Y , $Z

8

9

Cycle : 3 times

200pF , 0Ā $200V

1 time / each terminal

Electrostatic Discharge Test

(non-operating)

Ta: ambient temperature

Note : The protective film must be removed before temperature test.

[Criteria]

1. Main LCD should normally work under the normally condition no defect of function,

screen quality and appearance. (including : mura ,line defect ,no image)

2. After the temperature and humidity test, the luminance and CR (Contrast ratio), should not

be lower than minimum of specification.

3. After the vibration and shock test, can’t be found chip broken.

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reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 36

PD024OX8

17. Packing Diagram

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 37

PD024OX8

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 38

PD024OX8

Revision History

Rev. Issued Date Revised Contents

1.0 June. 7, 2006 New

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page 39


型号：	PD024OX8
厂家：	AZ DISPLAYS
描述：	TECHNICAL SPECIFICATION 技术规格
文件：	总39页 (文件大小：2042K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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