ADC71BG [BB]
16-Bit ANALOG-TO-DIGITAL CONVERTER; 16位模拟数字转换器
| 型号： | ADC71BG |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总9页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADC71
16-Bit
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADC71 is a low cost, high quality, 16-bit succes-
sive approximation analog-to-digital converter. It uses
laser-trimmed ICs and is packaged in a convenient
32-pin hermetic ceramic dual-in-line package. The
converter is complete with internal reference, clock,
comparator, and thin-film scaling resistors, which
allow selection of analog input ranges of ±2.5V, ±5V,
±10V, 0 to +5V, 0 to +10V and 0 to +20V.
● 16-BIT RESOLUTION
● ±0.003% MAXIMUM NONLINEARITY
● COMPACT DESIGN: 32-pin Hermetic
Ceramic Package
● CONVERSION SPEED: 50µs max
Data is available in parallel and serial form with
corresponding clock and status output. All digital in-
puts and outputs are TTL-compatible.
Power supply voltages are ±15VDC and +5VDC.
Reference
Ref Out (+6.3V)
Parallel
Digital
Output
16-Bit D/A
Converter
16-Bit
Short Cycle
Successive Approx.
Register (SAR)
Convert Command
Input Range
Select
}
Comparator In
Clock Out
Status
Clock
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1990 Burr-Brown Corporation
PDS-1060A
Printed in U.S.A. December, 1993
SPECIFICATIONS
ELECTRICAL
At +25°C and rated power supplies, unless otherwise noted.
ADC71J, K
TYP
ADC71A, B
TYP
MODEL
MIN
MAX
MIN
MAX
UNITS
RESOLUTION
16
16
Bits
INPUTS
ANALOG
Voltage Ranges: Bipolar
Unipolar
±2.5, ±5, ±10
0 to +5, 0 to +10,
0 to +20
±2.5, ±5, ±10
0 to +5, 0 to +10,
0 to +20
V
V
Input Impedance (Direct Input)
0 to +5V, ±2.5V
0 to +10V, ±5.0V
2.5
5
10
2.5
5
10
kΩ
kΩ
kΩ
0 to +20V, ±10V
DIGITAL(1)
Convert Command Positive pulse 50ns wide (min) trailing edge (“1” to “0” initiates conversion)
1
Logic Loading
TTL Load
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error(2)
Offset(2): Unipolar
Bipolar
Linearity Error: K, B
J, A
Inherent Quantization Error
Differential Linearity Error
±0.1
±0.05
±0.1
±0.2
±0.1
±0.2
±0.003
±0.006
±0.1
±0.05
±0.1
±0.2
±0.1
±0.2
±0.003
±0.006
%
% of FSR(3)
% of FSR
% of FSR
% of FSR
LSB
±1/2
±0.003
±1/2
±0.003
% of FSR
POWER SUPPLY SENSITIVITY
±15VDC
+5VDC
0.003
0.001
0.003
0.001
% of FSR/%VS
% of FSR/%VS
CONVERSION TIME(4)
14 Bits
50
50
µs
WARM-UP TIME
5
*
min
DRIFT
Gain
Offset: Unipolar
Bipolar
±10
±2
±8
±15
±4
±10
±3
*
*
±2
±10
±2
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
±5
Linearity
±2
No Missing Codes Temp Range
J, A (13 Bits)
K, B (14 Bits)
0
0
+70
+70
–25
–25
+85
+85
°C
°C
OUTPUT
DIGITAL DATA
(All Codes Complementary)
Parallel Output Codes(5): Unipolar
Bipolar
CSB
COB, CTC(6)
Output Drive
Serial Data Code (NRZ)
Output Drive
2
2
*
*
TTL Loads
TTL Loads
CSB, COB
Status
Logic “1” During Conversion
Status Output Drive
Clock Output Drive
Frequency(7)
2
2
2
2
TTL Loads
TTL Loads
kHz
280
6.3
*
INTERNAL REFERENCE VOLTAGE
Max External Current with
No Degradation of Specs
Temp Coefficient
6.0
6.6
6.0
6.3
6.6
V
±200
±10
±200
*
µA
ppm/°C
POWER SUPPLY REQUIREMENTS
Power Consumption
655
±15
+5
+10
–28
+17
655
mW
VDC
VDC
mA
mA
mA
Rated Voltage, Analog
Rated Voltage, Digital
Supply Drain +15VDC
Supply Drain –15VDC
Supply Drain +5VDC
±11.4
+4.75
±16
+4.75
+15
–35
+20
*
*
*
*
*
*
*
*
*
*
*
*
TEMPERATURE RANGE
Specification
Operating (Derated Specs)
Storage
0
–25
–55
+70
+85
+125
–25
–55
–55
+85
+125
+125
°C
°C
°C
NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = +0.4V, max Logic “1” = 2.4V min.
(2) Adjustable to zero. (3) FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. (4) Conversion time may be shortened with
“Short Cycle” set for lower resolution, see “Additional Connections Required” section. (5) See Table I. CSB = Complementary Straight Binary. COB = Complementary
Offset Binary. CTC = Complementary Two’s Complement. (6) CTC coding obtained by inverting MSB (Pin 1).
®
ADC71
2
PIN CONFIGURATION
Top View
DIP
(MSB) Bit 1
Bit 2
1
2
3
4
5
6
7
8
9
32 Short Cycle
31 Convert Command
30 +5VDC Supply
29 Gain Adjust
28 +15VDC Supply
27 Comparator In
26 Bipolar Offset
25 10V
Bit 3
Reference
Bit 4
Bit 5
Bit 6
6.3kΩ
Bit 7
Bit 8
5kΩ 5kΩ
Bit 9
24 20V
Bit 10 10
Bit 11 11
Bit 12 12
23 Ref Out 6.3V
22 Analog Common(1)
21 –15VDC Supply
20 Clock Out
(LSB for 13 bits) Bit 13 13
(LSB for 14 bits) Bit 14 14
Bit 15 15
19 Digital Common
18 Status
Comparator
Clock
Bit 16 16
17 Serial Out
NOTE: (1) Metal lid of package is connected to pin 22 (Analog Common).
ABSOLUTE MAXIMUM SPECIFICATIONS
PACKAGE INFORMATION
+VCC to Common.................................................................... 0 to +16.5V
–VCC to Common .................................................................. 0V to –16.5V
+VDD to Common....................................................................... 0V to +7V
Analog Common to Digital Common ............................................... ±0.5V
Logic Inputs to Common ........................................................... 0V to VDD
Maximum Power Dissipation ....................................................... 1000mW
Lead Temperature (10s) .................................................................. 300°C
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
ADC71JG
ADC71KG
ADC71AG
ADC71BG
32-Pin Hermetic DIP
32-Pin Hermetic DIP
32-Pin Hermetic DIP
32-Pin Hermetic DIP
172-5
172-5
172-5
172-5
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
MODEL
TEMPERATURE RANGE
NONLINEARITY
ADC71JG
ADC71KG
ADC71AG
ADC71BG
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
±0.006% FSR
±0.003% FSR
±0.006% FSR
±0.003% FSR
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADC71
Maximum Throughput Time(2)
Conversion Time
Convert Command(1)
Internal Clock
Status (EOC)
MBS
“0”
Bit 2
“1”
Bit 3
Bit 4
Bit 5
“1”
“0”
“0”
Bit 6
Bit 7
Bit 8
“1”
“1”
“1”
“0”
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
“1”
“1”
“0”
“1”
“0”
Bit 14
Bit 15
“0”
Bit 16
LSB
15
MSB
1
“1”
16
3
4
8
11
“1”
12
“0”
14
“0”
Serial Data Out
2
5
7
10
“1”
13
“1”
9
6
“1”
“1”
“1”
“1”
“1”
“0”
“1”
“0”
“0”
“0”
“0”
NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is initiated
by the “trailing edge” of the convert command. (2) 57µs for 16 bits.
FIGURE 1. ADC71 Timing Diagram.
Bit 16
Valid
Serial
Out
40-125ns
40-125ns
Bit 16
Clock
Out
40-125ns
Status
FIGURE 2. Timing Relationship of Serial Data to Clock.
FIGURE 3. Timing Relationship of Valid Data to Status.
Binary (BIN)
Output
INPUT VOLTAGE RANGE AND LSB VALUES
Analog Input
Voltage Range
Defined As:
±10V
±5V
±2.5V
0 to +10V
CSB(3)
0 to +5V
CSB(3)
0 to +20V
CSB(3)
Code
Designation
COB(1)
or CTC(2)
COB(1)
or CTC(2)
COB(1)
or CTC(2)
One Least
Significant
Bit (LSB)
FSR
2n
n = 12
n = 13
n = 14
20V
2n
4.88mV
2.44mV
1.22mV
10V
2n
2.44mV
1.22mV
610µV
5V
2n
1.22mV
610µV
305µV
10V
2n
2.44mV
1.22mV
610µV
5V
2n
1.22mV
610µV
305µV
20V
2n
4.88mV
2.44mV
1.22mV
Transition Values
MSB LSB
000 ... 000(4)
011 ... 111
111 ... 110
+Full Scale
Mid Scale
–Full Scale
+10V–3/2LSB
0
–10V +1/2LSB
+5V–3/2LSB
0
–5V +1/2LSB
+2.5V–3/2LSB
0
–2.5V +1/2LSB
+10V–3/2LSB
+5V
0 +1/2LSB
+5V–3/2LSB
+2.5V
0 +1/2LSB
+20V–3/2LSB
+10V
0 +1/2LSB
NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Two’s Complement—obtained by inverting the most significant bit MSB (pin 1). (3) CSB
= Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.
TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions.
®
ADC71
4
TYPICAL PERFORMANCE CURVES
At +25°C and rated power supplies unless otherwise noted.
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
GAIN DRIFT ERROR (% OF FSR)
vs TEMPERATURE
+0.10
0.1
0.06
+0.08
ADC71AG, BG
0.04
–15VDC
+0.06
ADC71JG,KG
+0.04
0.02
+0.02
0
0.01
0.006
0.004
+15VDC
–0.02
–0.04
–0.06
–0.08
–0.10
+5VDC
0.002
0.001
–25°C
0°C
+25°C
+70°C +85°C
1
10
100
1k
10k
100k
Temperature (°C)
Frequency (Hz)
NOTE: Pa g es 4 &5
w ere sw it ch ed fo r
Ab rid g ed Versio n
fo r '9 6 d a t a b o o k.
DISCUSSION OF
PERFORMANCE
The accuracy of a successive approximation A/D converter
is described by the transfer function shown in Figure 1. All
successive approximation A/D converters have an inherent
Quantization Error of ±1/2 LSB. The remaining errors in the
A/D converter are combinations of analog errors due to the
linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including Gain, Offset, Linearity, Differential Linear-
ity, and Power Supply Sensitivity. Initial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature
rotates the line (Figure 1) about the zero or minus full scale
point (all bits Off) and Offset drift shifts the line left or right
over the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of A/D
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
level over the range of the A/D converter. A Differential
Linearity error of ±1/2 LSB means that the width of each bit
step over the range of the A/D converter is 1 LSB, ±1/2 LSB.
The ADC71 is monotonic, assuring that the output digital
code either increases or remains the same for increasing
analog input signals. Burr-Brown guarantees that these con-
verters will have no missing codes over a specified tempera-
ture range when short-cycled for 14-bit operation.
TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input such
that the positive true digital word 1001 1000 1001 0110
exists. The output will be complementary as shown in Figure
2 (0110 0111 0110 1001 is the digital output). Figures 3 and
4 are timing diagrams showing the relationship of serial data
to clock and valid data to status.
All Bits On
0000 ... 0000
Gain
Error
0000 ... 0001
0111 ... 1101
0111 ... 1110
0111 ... 1111
1000 ... 0000
1000 ... 0001
1111 ... 1110
1111 ... 1111
DEFINITION OF DIGITAL CODES
–1/2LSB
Parallel Data
Two binary codes are available on the ADC71 parallel
output; they are complementary (logic “0” is true) straight
binary (CSB) for unipolar input signal ranges and comple-
mentary offset binary (COB) for bipolar input signal ranges.
Complementary two’s complement (CTC) may be obtained
by inverting MSB (Pin 1).
+1/2LSB
Offset
Error
eIN On
All Bits Off
Analog Input
+FSR/2–1LSB
–FSR/2
Table I shows the LSB, transition values, and code defini-
tions for each possible analog input signal range for 12-, 13-
and 14-bit resolutions. Figure 5 shows the connections for
14-bit resolution, parallel data output, with ±10V input.
eIN Off
NOTE: (1) See Table I for Digital Code Definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar A/D
Converter.
®
5
ADC71
0.01µF(1)
MSB
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Offset
Adjust
Convert Command From
Control Logic
Dotted Lines
Are External
Connections
+5VDC
3
270kΩ
1.8MΩ
4
+15VDC
5
+
Gain
10kΩ to
6
1µF
1µF
100kΩ
Bipolar
Offset
Adjust
7
10kΩ to
100kΩ
ADC71
8
Analog Input
±10V
9
NC
10
11
12
13
14
15
16
+
–15VDC
+
1µF
Digital
Common
Analog
Common
Status Output to
Control Logic
NC
NC
NOTE: (1) Capacitor should be connected even if external gain adjust is not used.
FIGURE 5. ADC71 Connections for: ±10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output.
SERIAL DATA
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
+15VDC
(a)
1.8MΩ
27
10kΩ to 100kΩ
Offset Adjust
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
Comparator In
–15VDC
+15VDC
(b)
180kΩ
180kΩ
22kΩ
DISCUSSION
OF SPECIFICATIONS
The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for an A/D converter are linearity, drift, gain
and offset errors. This ADC is factory-trimmed and tested
for all critical key specifications.
27
10kΩ to 100kΩ
Offset Adjust
Comparator In
–15VDC
FIGURE 6. Two Methods of Connecting Optional Offset
Adjust with a 0.4% of FSR of Adjustment.
GAIN AND OFFSET ERROR
+15VDC
Initial Gain and Offset errors are factory-trimmed to typi-
cally ±0.1% of FSR (typically ±0.05% for unipolar offset) at
25°C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
270kΩ
29
10kΩ to 100kΩ
Gain Adjust
Gain Adjust
0.01µF
–15VDC
22
POWER SUPPLY SENSITIVITY
Analog Common
Changes in the DC power supplies will affect accuracy. The
power supply sensitivity is specified for ±0.003% of FSR/
%∆VS for ±15V supplies and ±0.001% of FSR/%∆S for +5
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling and Figure
8.
FIGURE 7. Connecting Optional Gain Adjust with a 0.2%
Range of Adjustment.
®
ADC71
6
Direct
Input
–15VDC
21
22
28
+5VDC
30
19
R2
5kΩ
24
25
1µF
1µF
Analog
Common
+
+
22
+
1µF
R1
5kΩ
Comp
In
27
26
Digital
Common
6.3kΩ
From D/A
Converter
+15VDC
Comparator
to Logic
VREF
Bipolar
Offset
FIGURE 8. Recommended Power Supply Decoupling.
FIGURE 9. ADC71 Input Scaling Circuit.
LAYOUT AND OPERATING INSTRUCTIONS
Layout Precautions
OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS
Analog and digital common are not connected internally in
the ADC71 but should be connected together as close to the
unit as possible, preferably to a large plane under the ADC.
If these grounds must be run separately, use wide conductor
patterns and a 0.01µF to 0.1µF non-polarized bypass capaci-
tor between analog and digital commons at the unit. Low
impedance analog and digital commons returns are essential
for low noise performance. Coupling between analog inputs
and digital lines should be minimized by careful layout. The
comparator input (Pin 27) is extremely sensitive to noise.
Any connection to this point should be as short as possible
and shielded by Analog Common patterns.
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to the
ADC as shown in Figure 6 and 7. Multiturn potentiometers
with 100ppm/°C or better TCRs are recommended for mini-
mum drift over temperature and time. These pots may be any
value from 10kΩ to 100kΩ. All resistors should be 20%
carbon or better. Pin 29 (Gain Adjust) and Pin 27 (Offset
Adjust) may be left open of no external adjustment is
required.
ADJUSTMENT PROCEDURE
OFFSET — Connect the Offset potentiometer (make sure R1
is as close to pin 27 as possible) as shown in Figure 6. Sweep
the input through the end point transition voltage that should
cause an output transition to all bits Off (EIN).
POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum ca-
pacitors as shown in Figure 8 to obtain noise free operation.
These capacitors should be located close to the ADC.
Adjust the Offset potentiometer until the actual end point
transition voltage occurs at EIN. The ideal transition voltage
values of the input are given in Table I.
INPUT SCALING
The analog input should be scaled as close to the maximum
input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/D converter. Connect the
input signal as shown in Table II. See Figure 9 for circuit
details.
GAIN — Connect the Gain Adjust potentiometer as shown
in Figure 7. Sweep the input through the end point transition
voltage that should cause an output transition to all bits on
(EIN). Adjust the Gain potentiometer until the actual end
point transition voltage occurs at EIN.
Table I details the transition voltage levels required.
CONNECT
INPUT
SIGNAL
RANGE
CONNECT
PIN 26
TO PIN
CONNECT
PIN 24
TO
INPUT
SIGNAL
TO PIN
CONVERT COMMAND CONSIDERATIONS
OUTPUT
CODE
Convert command resets the converter whenever taken high.
This insures a valid conversion on the first conversion after
power-up.
±10V
±5V
±2.5V
0 to +5V
0 to +10V
0 to +20V
COB or CTC(1)
COB or CTC(1)
COB or CTC(1)
CSB
27
27
27
22
22
22
Input Signal
Open
Pin 27
Pin 27
Open
24
25
25
25
25
24
Convert command must stay low during a conversion unless
it is desired to reset the converter during a conversion.
CSB
CSB
Input Signal
NOTE: (1) Obtained by inverting MSB pin 1.
ADDITIONAL CONNECTIONS REQUIRED
The ADC71 may be operated at faster speeds by connecting
the Short-Cycle Input, pin 32, as shown in Table III. Conver-
sion speeds, linearity, and resolutions are shown for refer-
ence.
TABLE II. ADC71 Input Scaling Connections.
®
7
ADC71
OUTPUT DRIVE
RESOLUTION (Bits)
16
14
13
12
Normally all ADC71 logic outputs will drive two standard
TTL loads; however, if long digital lines must be driver,
external logic buffers are recommended.
Connect Pin 32 to
Open
Pin 15
Pin 14
Pin 13
Maximum Conversion
Speed (µs)(1)
57
50
46.5
43
Maximum Nonlinearity
at 25°C (% of FSR)
0.003(2)
0.003(2)
0.006
0.006
HEAT DISSIPATION
NOTES: (1) Max conversion time to maintain specified nonlinearity error.
(2) BH and KH models only.
The ADC71 dissipates approximately 0.6W (typical) and the
packages have a case-to-ambient thermal resistance (θCA) of
25°C/W. For operation above 85°C, θCA should be lowered
by a heat sink or by forced air over the surface of the
package. See Figure 10 for θCA requirement above 85°C. If
the converter is mounted on a PC card, improved thermal
contact with the copper ground plane under the case can be
achieved using a silicone heat sink compound. On a 0.062"
thick PC card with a 16 square in (min) area, this techniques
will allow operation to 85°C.
TABLE III. Short-Cycle Connections and Specifications for
12- to 14-Bit Resolutions.
25
θ
10
0
60
70
80
90
100
110
125
Ambient Temperature (°C)
FIGURE 10. θCA Requirement Above 85°C.
®
ADC71
8
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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ADI
ADC72KD
IC 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP32, BOTTOM BRAZED, CERAMIC, DIP-32, Analog to Digital Converter
ADI
ADC72KM
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, CMOS, MDIP32,
BB
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