ADS1100IDBVR [BB]
Self-Calibrating, 16-Bit ANALOG-TO-DIGITAL CONVERTER; 自校准， 16位模拟数字转换器
| 型号： | ADS1100IDBVR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Self-Calibrating, 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1100
BAAI
SBAS239 – MAY 2002
Self-Calibrating, 16-Bit
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS1100 is a precision, continuously self-calibrating
Analog-to-Digital (A/D) converter with differential inputs and
up to 16 bits of resolution in a small SOT23-6 package.
Conversions are performed ratiometrically, using the power
supply as the reference voltage. The ADS1100 uses an
I2C-compatible serial interface and operates from a single
power supply ranging from 2.7V to 5.5V.
● COMPLETE DATA ACQUISITION SYSTEM IN A
TINY SOT23-6 PACKAGE
● 16-BITS NO MISSING CODES
● INL: 0.0125% of FSR MAX
● CONTINUOUS SELF-CALIBRATION
● SINGLE-CYCLE CONVERSION
The ADS1100 can perform conversions at rates of 8, 16, 32,
or 128 samples per second. The onboard programmable-
gain amplifier, which offers gains of up to 8, allows smaller
signals to be measured with high resolution. In single-
conversion mode, the ADS1100 automatically powers down
after a conversion, greatly reducing current consumption
during idle periods.
● PROGRAMMABLE GAIN AMPLIFIER
GAIN = 1, 2, 4, OR 8
● LOW NOISE: 4µVp-p
● PROGRAMMABLE DATA RATE: 8SPS to 128SPS
● INTERNAL SYSTEM CLOCK
● I2CTM INTERFACE
The ADS1100 is designed for applications requiring high-
resolution measurement, where space and power consump-
tion are major considerations. Typical applications include
portable instrumentation, industrial process control and smart
transmitters.
● POWER SUPPLY: 2.7V TO 5.5V
● LOW CURRENT CONSUMPTION: 90µA
APPLICATIONS
● PORTABLE INSTRUMENTATION
● INDUSTRIAL PROCESS CONTROL
● SMART TRANSMITTERS
A = 1, 2, 4, or 8
VIN+
VIN–
SCL
SDA
VDD
I2C
Interface
∆Σ A/D
Converter
PGA
● CONSUMER GOODS
● FACTORY AUTOMATION
● TEMPERATURE MEASUREMENT
GND
Clock
Oscillator
I2C is a registered trademark of Philips Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
VDD to GND ........................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
Voltage to GND, VIN+, VIN– ........................................ –0.3V to VDD + 0.3V
Voltage to GND, SDA, SCL .....................................................–0.5V to 6V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature .................................................... –40°C to +85°C
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
PACKAGE-LEAD DESIGNATOR(2)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
I2C ADDRESS(1)
ADS1100
1001 000
SOT23-6
DBV
–40°C to +85°C
BAAI
ADS1100IDBVT
Tape and Reel, 250
"
"
"
"
"
"
ADS1100IDBVR Tape and Reel, 3000
NOTES: (1) Contact TI or your local sales representative for more information on the availability of other addresses. (2) For the most current specifications and
package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
SOT
VIN– VDD
SDA
4
6
5
BAAI
1
2
3
VIN+ GND SCL
NOTE: Marking text direction indicates pin 1.
ADS1100
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ELECTRICAL CHARACTERISTICS
All specifications at –40°C to +85°C, VDD = 5V, GND = 0V, all PGAs, unless otherwise noted.
ADS1100
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Voltage
Analog Input Voltage
(VIN+) – (VIN–)
IN+, VIN– to GND
±VDD/PGA
V
V
V
GND – 0.2
VDD + 0.2
Differential Input Impedance
Common-Mode Input Impedance
2.4/PGA
8
MΩ
MΩ
SYSTEM PERFORMANCE
Resolution and No Missing Codes
DR = 00
DR = 01
DR = 10
DR = 11
DR = 00
DR = 01
DR = 10
DR = 11
12
14
15
16
104
26
12
14
15
16
184
46
Bits
Bits
Bits
Bits
Conversion Rate
128
32
16
8
SPS
SPS
SPS
SPS
13
6.5
23
11.5
Output Noise
Integral Nonlinearity
Offset Error
See Typical Characteristic Curves
DR = 11, PGA = 1, End Point Fit(1)
±0.003
±2.5/PGA
1.5
1.0
0.7
0.6
0.01
2
±0.0125
±5/PGA
% of FSR(2)
mV
µV/°C
µV/°C
µV/°C
µV/°C
%
ppm/°C
dB
dB
Offset Drift
PGA = 1
PGA = 2
PGA = 4
PGA = 8
8
4
2
2
0.1
Gain Error
Gain Error Drift
Common-Mode Rejection
At DC, PGA = 8
At DC, PGA = 1
94
100
85
DIGITAL INPUT/OUTPUT
Logic Level
VIH
VIL
VOL
0.7 • VDD
GND – 0.5
GND
6
V
V
V
0.3 • VDD
0.4
IOL = 3mA
Input Leakage
IIH
IIL
VIH = 5.5V
VIL = GND
10
µA
µA
–10
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Supply Current
VDD
Power Down
Active Mode
2.7
5.5
2
150
V
µA
µA
0.05
90
Power Dissipation
V
V
DD = 5.0V
DD = 3.0V
450
210
750
µW
µW
NOTES: (1) 99% of full-scale. (2) FSR = Full-Scale Range = 2 • VDD/PGA.
ADS1100
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
120
SUPPLY CURRENT vs I2C BUS FREQUENCY
250
225
200
175
150
125
100
75
VDD = 5V
100
25°C
125°C
80
60
VDD = 2.7V
–40°C
50
40
10
100
1k
10k
–60 –40 –20
0
20
40
60
80 100 120 140
I2C Bus Frequency (kHz)
Temperature (°C)
OFFSET ERROR vs TEMPERATURE
VDD = 5V
OFFSET ERROR vs TEMPERATURE
2.0
1.0
2.0
1.0
VDD = 2.7V
PGA = 8 PGA = 4 PGA = 2
PGA = 1
PGA = 8 PGA = 4
PGA = 2
PGA = 1
0.0
0.0
–1.0
–2.0
–1.0
–2.0
–60 –40 –20
0
20
40
60
80 100 120 140
–60 –40 –20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
GAIN ERROR vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
0.010
0.04
0.03
VDD = 5V
VDD = 2.7V
0.005
0.000
PGA = 4
PGA = 8
PGA = 4
PGA = 8
0.02
0.01
PGA = 1
–0.005
–0.010
–0.015
–0.020
0.00
PGA = 1
PGA = 2
–0.01
–0.02
–0.03
–0.04
PGA = 2
–60 –40 –20
0
20
40
60
80 100 120 140
–60 –40 –20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
ADS1100
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.
INTEGRAL NONLINEARITY vs
SUPPLY VOLTAGE
TOTAL ERROR vs INPUT SIGNAL
0.0
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0.000
PGA = 8
PGA = 4
PGA = 2
PGA = 1
PGA = 8
–0.5
PGA = 4
–1.0
PGA = 2
–1.5
–2.0
PGA = 1
Data Rate = 8SPS
50 75
–2.5
–100 –75
–50
–25
0
25
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Signal (% of Full-Scale)
VDD (V)
INTEGRAL NONLINEARITY vs TEMPERATURE
PGA =1
NOISE vs INPUT SIGNAL
Data Rate = 8SPS
0.05
0.04
0.03
0.02
0.01
0.00
20
15
10
5
PGA = 8
PGA = 4
VDD = 2.7V
PGA = 2
PGA = 1
VDD = 3.5V
VDD = 5V
0
0
20
40
60
80
100
–60 –40 –20
0
20
40
60
80 100 120 140
Input Signal (% of Full-Scale)
Temperature (°C)
NOISE vs TEMPERATURE
NOISE vs SUPPLY VOLTAGE
25
20
15
10
5
30
25
20
15
10
5
Data Rate = 8SPS
PGA = 8
PGA = 8
PGA = 4
PGA = 2
PGA = 1
4.5 5.0
Data Rate = 8SPS
0
–60 –40 –20
0
20
40
60
80 100 120 140
2.5
3.0
3.5
4.0
5.5
Temperature (°C)
V
DD (V)
ADS1100
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TYPICAL CHARACTERISTICS
At TA = 25°C, VDD = 5V, unless otherwise noted.
FREQUENCY RESPONSE
Data Rate = 8SPS
DATA RATE vs TEMPERATURE
10
0
–20
VDD = 2.7V
9
–40
8
–60
VDD = 5V
7
–80
Data Rate = 8SPS
6
–100
0.1
1
10
100
1k
–60 –40 –20
0
20
40
60
80 100 120 140
Input Frequency (Hz)
Temperature (°C)
ADS1100
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puts codes in binary two’s complement format, so the abso-
lute values of the minima and maxima are not the same; the
maximum n-bit code is 2n-1 – 1, while the minimum n-bit code
THEORY OF OPERATION
is –1 • 2n-1
.
The ADS1100 is a fully differential, 16-bit, self-calibrating,
delta-sigma A/D converter. Extremely easy to design with
and configure, the ADS1100 allows you to take high-quality
measurements with a minimum of effort.
For example, the ideal expression for output codes with a
data rate of 16SPS and PGA = 2 is:
V
– V
IN
–
(
)
(
)
IN
+
The ADS1100 consists of a delta-sigma A/D converter core
with adjustable gain, a clock generator, and an I2C interface.
Each of these blocks are described in detail in the sections
that follow.
Output Code = 16384 • 2 •
VDD
The ADS1100 outputs all codes right-justified and sign-
extended. This arrangement makes it possible to perform
averaging on the higher data rate codes using only a 16-bit
accumulator.
ANALOG-TO-DIGITAL CONVERTER
The ADS1100’s A/D converter core consists of a differential
switched-capacitor delta-sigma modulator followed by a digi-
tal filter. The modulator measures the difference between the
positive and negative analog inputs and compares this to a
reference voltage, which, in the ADS1100, is the power
supply. The digital filter receives a high-speed bitstream from
the modulator and outputs a code, which is a number
proportional to the input voltage.
Output codes for various input levels are shown in Table II.
SELF-CALIBRATION
The previous expressions for the ADS1100’s output code do
not account for the gain and offset errors in the modulator. To
compensate for these, the ADS1100 incorporates self-cali-
bration circuitry.
The self-calibration system operates continuously, and re-
quires no user intervention. No adjustments can be made to
the self-calibration system, and none need to be made. The
self-calibration system cannot be deactivated.
OUTPUT CODE CALCULATION
The output code is a scalar value which is (except for clipping)
proportional to the voltage difference between the two analog
inputs. The output code is confined to a finite range of numbers;
this range depends on the number of bits needed to represent
the code. The number of bits needed to represent the output
code for the ADS1100 depends on the data rate, as shown in
Table I.
The offset and gain error figures shown in the specifications
table include the effects of calibration.
CLOCK GENERATOR
The ADS1100 features an onboard clock generator, which
drives the operation of the modulator and digital filter. The
Typical Characteristics show varieties in data rate over
supply voltage and temperature.
Data rate
Number of Bits Minimum Code Maximum Code
8SPS
16SPS
32SPS
128SPS
16
15
14
12
–32768
–16384
–8192
32767
16383
8191
It is not possible to operate the ADS1100 with an external
modulator clock.
–2048
2047
TABLE I. Minimum and Maximum Codes.
INPUT IMPEDANCE
For a minimum output code of Min Code, gain setting of
PGA, positive and negative input voltages of VIN+ and VIN-
and power supply of VDD, the output code is given by the
expression:
The ADS1100 uses a switched-capacitor input stage. To
external circuitry, it looks roughly like a resistance. The
resistance value, as with all switched-capacitor circuits, de-
pends on the capacitor values and the rate at which they are
switched. The switching frequency is the same as the modu-
lator frequency; the capacitor values depend on the PGA
setting. The switching clock is generated by the onboard
clock generator, so its frequency, nominally 275 kHz, is
somewhat dependent on supply voltage and temperature.
,
V
– V
IN
–
(
)
(
)
IN
+
Output Code = –1•Min Code •PGA •
VDD
In the above expression, it is important to note that the
negated minimum output code is used. The ADS1100 out-
Input Signal
Data Rate
Negative Full-Scale
–1 LSB
Zero
+1 LSB
Positive Full-Scale
8 SPS
16 SPS
32 SPS
128 SPS
8000H
C000H
E000H
F800H
FFFFH
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0001H
0001H
0001H
0001H
7FFFH
3FFFH
1FFFH
07FFH
TABLE II. Output Codes for Different Input Signals.
ADS1100
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The common-mode and differential input impedances are
different. For a gain setting of PGA, the differential input
impedance is typically:
RESET AND POWER-UP
When the ADS1100 powers up, it automatically performs a
reset. As part of the reset, the ADS1100 sets all of the bits
in the configuration register to their default setting.
2.4MΩ / PGA
The ADS1100 responds to the I2C General Call Reset
command. When the ADS1100 receives a General Call
Reset, it performs an internal reset, exactly as though it had
just been powered on.
The common mode impedance is typically 8MΩ.
The typical value of the input impedance often cannot be
neglected. Unless the input source has a low impedance, the
ADS1100’s input impedance may affect the measurement
accuracy. For sources with high output impedance, buffering
may be necessary. Bear in mind, however, that active buffers
introduce noise, and also introduce offset and gain errors. All
of these factors should be considered in high-accuracy
applications.
I2C INTERFACE
The ADS1100 communicates through an I2C (Inter-Inte-
grated Circuit) interface. The I2C interface is a 2-wire open-
drain interface supporting multiple devices and masters on a
single bus. Devices on the I2C bus only drive the bus lines
LOW, by connecting them to ground; they never drive the
bus lines HIGH. Instead, the bus wires are pulled HIGH by
pull-up resistors, so the bus wires are HIGH when no device
is driving them LOW. This way, two devices cannot conflict;
if two devices drive the bus simultaneously, there is no driver
contention.
Because the clock generator frequency drifts slightly with
temperature, the input impedances will also drift. For many
applications, this input impedance drift can be neglected, and
the typical impedance values above can be used.
ALIASING
If frequencies are input to the ADS1100 which exceed half
the data rate, aliasing will occur. To prevent aliasing, the
input signal must be bandlimited. Some signals are inher-
ently bandlimited, for example, a thermocouple’s output,
which has a limited rate of change, but may nevertheless
contain noise and interference components. These can fold
back into the sampling band just as any other signal can.
Communication on the I2C bus always takes place between
two devices, one acting as the master and the other acting
as the slave. Both masters and slaves can read and write,
but slaves can only do so under the direction of the master.
Some I2C devices can act as masters or slaves, but the
ADS1100 can only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries
data; SCL provides the clock. All data is transmitted across
the I2C bus in groups of eight bits. To send a bit on the I2C
bus, the SDA line is driven to the bit’s level while SCL is
LOW. (A LOW on SDA indicates a zero bit; a HIGH indicates
a one bit.) Once the SDA line has settled, the SCL line is
brought HIGH, then LOW. This pulse on SCL clocks the SDA
bit into the receiver’s shift register.
The ADS1100’s digital filter provides some attenuation of
high frequency noise, but the filter’s sinc1 frequency re-
sponse cannot completely replace an anti-aliasing filter;
some external filtering may still be needed. For many appli-
cations, a simple RC filter will suffice.
When designing an input filter circuit, remember to take the
interaction between the filter network and the input imped-
ance of the ADS1100 into account.
The I2C bus is bidirectional: the SDA line is used both for
transmitting and receiving data. When a master reads from
a slave, the slave drives the data line; when a master sends
to a slave, the master drives the data line. The master always
drives the clock line. The ADS1100 never drives SCL,
because it cannot act as a master. On the ADS1100, SCL is
an input only.
USING THE ADS1100
OPERATING MODES
The ADS1100 operates in one of two modes: continuous
conversion and single conversion.
In continuous conversion mode, the ADS1100 continuously
performs conversions. Once a conversion has been com-
pleted, the ADS1100 places the result in the output register,
and immediately begins another conversion. When the
ADS1100 is in continuous conversion mode, the ST/BSY bit
in the configuration register always reads 1.
Most of the time the bus is idle, no communication is taking
place, and both lines are HIGH. When communication is
taking place, the bus is active. Only master devices can start
a communication. They do this by causing a start condition
on the bus. Normally, the data line is only allowed to change
state while the clock line is LOW. If the data line changes
state while the clock line is HIGH, it is either a start condition
or its counterpart, a stop condition. A start condition is when
the clock line is HIGH and the data line goes from HIGH to
LOW. A stop condition is when the clock line is HIGH and the
data line goes from LOW to HIGH.
In single conversion mode, the ADS1100 waits until the
ST/BSY bit in the conversion register is set to 1. When this
happens, the ADS1100 powers up and performs a single
conversion. After the conversion completes, the ADS1100
places the result in the output register, resets the ST/BSY bit
to 0 and powers down. Writing a 1 to ST/BSY while a
conversion is in progress has no effect.
After the master issues a start condition, it sends a byte
which indicates which slave device it wants to communicate
with. This byte is called the address byte. Each device on an
I2C bus has a unique 7-bit address to which it responds.
(Slaves can also have 10-bit addresses; see the I2C specifi-
When switching from continuous conversion mode to single
conversion mode, the ADS1100 will complete the current
conversion, reset the ST/BSY bit to 0 and power down.
ADS1100
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ADS1100 I2C ADDRESS
cation for details.) The master sends an address in the
address byte, together with a bit which indicates whether it
wishes to read from or write to the slave device.
The ADS1100’s I2C address is 1001aaa, where aaa are bits
set at the factory. The ADS1100 is shipped with aaa set to
zero, so its address is 1001000.
Every byte transmitted on the I2C bus, whether it be address
or data, is acknowledged with an acknowledge bit. When a
master has finished sending a byte, eight data bits, to a
slave, it stops driving SDA and waits for the slave to acknowl-
edge the byte. The slave acknowledges the byte by pulling
SDA LOW. The master then sends a clock pulse to clock the
acknowledge bit. Similarly, when a master has finished
reading a byte, it pulls SDA LOW to acknowledge this to the
slave. It then sends a clock pulse to clock the bit. (Remember
that the master always drives the clock line.)
Contact Texas Instruments for information about the avail-
ability of other addresses.
I2C GENERAL CALL
The ADS1100 responds to General Call Reset, which is an
address byte of 00H followed by a data byte of 06H. The
ADS1100 acknowledges both bytes.
On receiving a General Call Reset, the ADS1100 performs a
full internal reset, just as though it had been powered off and
then on. If a conversion is in process, it is interrupted; the
output register is set to zero; and the configuration register is
set to its default setting.
A not-acknowledge is performed by simply leaving SDA
HIGH during an acknowledge cycle. If a device is not present
on the bus, and the master attempts to address it, it will
receive a not-acknowledge because no device is present at
that address to pull the line LOW.
The ADS1100 always acknowledges the General Call ad-
dress byte of 00H, but it does not acknowledge any General
Call data bytes other than 04H or 06H.
When a master has finished communicating with a slave, it
may issue a stop condition. When a stop condition is issued,
the bus becomes idle again. A master may also issue
another start condition. When a start condition is issued while
the bus is active, it is called a repeated start condition.
I2C DATA RATES
The I2C bus operates in one of three speed modes: Stan-
dard, which allows a clock frequency of up to 100kHz; Fast,
which allows a clock frequency of up to 400kHz; and High-
A timing diagram for an ADS1100 I2C transaction is shown in
Figure 1. Table III gives the parameters for this diagram.
t(LOW)
tF
tR
t(HDSTA)
SCL
SDA
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
t(BUF)
P
S
S
P
FIGURE 1. I2C Timing Diagram.
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
SCLK Operating Frequency
f(SCLK)
0.4
3.4
MHz
ns
Bus Free Time Between STOP and START Condition t(BUF)
600
600
160
160
Hold Time After Repeated START Condition.
After this period, the first clock is generated.
t(HDSTA)
ns
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time
100
1300
600
10
SCLK Clock LOW Period
SCLK Clock HIGH Period
Clock/Data Fall Time
160
60
300
300
160
160
Clock/Data Rise Time
tR
TABLE III. Timing Diagram Definitions.
ADS1100
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speed mode (also called Hs mode), which allows a clock
frequency of up to 3.4MHz. The ADS1100 is fully compatible
with all three modes.
In continuous conversion mode, the ADS1100 ignores the
value written to ST/BSY.
When read in single conversion mode, ST/BSY indicates
whether the A/D converter is busy taking a conversion. If ST/
BSY is read as 1, the A/D converter is busy, and a conversion
is taking place; if 0, no conversion is taking place, and the
result of the last conversion is available in the output register.
No special action needs to be taken to use the ADS1100 in
Standard or Fast modes, but High-speed mode must be
activated. To activate High-speed mode, send a special
address byte of 00001XXX following the start condition,
where the XXX bits are unique to the Hs-capable master.
This byte is called the Hs master code. (Note that this is
different from normal address bytes: the low bit does not
indicate read/write status.) The ADS1100 will not acknowl-
edge this byte; the I2C specification prohibits acknowledg-
ment of the Hs master code. On receiving a master code, the
ADS1100 will switch on its High-speed mode filters, and will
communicate at up to 3.4MHz. The ADS1100 switches out of
Hs mode with the next stop condition.
In continuous mode, ST/BSY is always read as 1.
Bits 6-5: Reserved
Bits 6 and 5 must be set to zero.
Bit 4: SC
SC controls whether the ADS1100 is in continuous conver-
sion or single conversion mode. When SC is 1, the ADS1100
is in single conversion mode; when SC is 0, the ADS1100 is
in continuous conversion mode. The default setting is 0.
For more information on High-speed mode, consult the I2C
specification.
REGISTERS
Bits 3-2: DR
The ADS1100 has two registers which are accessible via its
I2C port. The output register contains the result of the last
conversion; the configuration register allows you to change
the ADS1100’s operating mode and query the status of the
device.
Bits 3 and 2 control the ADS1100’s data rate, as shown in
Table VI.
DR1
DR0
DATA RATE
0
0
0
1
128SPS
32SPS
16SPS
8SPS(1)
1
1(1)
0
1(1)
OUTPUT REGISTER
The 16-bit output register contains the result of the last
conversion in binary two’s complement format. Following
reset or power-up, the output register is cleared to zero; it
remains zero until the first conversion is completed. There-
fore, if you read the ADS1100 just after reset or power-up,
you will read zero from the output register.
NOTE: (1) Default Setting
TABLE VI. DR Bits.
Bits 1-0: PGA
Bits 1 and 0 control the ADS1100’s gain setting, as shown in
Table VII.
The output register’s format is shown in Table V.
PGA1
PGA0
GAIN
CONFIGURATION REGISTER
0(1)
0(1)
1
1(1)
2
You can use the 8-bit configuration register to control the
ADS1100’s operating mode, data rate, and PGA settings.
The configuration register’s format is shown in Table IV. The
default setting is 8CH.
0
1
0
4
1
1
8
NOTE: (1) Default Setting.
TABLE VII. PGA Bits.
BIT
7
6
0
5
0
4
3
2
1
0
NAME
ST/BSY
SC
DR1 DR0 PGA1 PGA0
READING FROM THE ADS1100
TABLE IV. Configuration Register.
You can read the output register and the contents of the
configuration register from the ADS1100. To do this, address
the ADS1100 for reading, and read three bytes from the
device. The first two bytes are the output register’s contents;
the third byte is the configuration register’s contents.
Bit 7: ST/BSY
The meaning of the ST/BSY bit depends on whether it is
being written to or read from.
You do not always have to read three bytes from the
ADS1100. If you want only the contents of the output regis-
ter, read only two bytes.
In single conversion mode, writing a 1 to the ST/BSY bit
causes a conversion to start, and writing a 0 has no effect.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TABLE V. Output Register.
10
ADS1100
SBAS239
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Reading more than three bytes from the ADS1100 has no
effect. All of the bytes beginning with the fourth will be FFH.
do this, address the ADS1100 for writing, and write one byte
to it. This byte is written into the configuration register.
A timing diagram for an ADS1100 read operation is shown in
Figure 2.
Writing more than one byte to the ADS1100 has no effect.
The ADS1100 will ignore any bytes sent to it after the first
one, and it will only acknowledge the first byte.
WRITING TO THE ADS1100
A timing diagram for an ADS1100 write operation is shown in
Figure 3.
You can write new contents into the configuration register
(you cannot change the contents of the output register). To
1
9
1
9
SCL
…
…
SDA
1
0
0
1
A2
A1
A0 R/W
D15 D14 D13 D12 D11 D10 D9
D8
Start By
Master
ACK By
ADS1100
From
ADS1100
ACK By
Master
Frame 1: I2C Slave Address Byte
Frame 2: Output Register Upper Byte
1
9
1
9
SCL
(Continued)
…
…
SDA
(Continued)
ST/
BSY
D7 D6
D5
D4
D3
D2
D1
D0
PGA1 PGA0
SC DR1 DR0
0
0
From
ADS1100
ACK By
Master
ACK By
Master
Stop By
Master
From
ADS1100
Frame 3: Output Register Lower Byte
Frame 4: Configuration Register
(Optional)
FIGURE 2. Timing Diagram for Reading From the ADS1100.
1
9
1
9
SCL
ST/
BSY
A2
PGA1 PGA0
SC DR1 DR0
SDA
1
0
0
1
A1
A0 R/W
0
0
Stop By
Master
Start By
Master
ACK By
ACK By
ADS1100
ADS1100
Frame 1: I2C Slave Address Byte
Frame 2: Configuration Register
FIGURE 3. Timing Diagram for Writing to the ADS1100.
ADS1100
11
SBAS239
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PACKAGE DRAWING
MPDS026D – FEBRUARY 1997 – REVISED FEBRUARY 2002
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,50
0,25
M
0,20
0,95
6
6X
4
0,15 NOM
1,70
1,50
3,00
2,60
1
3
Gage Plane
3,00
2,80
0,25
0,55
0 –8
0,35
Seating Plane
0,10
1,45
0,95
0,05 MIN
4073253-5/G 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
ADS1100
12
SBAS239
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