ADS1286A [BB]
12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER; 12位微功耗采样模拟数字转换器
| 型号： | ADS1286A |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总11页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS1286
ADS1286
ADS1286
12-Bit Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● SERIAL INTERFACE
The ADS1286 is a 12-bit, 20kHz analog-to-digital
converter with a differential input and sample and hold
amplifier and consumes only 250µA of supply cur-
rent. The ADS1286 offers an SPI and SSI compatible
serial interface for communications over a two or three
wire interface. The combination of a serial two wire
interface and micropower consumption makes the
ADS1286 ideal for remote applications and for those
requiring isolation.
● GUARANTEED NO MISSING CODES
● 20kHz SAMPLING RATE
● LOW SUPPLY CURRENT: 250µA
APPLICATIONS
● REMOTE DATA ACQUISITION
● ISOLATED DATA ACQUISITION
● TRANSDUCER INTERFACE
The ADS1286 is available in a 8-pin plastic mini DIP
and a 8-lead SOIC.
● BATTERY OPERATED SYSTEMS
Control
SAR
VREF
DOUT
+In
CDAC
Serial
Interface
DCLOCK
CS/SHDN
–In
Comparator
S/H Amp
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS-1335B
Printed in U.S.A. October, 1998
SPECIFICATIONS
At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS1286, ADS1286A
ADS1286K, ADS1286B
ADS1286C, ADS1286L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Range
Absolute Input Voltage
+In – (–In)
+In
0
–0.2
–0.2
VREF
VCC +0.2
+0.2
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
–In
Capacitance
Leakage Current
25
±1
✻
✻
✻
✻
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity
Differential Linearity
Offset Error
Gain Error
Noise
Power Supply Rejection
12
✻
✻
Bits
Bits
12
✻
✻
±1
±0.5
0.75
±2
50
82
±2
±1.0
±3
✻
✻
✻
✻
✻
✻
✻
±0.75
✻
±0.5
±0.25
✻
✻
✻
±1
±0.75
✻
LSB
LSB
LSB
LSB
µVrms
dB
±8
✻
✻
✻
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
12
✻
✻
Clk Cycles
Clk Cycles
kHz
1.5
✻
✻
Small Signal Bandwidth
500
✻
✻
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
V
V
V
V
IN = 5.0Vp-p at 1kHz
IN = 5.0Vp-p at 5kHz
IN = 5.0Vp-p at 1kHz
IN = 5.0Vp-p at 1kHz
–85
–83
72
✻
✻
✻
✻
✻
✻
✻
✻
dB
dB
dB
dB
SINAD
Spurious Free Dynamic Range
90
REFERENCE INPUT
REF Input Range
Input Resistance
1.25
2.5
5000
5000
0.01
2.4
VCC+0.05V
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
CS = VCC
CS = GND, fCLK = 0Hz
CS = VCC
tCYC ≥ 640µs, fCLK ≤ 25kHz
tCYC = 80µs, fCLK = 200kHz
MΩ
MΩ
µA
µA
µA
Current Drain
2.5
20
20
✻
✻
✻
✻
✻
✻
2.4
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
CMOS
✻
✻
IIH = +5µA
IIL = +5µA
IOH = 250µA
IOL = 250µA
3
0.0
3
+VCC
0.8
+VCC
0.4
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
VOL
0.0
Data Format
Straight Binary
✻
✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
VCC
+4.50
5
200
250
5.25
400
500
3
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
Quiescent Current, VANA
tCYC ≥ 640µS, fCLK ≤ 25kHz
µA
µA
µA
tCYC = 90µS, fCLK = 200kHz
Power Down
CS = VCC
TEMPERATURE RANGE
Specified Performance
ADS1286, K, L
ADS1286A, B, C
0
–40
+70
+85
✻
✻
✻
✻
✻
✻
✻
✻
°C
°C
✻ Specifications same as grade to the left.
TIMING CHARACTERISTICS
fCLK = 200kHz, TA = TMIN to TMAX
.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
tSMPL (MAX)
tCONV
tdDO
tdis
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
See Operating Sequence
ADS1286
1.5
2.0
20
Clk Cycles
kHz
See Operating Sequence
See Test Circuits
12
85
25
50
30
70
60
Clk Cycles
Delay TIme, DCLOCK↓ to DOUT Data Valid
Delay TIme, CS↑ to DOUT Hi-Z
Delay TIme, DCLOCK↓ to DOUT Enable
Output Data Remains Valid After DCLOCK↓
DOUT Fall Time
150
50
ns
ns
ns
ns
ns
ns
ns
ns
See Test Circuits
ten
See Test Circuits
100
thDO
tf
CLOAD = 100pF
15
30
See Test Circuits
100
100
0
tr
DOUT Rise Time
See Test Circuits
tCSD
tSUCS
Delay Time, CS↓ to DCLOCK↓
Delay Time, CS↓ to DCLOCK↑
See Operating Sequence
See Operating Sequence
®
ADS1286
2
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
+VCC ..................................................................................................... +6V
Analog Input ....................................................... –0.3V to (+VCC + 300mV)
Logic Input ......................................................... –0.3V to (+VCC + 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
NOTE: (1) Stresses above these ratings may permanently damage the device.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN CONFIGURATION
VREF
+In
1
2
3
4
8
7
6
5
+VCC
DCLOCK
DOUT
ADS1286
–In
GND
CS/SHDN
8-Pin Mini PDIP
8-Lead SOIC
PIN ASSIGNMENTS
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
VREF
+In
Reference Input.
Non Inverting Input.
–In
Inverting Input. Connect to ground or remote ground sense point.
Ground.
GND
CS/SHDN
DOUT
Chip Select when low, Shutdown Mode when high.
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
Data Clock synchronizes the serial data transfer and determines conversion speed.
7
8
DCLOCK
+VCC
Power Supply.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
INTEGRAL
LINEARITY
TEMPERATURE
RANGE
PRODUCT
PACKAGE
ADS1286P
±2
±2
±1
±2
±2
±1
±2
±2
±1
±2
±2
±1
0°C to +70°C
0°C to +70°C
Plastic DIP
Plastic DIP
Plastic DIP
SOIC
006
006
006
182
182
182
006
006
006
182
182
182
ADS1286PK
ADS1286PL
ADS1286U
0°C to +70°C
0°C to +70°C
ADS1286UK
ADS1286UL
ADS1286PA
ADS1286PB
ADS1286PC
ADS1286UA
ADS1286UB
ADS1286UC
0°C to +70°C
SOIC
0°C to +70°C
SOIC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Plastic DIP
Plastic DIP
Plastic DIP
SOIC
SOIC
SOIC
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix
C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS1286
TYPICAL PERFORMANCE CURVES
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
REFERENCE CURRENT vs SAMPLE RATE
REFERENCE CURRENT vs TEMPERATURE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
–55
–55
1
–40
–25
0
25
70
85
85
5
Sample Rate (kHz)
Temperature (°C)
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN OFFSET vs REFERENCE VOLTAGE
5
4.5
4
0.6
0.4
3.5
3
0.2
0
2.5
2
–0.2
–0.4
–0.6
1.5
1
0.5
0
–40
–25
0
25
70
1
2
3
4
5
Reference Voltage (V)
Temperature (°C)
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
CHANGE IN GAIN vs REFERENCE VOLTAGE
0.10
0.05
4
3.5
3
Change in Differential
Linearity (LSB)
0.00
2.5
2
–0.05
–0.10
–0.15
–0.20
1.5
1
Change in Integral
Linearity (LSB)
0.5
0
1
2
3
4
5
2
3
4
Reference Voltage (V)
Reference Voltage (V)
®
ADS1286
4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR vs CODE
12
11.75
11.5
11.25
11
3.0
2.0
1.0
0
10.75
10.5
10.25
10
–1.0
–2.0
–3.0
0.1
1
10
10
0
0
2048
Code
4095
Reference Voltage (V)
SPURIOUS FREE DYNAMIC RANGE
AND SIGNAL-TO-NOISE RATIO vs FREQUENCY
SIGNAL-TO-(NOISE + DISTORTION)
vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Spurious Free Dynamic Range
Signal-to-Noise Ratio
0.1
1
10
0.1
1
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
TOTAL HARMONIC DISTORTION vs FREQUENCY
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.1
1
10
–40
–35
–30
–25
–20
–15
–10
–5
Frequency (kHz)
Input Level (dB)
®
5
ADS1286
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
4096 POINT FFT
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
0
–25
–50
–75
–100
–125
0
2
4
6
0.1
–55
–55
1
10
85
85
Frequency (kHz)
Reference Voltage (V)
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
VRIPPLE = 20mV
CHANGE GAIN vs TEMPERATURE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–40
–25
0
25
70
1
10
100
1000
10000
Ripple Frequency (kHz)
Temperature (°C)
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
3
2.5
2
400
350
300
250
200
150
100
fSAMPLE = 12.5kHz
1.5
1
fSAMPLE = 1.6kHz
0.5
0
–55
–40
–25
0
25
70
85
–40
–25
0
25
70
Temperature (°C)
Temperature (°C)
®
ADS1286
6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
DIGITAL INPUT LINE THRESHOLD
vs SUPPLY VOLTAGE
INTEGRAL LINEARITY ERROR vs CODE
3.0
2.0
3
2.5
2
1.0
0
1.5
1
–1.0
–2.0
–3.0
0.5
0
0
2048
Code
4095
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
Supply Voltage (V)
INPUT LEAKAGE CURRENT vs TEMPERATURE
10
1
0.1
0.01
–55
–40
–25
0
25
70
85
Temperature (°C)
®
7
ADS1286
TIMING DIAGRAMS AND TEST CIRCUITS
1.4V
VOH
VOL
3kΩ
DOUT
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times tr, and tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdDO
t
dis Waveform 2, ten
3kΩ
DOUT
VOH
VOL
tdis Waveform 1
DOUT
100pF
CLOAD
thDO
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and tden
VIH
CS/SHDN
CS/SHDN
DCLOCK
DOUT
Waveform 1(1)
90%
10%
1
2
tdis
DOUT
Waveform 2(2)
VOL
DOUT
B11
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for ten
®
ADS1286
8
tCYC
CS/SHDN
DCLOCK
POWER
DOWN
tSUCS
tCSD
NULL
BIT
NULL
BIT
HI-Z
HI-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
B11 B10 B9 B8
DOUT
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
POWER DOWN
tCSD
NULL
HI-Z
HI-Z
BIT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
(MSB)
tSMPL
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS1286 Operating Sequence.
leaving the DCLOCK running to clock out the LSB first
data or zeroes. If the CS input is not running rail-to-rail, the
input logic buffer will draw current. This current may be
large compared to the typical supply current. To obtain the
lowest supply current, bring the CS pin to ground when it is
low and to supply voltage when it is high.
SERIAL INTERFACE
The ADS1286 communicates with microprocessors and other
external digital systems via a synchronous 3-wire serial inter-
face. DCLOCK synchronizes the data transfer with each bit
being transmitted on the falling DCLOCK edge and captured
on the rising DCLOCK edge in the receiving system. A falling
CS initiates data transfer as shown in Figure 1. After CS falls,
the second DCLOCK pulse enables DOUT. After one null bit,
the A/D conversion result is output on the DOUT line. Bringing
CS high resets the ADS1286 for the next data exchange.
1000
TA = 25°C
V
CC = 5V
VREF = 5V
CLK = 16 • fSAMPLE
100
10
1
f
MICROPOWER OPERATION
With typical operating currents of 250µA and automatic
shutdown between conversions, the ADS1286 achieves ex-
tremely low power consumption over a wide range of
sample rates (see Figure 2). The auto-shutdown allows the
supply current to drop with sample rate.
0.1k
1k
10k
100k
SHUTDOWN
Sample Rate (kHz)
The ADS1286 is equipped with automatic shutdown fea-
tures. The device draws power when the CS pin is LOW and
shuts down completely when the pin is HIGH. The bias
circuit and comparator powers down and the reference input
becomes high impedance at the end of each conversion
FIGURE 2. Automatic Power Shutdown Between Conver-
sions Allows Power Consumption to Drop with
Sample Rate.
®
9
ADS1286
MINIMIZING POWER DISSIPATION
REDUCED REFERENCE
OPERATION
In systems that have significant time between conversions,
the lowest power drain will occur with the minimum CS
LOW time. Bringing CS LOW, transferring data as quickly
as possible, and then bringing it back HIGH will result in the
lowest current drain. This minimizes the amount of time the
device draws power. After a conversion the A/D automati-
cally shuts down even if CS is held LOW. If the clock is left
running to clock out LSB-data or zero, the logic will draw a
small amount of current (see Figure 3).
The effective resolution of the ADS1286 can be increased
by reducing the input span of the converter. The ADS1286
exhibits good linearity and gain over a wide range of
reference voltages (see Typical Performance Curves “ Change
in Linearity vs Reference Voltage” and “Change in Gain vs
Reference Voltage”). However, care must be taken when
operating at low values of VREF because of the reduced LSB
size and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low VREF values:
6.00
TA = 25°C
VCC = +5V
1. Offset
2. Noise
5.00
V
REF = +5V
f
CLK = 16 • fSAMPLE
4.00
3.00
2.00
1.00
0.00
OFFSET WITH REDUCED VREF
CS = LOW
(GND)
The offset of the ADS1286 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The Typical Performance Curve “Change in
Offset vs Reference Voltage” shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 122µV which is 0.1 LSB with a 5V
reference becomes 0.5LSB with a 1V reference and 2.5LSBs
with a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the negative input of the ADS1286.
CS HIGH
(VCC
)
0.1
1
10
100
Sample Rate (kHz)
FIGURE 3. Shutdown Current with CS HIGH is Lower than
with CS LOW.
RC INPUT FILTERING
It is possible to filter the inputs with an RC network as
shown in Figure 4. For large values of CFILTER (e.g., 1µF),
the capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops across
the resistor. The magnitude of the DC current is approxi-
mately IDC = 20pF x VIN/tCYC and is roughly proportional to
VIN. When running at the minimum cycle time of 64µs, the
input current equals 1.56µA at VIN = 5V. In this case, a filter
resistor of 75Ω will cause 0.1LSB of full-scale error. If a
larger filter resistor must be used, errors can be eliminated
by increasing the cycle time.
NOISE WITH REDUCED VREF
The total input referred noise of the ADS1286 can be
reduced to approximately 200µV peak-to-peak using a ground
plane, good bypassing, good layout techniques and minimiz-
ing noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of an
LSB as the size of the LSB is reduced.
For operation with a 5V reference, the 200µV noise is only
0.15LSB peak-to-peak. In this case, the ADS1286 noise will
contribute virtually no uncertainty to the output code. How-
ever, for reduced references, the noise may become a signifi-
cant fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 2.5V reference this same
200µV noise is 0.3LSB peak-to-peak. If the reference is
further reduced to 1V, the 200µV noise becomes equal to
0.8LSBs and a stable code may be difficult to achieve. In
this case averaging multiple readings may be necessary.
IDC
RFILTER
VIN
ADS1286
CFILTER
FIGURE 4. RC Input Filtering.
®
ADS1286
10
+5V
+5V
+5V
R8
46kΩ
0.4V
0.3V
R7
10Ω
R9
1kΩ
R1
150kΩ
OPA237
D1
C2
0.1µF
U2
R3
500kΩ
R10
1kΩ
C1
10µF
MUX
R6
1MΩ
R2
59kΩ
VREF
0.2V
0.1V
DCLOCK
DOUT
R11
1kΩ
C3
0.1µF
ADS1286
TC1
A0
TC2
TC3
CS/SHDN
A1
Thermocouple
R12
1kΩ
U1
C4
10µF
R4
1kΩ
U3
C5
0.1µF
R5
500Ω
µP
ISO Thermal Block
3-Wire
Interface
U4
FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286.
+VCC
REF200
(100µA)
0.1µF
VREF
1
8
DCLOCK
DOUT
2
µP
ADS1286
RTD
CS/SHDN
3
4
FIGURE 6. ADS1286 with RTD Sensor.
®
11
ADS1286
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