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ADS8330 [BB]

LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE; 低功耗， 16位， 1兆赫，单/双单极性输入，模拟 - 数字转换器，串行接口
ADS8330
型号： ADS8330
厂家： BURR-BROWN CORPORATION    BURR-BROWN CORPORATION
描述：

LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
低功耗， 16位， 1兆赫，单/双单极性输入，模拟 - 数字转换器，串行接口

转换器 输入元件
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ADS8329  
ADS8330  
SLAS516–DECEMBER 2006  
LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL  
CONVERTERS WITH SERIAL INTERFACE  
FEATURES  
APPLICATIONS  
•
•
•
•
•
•
•
Communications  
•
2.7-V to 5.5-V Analog Supply, Low Power:  
Transducer Interface  
Medical Instruments  
Magnetometers  
Industrial Process Control  
Data Acquisition Systems  
Automatic Test Equipment  
–
15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V)  
•
•
1-MHz Sampling Rate 3 V ≤ +VA ≤ 5.5 V,  
900-kHz Sampling Rate 2.7 V ≤ +VA ≤ 3 V  
Excellent DC Performance  
–
–
–
–
–
±1.0 LSB Typ, ±1.75 LSB Max INL  
±0.5 LSB Typ, ±1 LSB Max DNL  
16-Bit NMC Over Temperature  
±0.5 mV Max Offset Error at 3 V  
±1 mV Max Offset Error at 5 V  
DESCRIPTION  
The ADS8329 is a low power, 16-bit, 1-MSPS  
analog-to-digital converter with a unipolar input. The  
device includes a 16-bit capacitor-based SAR A/D  
converter with inherent sample and hold.  
•
Excellent AC Performance at fi = 100 kHz with  
92 dB SNR, 102 dB SFDR, –102 dB THD  
•
•
Built-In Conversion Clock (CCLK)  
1.65 V to 5.5 V I/O Supply  
The ADS8330 is based on the same core and  
includes a 2-to-1 input MUX with programmable  
option of TAG bit output. Both the ADS8329 and  
ADS8330 offer a high-speed, wide voltage serial  
interface and are capable of chain mode operation  
when multiple converters are used.  
–
–
SPI/DSP Compatible Serial  
SCLK up to 50 MHz  
•
Comprehensive Power-Down Modes:  
–
–
–
Deep Powerdown  
Nap Powerdown  
These converters are available in a 4x4 QFN  
package and are fully specified for operation over the  
industrial –40°C to +85°C temperature range.  
Auto Nap Powerdown  
•
•
•
•
•
•
•
•
Unipolar Input Range: 0 V to Vref  
Software Reset  
Low Power, High-Speed SAR Converter Family  
Type/Speed  
Single  
500 kHz  
ADS8327  
ADS8328  
1 MHz  
ADS8329  
ADS8330  
Global CONVST (Independent of CS)  
Programmable Status/Polarity EOC/INT  
16-Pin 4 x 4 QFN Package  
16 Bit Pseudo-Diff  
Dual  
Multi-Chip Daisy Chain Mode  
Programmable TAG Bit Output  
Auto/Manual Channel Select Mode (ADS8330)  
OUTPUT  
LATCH  
and  
3−STATE  
DRIVER  
ADS8330 ADS8329  
SDO  
SAR  
NC  
+IN1  
+IN0  
COM  
+
_
CDAC  
+IN  
FS/CS  
SCLK  
SDI  
CONVERSION  
and  
CONTROL  
LOGIC  
COMPARATOR  
−IN  
REF+  
REF−  
CONVST  
OSC  
EOC/INT/CDI  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006, Texas Instruments Incorporated  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
MAXIMUM  
INTEGRAL  
LINEARITY  
(LSB)  
MAXIMUM  
DIFFERENTIAL  
LINEARITY  
(LSB)  
MAXIMUM  
OFFSET  
ERROR  
(mV)  
TRANSPORT  
MEDIA  
QUANTITY  
PACKAGE  
TYPE  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
ORDERING  
INFORMATION  
MODEL  
Small tape and  
reel 250  
ADS8329IRSAT  
ADS8329IRSAR  
ADS8329IBRSAT  
ADS8329IBRSAR  
ADS8330IRSAT  
ADS8330IRSAR  
ADS8330IBRSAT  
ADS8330IBRSAR  
ADS8329I  
±2.5  
±1.75  
±2.5  
–1/+2  
±1  
±0.8  
±0.5  
±0.8  
±0.5  
4X4 QFN-16  
4X4 QFN-16  
4X4 QFN-16  
4X4 QFN-16  
RSA  
RSA  
RSA  
RSA  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
Tape and reel  
3000  
Small tape and  
reel 250  
ADS8329IB  
ADS8330I  
ADS8330IB  
Tape and reel  
3000  
Small tape and  
reel 250  
–1/+2  
±1  
Tape and reel  
3000  
Small tape and  
reel 250  
±1.75  
Tape and reel  
3000  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
UNIT  
+IN to AGND  
–0.3 V to +VA + 0.3 V  
–0.3 V to +VA + 0.3 V  
–0.3 V to 7 V  
Voltage  
Voltage  
–IN to AGND  
+VA to AGND  
+VBD to BDGND  
AGND to BDGND  
–0.3 V to 7 V  
–0.3 V to 0.3 V  
–0.3 V to +VBD + 0.3 V  
–0.3 V to +VBD + 0.3 V  
–40°C to 85°C  
–65°C to 150°C  
150°C  
Digital input voltage to BDGND  
Digital output voltage to BDGND  
Operating free-air temperature range  
Storage temperature range  
TA  
Tstg  
Junction temperature (TJ max)  
Vapor phase (60 sec)  
Infrared (15 sec)  
215°C  
Lead temperature, soldering  
220°C  
4x4 QFN-16  
Package  
Power dissipation  
(TJMax - TA)/θJA  
47°C/W  
θJA thermal impedance  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2
Submit Documentation Feedback  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
SPECIFICATIONS  
TA = –40°C to 85°C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, Vref = 5 V, fSAMPLE = 1 MHz (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ANALOG INPUT  
(1)  
Full-scale input voltage  
+IN – (–IN) or (+INx – COM)  
+IN, +IN0, +IN1  
0
AGND – 0.2  
AGND – 0.2  
+Vref  
+VA + 0.2  
AGND + 0.2  
45  
V
V
Absolute input voltage  
–IN or COM  
Input capacitance  
40  
pF  
nA  
No ongoing conversion,  
DC Input  
Input leakage current  
-1  
1
At dc  
109  
101  
Input channel isolation, ADS8330 only  
SYSTEM PERFORMANCE  
dB  
VI = ±1.25 Vpp at 50 kHz  
Resolution  
16  
Bits  
Bits  
No missing codes  
16  
–1.75  
-2.5  
– 1  
ADS8329IB, ADS8330IB  
±1.2  
±1.5  
±0.4  
±0.5  
±0.27  
±0.8  
0.4  
1.75  
2.5  
1
Integral  
linearity  
INL  
DNL  
EO  
LSB(2)  
LSB(2)  
mV  
ADS8329I, ADS8330I  
ADS8329IB, ADS8330IB  
ADS8329I, ADS8330I  
ADS8329IB, ADS8330IB  
ADS8329I, ADS8330I  
Differential  
linearity  
–1  
2
– 1  
1
Offset error(3)  
–1.25  
1.25  
Offset error drift  
Gain error  
FSR = 5 V  
PPM/°C  
%FSR  
EG  
– 0.25  
–0.04  
0.75  
70  
0.25  
Gain error drift  
PPM/°C  
At dc  
CMRR  
Common mode rejection ratio  
dB  
VI = 0.4 Vpp at 1 MHz  
50  
Noise  
33  
µV RMS  
PSRR  
Power supply rejection ratio  
At FFFFh output code(3)  
78  
dB  
SAMPLING DYNAMICS  
tCONV  
Conversion time  
18  
3
CCLK  
CCLK  
tSAMPLE1  
tSAMPLE2  
Manual trigger  
Auto trigger  
3
Acquisition time  
Throughput rate  
Aperture delay  
Aperture jitter  
1
MHz  
ns  
5
10  
ps  
Step response  
100  
100  
ns  
Overvoltage recovery  
ns  
(1) Ideal input span, does not include gain or offset error.  
(2) LSB means least significant bit  
(3) Measured relative to an ideal full-scale input [+IN – (–IN)] of 4.096 V when +VA = 5 V.  
3
Submit Documentation Feedback  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
SPECIFICATIONS (continued)  
TA = –40°C to 85°C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, Vref = 5 V, fSAMPLE = 1 MHz (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
dB  
DYNAMIC CHARACTERISTICS  
VIN = 5 Vpp at 10 kHz  
–102  
–95  
93  
(4)  
THD  
Total harmonic distortion  
Signal-to-noise ratio  
VIN = 5 Vpp at 100 kHz  
VIN = 5 Vpp at 10 kHz  
SNR  
ADS8329/30IB  
ADS8329/30I  
90  
92  
dB  
VIN = 5 Vpp at 100 kHz  
90  
VIN = 5 Vpp at 10 kHz  
VIN = 5 Vpp at 100 kHz  
VIN = 5 Vpp at 10 kHz  
VIN = 5 Vpp at 100 kHz  
92  
SINAD  
SFDR  
Signal-to-noise + distortion  
dB  
90  
105  
97  
Spurious free dynamic range  
-3dB Small signal bandwidth  
dB  
30  
MHz  
CLOCK  
Internal conversion clock frequency  
SCLK External serial clock  
21  
1
22.9  
24.5  
50  
MHz  
MHz  
Used as I/O clock only  
As I/O clock and conversion clock  
42  
EXTERNAL VOLTAGE REFERENCE INPUT  
Input  
reference  
range  
Vref[REF+ – (REF–)]  
(REF–) – AGND  
5.5 V ≥ +VA ≥ 4.5 V  
0.3  
5
5
Vref  
V
–0.1  
0.1  
(5)  
Resistance  
Reference input  
40  
kΩ  
DIGITAL INPUT/OUTPUT  
Logic family — CMOS  
High-level input voltage  
VIH  
VIL  
5.5 V ≥ +VBD ≥ 4.5 V  
5.5 V ≥ +VBD ≥ 4.5 V  
VI = +VBD or BDGND  
0.65 × (+VBD)  
+VBD + 0.3  
V
V
0.35 ×  
(+VBD)  
Low-level input voltage  
–0.3  
-50  
II  
Input current  
50  
nA  
pF  
Ci  
Input capacitance  
5
5
5.5 V ≥ +VBD ≥ 4.5 V,  
IO = 100 µA  
VOH  
VOL  
High-level output voltage  
Low-level output voltage  
+VBD – 0.6  
0
+VBD  
0.4  
V
V
5.5 V ≥ +VBD ≥ 4.5 V,  
IO = 100 µA  
CO  
CL  
Output capacitance  
pF  
pF  
Load capacitance  
30  
Data format — straight binary  
POWER SUPPLY REQUIREMENTS  
+VBD  
1.65  
4.5  
3.3  
5
5.5  
5.5  
7.8  
0.5  
50  
V
V
Power supply  
voltage  
+VA  
1-MHz Sample rate  
Nap mode  
7.0  
0.3  
4
mA  
Supply current  
PD Mode  
nA  
Buffer I/O supply current  
Power dissipation  
1 MSPS  
1.7  
44  
35  
mA  
+VA = 5 V, +VBD = 5 V  
+VA = 5 V, +VBD = 1.8 V  
48  
mW  
°C  
39.5  
TEMPERATURE RANGE  
TA  
Operating free-air temperature  
–40  
85  
(4) Calculated on the first nine harmonics of the input frequency  
(5) Can vary ±30%  
4
Submit Documentation Feedback  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
SPECIFICATIONS  
TA = –40°C to 85°C, +VBD = +VA × 1.5 to +1.65 V, Vref = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for  
3 V < +VA ≤ 2.7 V using external clock (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ANALOG INPUT  
(1)  
Full-scale input voltage  
+IN – (–IN) or (+INx – COM)  
+IN, +IN0, +IN1  
0
AGND – 0.2  
AGND – 0.2  
+Vref  
+VA + 0.2  
AGND + 0.2  
45  
V
V
Absolute input voltage  
–IN or COM  
Input capacitance  
40  
pF  
nA  
No ongoing conversion,  
DC Input  
Input leakage current  
-1  
1
At dc  
108  
101  
Input channel isolation, ADS8330 only  
SYSTEM PERFORMANCE  
dB  
VI = ±1.25 Vpp at 50 kHz  
Resolution  
16  
Bits  
Bits  
No missing codes  
16  
–1.75  
–2.5  
– 1  
ADS8329IB,  
ADS8330IB  
±1  
±1.5  
1.75  
2.5  
1
INL  
DNL  
EO  
Integral linearity  
LSB(2)  
LSB(2)  
mV  
ADS8329I, ADS8330I  
ADS8329IB,  
ADS8330IB  
±0.5  
Differential  
linearity  
ADS8329I, ADS8330I  
–1  
±0.8  
2
ADS8329IB,  
ADS8330IB  
– 0.5  
–0.8  
±0.05  
0.5  
0.8  
Offset error(3)  
ADS8329I, ADS8330I  
±0.2  
0.8  
Offset error drift  
Gain error  
FSR = 2.5 V  
PPM/°C  
%FSR  
EG  
– 0.25  
–0.04  
0.5  
0.25  
Gain error drift  
PPM/°C  
At dc  
70  
CMRR  
Common mode rejection ratio  
dB  
VI = 0.4 Vpp at 1 MHz  
50  
Noise  
33  
µV RMS  
PSRR  
Power supply rejection ratio  
At FFFFh output code(3)  
78  
dB  
SAMPLING DYNAMICS  
tCONV  
Conversion time  
18  
3
CCLK  
CCLK  
tSAMPLE1  
tSAMPLE2  
Manual trigger  
Auto trigger  
3
Acquisition time  
Throughput rate  
Aperture delay  
Aperture jitter  
1
MHz  
ns  
5
10  
ps  
Step response  
100  
100  
ns  
Overvoltage recovery  
ns  
(1) Ideal input span, does not include gain or offset error.  
(2) LSB means least significant bit  
(3) Measured relative to an ideal full-scale input [+IN – (–IN)] of 2.5 V when +VA = 3 V.  
5
Submit Documentation Feedback  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
SPECIFICATIONS (continued)  
TA = –40°C to 85°C, +VBD = +VA × 1.5 to +1.65 V, Vref = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for  
3 V < +VA ≤ 2.7 V using external clock (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DYNAMIC CHARACTERISTICS  
VIN = 2.5 Vpp at 10 kHz  
–102  
–93  
89  
(4)  
THD  
Total harmonic distortion  
Signal-to-noise ratio  
dB  
dB  
dB  
VIN = 2.5 Vpp at 100 kHz  
VIN = 2.5 Vpp at 10 kHz  
VIN = 2.5 Vpp at 100 kHz  
VIN = 2.5 Vpp at 10 kHz  
VIN = 2.5 Vpp at 100 kHz  
VIN = 2.5 Vpp at 10 kHz  
VIN = 2.5 Vpp at 100 kHz  
SNR  
88  
88.5  
88  
SINAD  
SFDR  
Signal-to-noise + distortion  
104  
94.2  
30  
Spurious free dynamic range  
-3dB Small signal bandwidth  
dB  
MHz  
CLOCK  
Internal conversion clock frequency  
SCLK External serial clock  
21  
1
22.3  
40  
5
23.5  
42  
MHz  
MHz  
Used as I/O clock only  
As I/O clock and conversion clock  
42  
EXTERNAL VOLTAGE REFERENCE INPUT  
Vref[REF+ – (REF–)]  
(REF–) – AGND  
3.6 V ≥ +VA ≥ 2.7 V  
2.475  
–0.1  
3
Input reference  
range  
Vref  
V
0.1  
(5)  
Resistance  
Reference input  
kΩ  
DIGITAL INPUT/OUTPUT  
Logic family — CMOS  
High-level input voltage  
VIH  
VIL  
II  
(+VA × 1.5) V ≥ +VBD ≥ 1.65 V  
(+VA × 1.5) V ≥ +VBD ≥ 1.65 V  
VI = +VBD or BDGND  
0.65 × (+VBD)  
+VBD + 0.3  
0.35 × (+VBD)  
50  
V
V
Low-level input voltage  
Input current  
–0.3  
-50  
nA  
pF  
Ci  
Input capacitance  
(+VA × 1.5) V ≥ +VBD ≥ 1.65 V,  
IO = 100 µA  
VOH  
VOL  
High-level output voltage  
Low-level output voltage  
+VBD – 0.6  
0
+VBD  
0.4  
V
V
(+VA × 1.5) V ≥ +VBD ≥ 1.65 V,  
IO = 100 µA  
CO  
CL  
Output capacitance  
5
pF  
pF  
Load capacitance  
30  
Data format — straight binary  
POWER SUPPLY REQUIREMENTS  
+VBD  
1.65  
3
+VA  
1.5 × (+VA)  
V
V
Power supply  
voltage  
fs ≤ 1 MHz  
3.6  
3.6  
+VA  
fs ≤ 900 kHz  
2.7  
1-MHz Sample rate,  
3 V ≤ +VA ≤ 3.6 V  
5.1  
6.1  
900-kHz Sample rate,  
2.7 V ≤ +VA ≤ 3 V  
mA  
4.84  
Supply current  
Nap mode  
0.25  
2
0.4  
50  
PD Mode  
nA  
Buffer I/O supply current  
Power dissipation  
1 MSPS, +VBD = 1.8 V  
+VBD = 1.8 V, 3 V ≤ +VA ≤ 3.6 V  
+VBD = 1.8 V, 2.7 V ≤ +VA ≤ 3 V  
0.05  
15.5  
13.2  
mA  
19  
85  
mW  
°C  
TEMPERATURE RANGE  
TA Operating free-air temperature  
–40  
(4) Calculated on the first nine harmonics of the input frequency  
(5) Can vary ±30%  
6
Submit Documentation Feedback  
ADS8329  
ADS8330  
www.ti.com  
SLAS516–DECEMBER 2006  
TIMING CHARACTERISTICS  
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V  
(1)(2)  
PARAMETER  
MIN  
TYP  
MAX UNIT  
Frequency, conversion clock, CCLK,  
fCCLK = 1/2 fSCLK  
fCCLK  
External  
Internal  
0.5  
21 MHz  
21  
1
22.9  
24.5  
CCLK  
ns  
tsu(CSF-EOC)  
th(CSF-EOC)  
twL(CONVST)  
tsu(CSF-EOS)  
th(CSF-EOS)  
tsu(CSR-EOS)  
th(CSR-EOS)  
tsu(CSF-SCLK1R)  
twL(SCLK)  
Setup time, falling edge of CS to EOC  
Hold time, falling edge of CS to EOC  
Pulse duration, CONVST low  
0
40  
20  
20  
20  
20  
5
ns  
Setup time, falling edge of CS to EOS  
Hold time, falling edge of CS to EOS  
Setup time, rising edge of CS to EOS  
Hold time, rising edge of CS to EOS  
Setup time, falling edge of CS to SCLK  
Pulse duration, SCLK low  
ns  
ns  
ns  
ns  
tc(SCLK) - 5  
ns  
ns  
ns  
8
tc(SCLK) - 8  
tc(SCLK) - 8  
twH(SCLK)  
Pulse duration, SCLK high  
8
I/O Clock only  
20  
23.8  
20  
I/O and conversion clock  
I/O Clock, chain mode  
2000  
2000  
tc(SCLK)  
Cycle time, SCLK  
ns  
I/O and conversion clock,  
chain mode  
23.8  
5
Delay time, falling edge of SCLK to SDO  
invalid  
td(SCLKF-SDOINVALID)  
td(SCLKF-SDOVALID)  
td(CSF-SDOVALID)  
10-pF Load  
10-pF Load  
10-pF Load  
ns  
ns  
ns  
Delay time, falling edge of SCLK to SDO  
valid  
12  
12  
Delay time, falling edge of CS to SDO  
valid, SDO MSB output  
tsu(SDI-SCLKF)  
th(SDI-SCLKF)  
Setup time, SDI to falling edge of SCLK  
Hold time, SDI to falling edge of SCLK  
8
4
ns  
ns  
Delay time, rising edge of CS/FS to SDO  
3-state  
td(CSR-SDOZ)  
tsu(lastSCLKF-CSR)  
td(SDO-CDI)  
5
ns  
ns  
ns  
Setup time, last falling edge of SCLK  
before rising edge of CS/FS  
10  
Delay time, CDI high to SDO high in daisy  
chain mode  
10-pF Load, chain mode  
16  
(1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.  
(2) See timing diagrams.  
7
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SLAS516–DECEMBER 2006  
TIMING CHARACTERISTICS  
All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (unless otherwise noted)  
(1)(2)  
PARAMETER  
MIN  
0.5  
TYP  
MAX UNIT  
External, 3 V ≤ +VA ≤ 3.6 V  
External, 2.7 V ≤ +VA ≤ 3 V  
Internal  
21  
Frequency, conversion clock, CCLK,  
fCCLK = 1/2 fSCLK  
fCCLK  
0.5  
21  
1
18.9 MHz  
22.3  
23.5  
CCLK  
ns  
tsu(CSF-EOC)  
th(CSF-EOC)  
twL(CONVST)  
tsu(CSF-EOS)  
th(CSF-EOS)  
tsu(CSR-EOS)  
th(CSR-EOS)  
tsu(CSF-SCLK1R)  
twL(SCLK)  
Setup time, falling edge of CS to EOC  
Hold time, falling edge of CS to EOC  
Pulse duration, CONVST low  
0
40  
20  
20  
20  
20  
5
ns  
Setup time, falling edge of CS to EOS  
Hold time, falling edge of CS to EOS  
Setup time, rising edge of CS to EOS  
Hold time, rising edge of CS to EOS  
Setup time, falling edge of CS to SCLK  
Pulse duration, SCLK low  
ns  
ns  
ns  
ns  
tc(SCLK) - 5  
ns  
ns  
ns  
8
tc(SCLK) - 8  
tc(SCLK) - 8  
twH(SCLK)  
Pulse duration, SCLK high  
8
I/O Clock only  
23.8  
I/O and conversion clock,  
3 V ≤ +VA ≤ 3.6 V  
23.8  
2000  
2000  
I/O and conversion clock,  
2.7 V ≤ +VA < 3 V  
26.5  
23.8  
I/O Clock, chain mode  
tc(SCLK)  
Cycle time, SCLK  
ns  
I/O and conversion clock,  
chain mode,  
3 V ≤ +VA ≤ 3.6 V  
23.8  
2000  
2000  
I/O and conversion clock,  
chain mode,  
2.7 V ≤ +VA < 3 V  
26.5  
8
Delay time, falling edge of SCLK to SDO  
invalid  
td(SCLKF-SDOINVALID)  
td(SCLKF-SDOVALID)  
td(CSF-SDOVALID)  
10-pF Load  
10-pF Load  
10-pF Load  
ns  
ns  
ns  
Delay time, falling edge of SCLK to SDO  
valid  
23  
23  
Delay time, falling edge of CS to SDO  
valid, SDO MSB output  
tsu(SDI-SCLKF)  
th(SDI-SCLKF)  
Setup time, SDI to falling edge of SCLK  
Hold time, SDI to falling edge of SCLK  
8
4
ns  
ns  
Delay time, rising edge of CS/FS to SDO  
3-state  
td(CSR-SDOZ)  
tsu(lastSCLKF-CSR)  
td(SDO-CDI)  
8
ns  
ns  
ns  
Setup time, last falling edge of SCLK  
before rising edge of CS/FS  
10  
Delay time, CDI high to SDO high in  
daisy chain mode  
10-pF Load, chain mode  
23  
(1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.  
(2) See timing diagrams.  
8
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PIN ASSIGNMENTS  
ADS8329  
RSA PACKAGE  
(TOP VIEW)  
ADS8330  
RSA PACKAGE  
(TOP VIEW)  
16 15 14 13  
16 15 14 13  
REF+(REFIN)  
1
2
12 RESERVED  
REF+(REFIN)  
1
2
12 +IN1  
NC  
CONVST  
+VA  
NC  
CONVST  
+VA  
11  
10  
9
11  
10  
9
+VBD  
SCLK  
+VBD  
SCLK  
3
4
3
4
EOC/INT/CDI  
EOC/INT/CDI  
6
7
8
6
7
8
5
5
NC − No internal connection  
9
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SLAS516–DECEMBER 2006  
ADS8329 Terminal Functions  
NO.  
NAME  
AGND  
I/O  
DESCRIPTION  
QFN  
15  
8
–
–
I
Analog ground  
Interface ground  
BDGND  
CONVST  
3
Freezes sample and hold, starts conversion with next rising edge of internal clock  
Status output. If programmed as EOC, this pin is low (default) when a conversion is in  
progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration  
after the end of conversion and a valid data is to be output. The polarity of EOC or INT is  
programmable. This pin can also be used as a chain data input when the device is operated  
in chain mode.  
EOC/ INT/ CDI  
FS/CS  
4
5
O
I
Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave  
select (SS-).  
+IN  
13  
14  
2
I
I
Non inverting input  
-IN  
Inverting input, usually connected to ground  
No connection.  
NC  
–
I
REF+  
REF-  
RESERVED  
SCLK  
SDI  
1
External reference input.  
Connect to AGND through individual via.  
Connect to AGND or +VA  
Clock for serial interface  
Serial data in  
16  
12  
9
I
I
I
6
I
SDO  
+VA  
7
O
Serial data out  
11  
10  
Analog supply, +2.7 V to +5.5 VDC.  
Interface supply  
+VBD  
ADS8330 Terminal Functions  
NO.  
QFN  
15  
NAME  
I/O  
DESCRIPTION  
AGND  
–
–
I
Analog ground  
BDGND  
COM  
8
Interface ground  
14  
Common inverting input, usually connected to ground  
Freezes sample and hold, starts conversion with next rising edge of internal clock  
CONVST  
3
I
Status output. If programmed as EOC, this pin is low (default) when a conversion is in  
progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration  
after the end of conversion and a valid data is to be output. The polarity of EOC or INT is  
programmable. This pin can also be used as a chain data input when the device is operated  
in chain mode.  
EOC/ INT/ CDI  
4
O
FS/CS  
+IN1  
+IN0  
NC  
5
12  
13  
2
I
I
Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface  
Second noninverting input.  
I
First noninverting input  
–
I
No connection.  
REF+  
REF-  
SCLK  
SDI  
1
External reference input.  
16  
9
I
Connect to AGND through individual via.  
Clock for serial interface  
I
6
I
Serial data in (conversion start and reset possible)  
Serial data out  
SDO  
+VA  
7
O
11  
10  
Analog supply, +2.7 V to +5.5 VDC.  
Interface supply  
+VBD  
10  
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SLAS516–DECEMBER 2006  
MANUAL TRIGGER / READ While Sampling  
(use internal CCLK, EOC and INT polarity programmed as active low)  
Nth  
CONVST  
twL(CONVST)  
Nth  
EOC  
(active low)  
tSAMPLE1 = 3 CCLKs min  
tCONV = 18 CCLKs  
tSAMPLE1 = 3 CCLKs min  
INT  
(active low)  
th(CSR-EOS)  
th(CSF-EOC)  
th(CSF-EOS)  
th(CSF-EOC)  
tsu(CSF-EOC)  
tsu(CSF-EOS)  
CS/FS  
SCLK  
1
1 . . . . . . . . . . . . . . . . . . . . 16  
Nth−1th  
td(CSR-EOS) = 20 ns min  
SDO  
SDI  
Nth  
1101b  
1101b  
READ Result  
READ Result  
Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while sampling)  
AUTO TRIGGER / READ While Sampling  
(use internal CCLK, EOC and INT polarity programmed as active low)  
CONVST = 1  
EOC  
(active low)  
Nth  
tCONV = 18 CCLKs  
tSAMPLE2 = 3 CCLKs  
tCONV = 18 CCLKs  
tSAMPLE2 = 3 CCLKs  
INT  
(active low)  
th(CSF-EOS)  
th(CSF-EOC)  
tsu(CSF-EOS)  
tsu(CSF-EOS)  
CS/FS  
SCLK  
SDO  
1 . . . . . . . . . . . . . . . . . . .16  
N − 1th  
1
1 . . . . . . . . . . . . . . . . . . .16  
th(CSF-EOC)  
N − 1th  
Nth  
1110b. . . . . . . . . . . . . .  
CONFIGURE  
1101b  
1101b  
SDI  
READ Result  
READ Result  
Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while sampling)  
11  
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MANUAL TRIGGER / READ While Converting  
(use internal CCLK, EOC and INT polarity programmed as active low)  
N − 1th  
CONVST  
Nth  
twL(CONVST)  
Nth  
N + 1th  
EOC  
(active low)  
tCONV = 18 CCLKs  
tSAMPLE1 = 3 CCLKs min  
INT  
(active low)  
th(CSF-EOS)  
tsu(CSR-EOS)  
tsu(CSF-EOS)  
CS/FS  
tsu(CSF-EOC)  
th(CSF-EOC)  
SCLK  
SDO  
1
1 . . . . . . . . . . . . . . . . . . . .16  
N − 1th  
N th  
1101b  
1101b  
SDI  
READ Result  
READ Result  
Figure 3. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while converting)  
AUTO TRIGGER / READ While Converting  
(use internal CCLK, EOC and INT polarity programmed as active low)  
CONVST = 1  
N + 1th  
EOC  
(active low)  
tCONV = 18 CCLKs  
Nth  
tCONV = 18 CCLKs  
tSAMPLE2 = 3 CCLKs min  
tSAMPLE2 = 3 CCLKs min  
INT  
(active low)  
th(CSF-EOS)  
tsu(CSR-EOS)  
tsu(CSF-EOS)  
th(CSF-EOS)  
th(CSR-EOS)  
CS/FS  
1 . . . . . . . . . . . . . . . . . . 16  
SCLK  
SDO  
tsu(CSR-EOS)  
1 . . . . . . . . . . . . . . . . . . 16  
N−1 th  
1 . . . . . . . . . . . . . . . . . . .16  
??  
N th  
N−1 th  
1110b . . . . . . . . . . . . . . .  
1101b  
1101b  
SDI  
CONFIGURE  
READ Result  
READ Result  
Figure 4. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while converting)  
12  
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15  
14  
1
2
3
4
5
6
7
16  
SCLK  
CS/FS  
t
c(SCLK)  
t
t
t
su(LastSCLK−CSR)  
su(CSF−SCLK1R)  
wH(SCLK)  
t
wL(SCLK)  
t
d(SCLKF−SDOINVALID)  
t
d(CSR−SDOZ)  
t
d(SCLKF−SDOVALID)  
t
d(CSF−SDOVALID)  
Hi−Z  
MSB MSB−1 MSB−2 MSB−3  
MSB−5 MSB−6  
LSB+2 LSB+1 LSB  
MSB−4  
SDO  
SDI  
t
h(SDI−SCLKF)  
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6  
LSB+2 LSB+1  
LSB  
MSB  
t
su(SDI−SCLKF)  
Figure 5. Detailed SPI Transfer Timing  
MANUAL TRIGGER / READ While Sampling  
(use internal CCLK active high, EOC and INT active low, TAG enabled, auto channel select)  
Nth CH0  
Nth CH1  
CONVST  
twL(CONVST)  
twL(CONVST)  
Nth CH0  
EOC  
(active low)  
Nth CH1  
tCONV = 18 CCLKs  
tCONV = 18 CCLKs  
tSAMPLE1 = 3 CCLKs min  
INT  
(active low)  
tsu(CSF-EOS)  
th(CSF-EOC)  
CS/FS  
SCLK  
1 . . . . . . . . . . . . . . . . . . . . . . . 16  
17  
1 . . . . . . . . . . . . . . . . . . . . . . . 16  
17  
td(CSR-EOS) = 20 ns MIN  
Hi−Z  
Hi−Z  
Nth CH0  
SDO  
SDI  
N−1th CH1  
TAG = 0  
TAG = 1  
1101b  
1101b  
READ Result  
READ Result  
Figure 6. Simplified Dual Channel Timing  
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TYPICAL CHARACTERISTICS  
At –40°C to 85°C, Vref [REF+ – (REF–)] = 5 V when +VA = +VBD = 5 V or Vref [REF+ – (REF–)] = 2.5 V when  
+VA = +VBD = 3 V, fSCLK = 42 MHz, or Vref = 2.5 when +VA = +VBD = 2.7 V, fSCLK = 37.8 MHz, fi = DC for DC  
curves, fi = 100 kHz for AC curves with 5-V supply and fi = 10 kHz for AC curves with 3-V supply (unless  
otherwise noted)  
CROSSTALK  
vs  
FREQUENCY  
DIFFERENTIAL NONLINEARITY  
vs  
FREE-AIR TEMPERATURE  
INTEGRAL NONLINEARITY  
vs  
FREE-AIR TEMPERATURE  
2
110  
105  
100  
1
0.8  
1.5  
+VA = 5 V  
+VA = 3 V  
0.6  
0.4  
+VA = 3 V  
1
95  
90  
+VA = 5 V  
+VA = 5 V  
0.5  
0.2  
0
85  
80  
+VA = 3 V  
150  
0
-40 -25 -10  
-40 -25 -10  
5
20 35  
50 65 80  
5
20 35 50 65 80  
0
50  
100  
200  
T
- Free-Air Temperature - °C  
f - Frequency - kHz  
A
T
- Free-Air Temperature - °C  
A
Figure 7.  
Figure 8.  
Figure 9.  
DIFFERENTIAL NONLINEARITY  
vs  
EXTERNAL CLOCK FREQUENCY  
INTEGRAL NONLINEARITY  
vs  
EXTERNAL CLOCK FREQUENCY  
DIFFERENTIAL NONLINEARITY  
vs  
EXTERNAL CLOCK FREQUENCY  
2
1.5  
1
1
0.5  
0
1
0.5  
0
+VA = 5 V  
+VA = 5 V  
+VA = 3 V  
MAX  
MAX  
MAX  
0.5  
0
-0.5  
-1  
MIN  
MIN  
MIN  
-0.5  
-0.5  
-1.5  
-2  
-1  
0.1  
-1  
0.1  
10  
100  
0.1  
1
1
10  
100  
1
10  
100  
External Clock Frequency - MHz  
External Clock Frequency - MHz  
External Clock Frequency - MHz  
Figure 10.  
Figure 11.  
Figure 12.  
14  
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TYPICAL CHARACTERISTICS (continued)  
INTEGRAL NONLINEARITY  
OFFSET VOLTAGE  
vs  
FREE-AIR TEMPERATURE  
OFFSET VOLTAGE  
vs  
SUPPLY VOLTAGE  
vs  
EXTERNAL CLOCK FREQUENCY  
2
1
1
+VA = 3 V  
1.5  
MAX  
0.8  
0.5  
1
0.5  
0
+VA = 5 V  
+VA = 3 V  
0.6  
0.4  
0
-0.5  
-1  
-0.5  
-1  
MIN  
0.2  
0
-1.5  
-2  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
-40 -25 -10  
5
20 35 50 65 80  
0.1  
1
10  
100  
+VA - Supply Voltage - V  
T
- Free-Air Temperature - °C  
External Clock Frequency - MHz  
A
Figure 13.  
Figure 14.  
Figure 15.  
POWER SUPPLY REJECTION  
GAIN ERROR  
vs  
FREE-AIR TEMPERATURE  
GAIN ERROR  
vs  
SUPPLY VOLTAGE  
RATIO  
vs  
SUPPLY RIPPLE FREQUENCY  
0
-0.02  
-0.04  
0.10  
0.05  
0
-80  
-78  
-76  
-74  
+VA = 5 V  
+VA = 3 V  
-0.06  
+VA = 5 V  
-0.05  
-0.10  
-0.08  
-0.10  
-72  
-70  
+VA = 3 V  
-40 -25 -10  
5
20 35 50 65  
80  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
0
20  
40  
60  
80  
100  
T
- Free-Air Temperature - °C  
A
f - Frequency - kHz  
+VA - Supply Voltage - V  
Figure 16.  
Figure 17.  
Figure 18.  
SIGNAL-TO-NOISE AND  
DISTORTION  
SIGNAL-TO-NOISE RATIO  
vs  
TOTALHARMONIC DISTORTION  
vs  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
INPUT FREQUENCY  
-90  
-95  
95  
93  
95  
93  
+VA = 3 V  
+VA = 5 V  
+VA = 5 V  
+VA = 5 V  
91  
89  
91  
89  
-100  
+VA = 3 V  
+VA = 3 V  
-105  
-110  
87  
85  
87  
85  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
f
- Input Frequency - kHz  
f
- Input Frequency - kHz  
f
- Input Frequency - kHz  
i
i
i
Figure 19.  
Figure 20.  
Figure 21.  
15  
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TYPICAL CHARACTERISTICS (continued)  
SIGNAL-TO-NOISE AND  
SPURIOUS FREE DYNAMIC RANGE  
SIGNAL-TO-NOISE RATIO  
vs  
FULL SCALE RANGE  
DISTORTION  
vs  
vs  
INPUT FREQUENCY  
FULL SCALE RANGE  
110  
100  
95  
100  
95  
f = 10 kHz  
i
f = 10 kHz  
i
108  
106  
104  
90  
85  
80  
90  
85  
80  
+VA = 3 V  
+VA = 5 V  
+VA = 3 V  
102  
100  
+VA = 5 V  
+VA = 5 V  
98  
96  
+VA = 3 V  
94  
92  
90  
75  
70  
75  
70  
0
1
2
3
4
5
0
0
20  
40  
60  
80  
100  
3
4
1
2
5
f
- Input Frequency - kHz  
Full Scale Range - V  
Full Scale Range - V  
i
Figure 22.  
Figure 23.  
Figure 24.  
TOTAL HARMONIC DISTORTION  
SPURIOUS FREE DYNAMIC RANGE  
TOTAL HARMONIC DISTORTION  
vs  
vs  
vs  
FULL SCALE RANGE  
FULL SCALE RANGE  
FREE-AIR TEMPERATURE  
-80  
-85  
110  
-90  
-95  
f = 10 kHz  
i
f = 10 kHz  
i
105  
100  
95  
+VA = 5 V  
+VA = 3 V  
+VA = 5 V  
-90  
-95  
-100  
+VA = 3 V  
+VA = 5 V  
90  
-100  
+VA = 3 V  
-105  
-110  
85  
80  
-105  
-110  
1
2
4
0
3
-40 -25 -10  
5
20  
35 50 65 80  
1
5
0
2
3
4
5
Full Scale Range - V  
Full Scale Range - V  
T
- Free-Air Temperature - °C  
A
Figure 25.  
Figure 26.  
Figure 27.  
SIGNAL-TO-NOISE AND  
DISTORTION  
SPURIOUS FREE DYNAMIC RANGE  
SIGNAL-TO-NOISE RATIO  
vs  
FREE-AIR TEMPERATURE  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
110  
95  
93  
95  
93  
91  
+VA = 5 V  
105  
100  
+VA = 3 V  
91  
89  
+VA = 5 V  
+VA = 3 V  
89  
87  
85  
+VA = 5 V  
+VA = 3 V  
95  
90  
87  
85  
-40 -25 -10  
5
20  
35 50 65 80  
-40 -25 -10  
5
20  
35 50 65 80  
-40 -25 -10  
5
20  
35 50 65 80  
T
- Free-Air Temperature - ºC  
T
- Free-Air Temperature - °C  
A
A
T
- Free-Air Temperature - ºC  
A
Figure 28.  
Figure 29.  
Figure 30.  
16  
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TYPICAL CHARACTERISTICS (continued)  
EFFECTIVE NUMBER OF BITS  
INTERNAL CLOCK FREQUENCY  
INTERNAL CLOCK FREQUENCY  
vs  
vs  
vs  
FREE-AIR TEMPERATURE  
SUPPLY VOLTAGE  
FREE-AIR TEMPERATURE  
24  
24  
16  
15.50  
15  
23.5  
23.5  
23  
22.5  
22  
23  
22.5  
22  
+VA = 5 V  
+VA = 3 V  
14.50  
21.5  
21  
21.5  
21  
14  
-40 -25 -10  
5
20 35 50 65 80  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
-40 -25 -10  
5
20  
35 50 65 80  
+VA - Supply Voltage - V  
T
- Free-Air Temperature - ºC  
T
- Free-Air Temperature - ºC  
A
A
Figure 31.  
Figure 32.  
Figure 33.  
ANALOG SUPPLY CURRENT  
ANALOG SUPPLY CURRENT  
ANALOG SUPPLY CURRENT  
vs  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
400  
360  
10  
8
f
= 1 MSPS  
7.5  
7.0  
6.5  
6.0  
5.5  
NAP Mode  
PD Mode  
s
6
4
320  
280  
240  
200  
2
0
5.0  
4.5  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
+VA - Supply Voltage - V  
+VA - Supply Voltage - V  
+VA - Supply Voltage - V  
Figure 34.  
Figure 35.  
Figure 36.  
ANALOG SUPPLY CURRENT  
ANALOG SUPPLY CURRENT  
ANALOG SUPPLY CURRENT  
vs  
FREE-AIR TEMPERATURE  
vs  
vs  
SAMPLE RATE  
SAMPLE RATE  
500  
400  
7.5  
7
f = 1 MSPS  
s
Auto NAP  
7
PD Mode  
+VA = 5 V  
6
6.5  
6
5
4
3
+VA = 5 V  
+VA = 3 V  
300  
200  
+VA = 5 V  
5.5  
5
+VA = 3 V  
2
1
+VA = 3 V  
100  
0
4.5  
4
0
1000  
10  
100  
1
-40 -25 -10  
5
20 35 50 65 80  
1
5
9
13  
17  
Sample Rate - kHz  
T
- Free-Air Temperature - ºC  
A
Sample Rate - kHz  
Figure 37.  
Figure 38.  
Figure 39.  
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TYPICAL CHARACTERISTICS (continued)  
ANALOG SUPPLY CURRENT  
vs  
FREE-AIR TEMPERATURE  
0.4  
NAP Mode  
0.36  
+VA = 5 V  
0.32  
0.28  
+VA = 3 V  
0.24  
0.2  
-40 -25 -10  
5
20 35 50 65 80  
T
- Free-Air Temperature - ºC  
A
Figure 40.  
INL  
1.75  
1.5  
+VA = 5 V  
1.0  
0.5  
0
-0.5  
-1.0  
-1.5  
-1.75  
0
10000  
20000  
30000  
Code  
40000  
50000  
60000  
Figure 41.  
DNL  
1
0.5  
0
+VA = 5 V  
-0.5  
-1  
0
10000  
20000  
30000  
40000  
50000  
60000  
Code  
Figure 42.  
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TYPICAL CHARACTERISTICS (continued)  
INL  
1.75  
1.5  
+VA = 3 V  
1.0  
0.5  
0
-0.5  
-1.0  
-1.5  
-1.75  
0
10000  
20000  
30000  
Code  
40000  
50000  
60000  
Figure 43.  
DNL  
1
+VA = 3 V  
0.5  
0
-0.5  
-1  
0
10000  
20000  
30000  
40000  
50000  
60000  
Code  
Figure 44.  
FFT  
0
5 kHz Input,  
+VA = 3 V,  
-20  
f
= 1 MSPS,  
s
V
= 2.5 V  
-40  
-60  
ref  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 45.  
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TYPICAL CHARACTERISTICS (continued)  
FFT  
0
-20  
10 kHz Input,  
+VA = 3 V,  
f
= 1 MSPS,  
s
V
= 2.5 V  
-40  
ref  
-60  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 46.  
FFT  
0
-20  
-40  
100 kHz Input,  
+VA = 3 V,  
f
= 1 MSPS,  
s
V
= 2.5 V  
ref  
-60  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 47.  
FFT  
0
5 kHz Input,  
+VA = 5 V,  
-20  
-40  
f
= 1 MSPS,  
s
V
= 5 V  
ref  
-60  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 48.  
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TYPICAL CHARACTERISTICS (continued)  
FFT  
20  
0
10 kHz Input,  
+VA = 5 V,  
-20  
f
= 1 MSPS,  
s
V
= 5 V  
ref  
-40  
-60  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 49.  
FFT  
0
100 kHz Input,  
+VA = 5 V,  
-20  
-40  
f
= 1 MSPS,  
s
V
= 5 V  
ref  
-60  
-80  
-100  
-120  
-140  
-160  
0
100  
200  
300  
400  
500  
f - Frequency - kHz  
Figure 50.  
THEORY OF OPERATION  
The ADS8329/30 is a high-speed, low power, successive approximation register (SAR) analog-to-digital  
converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which  
inherently includes a sample/hold function.  
The ADS8329/30 has an internal clock that is used to run the conversion but can also be programmed to run the  
conversion based on the external serial clock, SCLK.  
The ADS8329 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a  
conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a  
conversion is in progress, both +IN and –IN inputs are disconnected from any internal function.  
The ADS8330 has two inputs. Both inputs share the same common pin - COM. The negative input is the same  
as the -IN pin for the ADS8329. The ADS8330 can be programmed to select a channel manually or can be  
programmed into the auto channel select mode to sweep between channel 0 and 1 automatically.  
ANALOG INPUT  
When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the  
internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2 V and AGND + 0.2 V,  
allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a  
range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to 0 V to Vref.  
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input  
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THEORY OF OPERATION (continued)  
voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the  
sample period. After this capacitance has been fully charged, there is no further input current. The source of the  
analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the  
minimum acquisition time (120 ns). When the converter goes into hold mode, the input impedance is greater  
than 1 GΩ.  
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN  
and –IN inputs and the span [+IN – (–IN)] should be within the limits specified. Outside of these ranges,  
converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass  
filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN  
and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may  
result in an offset error, gain error, and linearity error which change with temperature and input voltage.  
Device in Hold Mode  
40 pF  
150 W  
+IN  
4 pF  
4 pF  
+VA  
AGND  
40 pF  
150 W  
−IN  
AGND  
Figure 51. Input Equivalent Circuit  
Driver Amplifier Choice  
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365. An  
RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20 Ω and  
a capacitor of 470 pF are recommended. The input to the converter is a unipolar input voltage in the range 0 V  
to Vref. The minimum -3dB bandwidth of the driving operational amplifier can be calculated to:  
f3db = (ln(2) ×(n+1))/(2π × tACQ  
)
where n is equal to 16, the resolution of the ADC (in the case of the ADS8329/30). When tACQ = 120 ns  
(minimum acquisition time), the minimum bandwidth of the driving amplifier is 15.6 MHz. The bandwidth can be  
relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas  
Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is  
shown in the typical input drive configuration, Figure 52.  
Bipolar to Unipolar Driver  
In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional  
DC bias applied to its + input so as to keep the input to the ADS8329/30 within its rated operating voltage range.  
This configuration is also recommended when the ADS8329/30 is used in signal processing applications where  
good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240  
reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91 dB  
SNR and –96 dB THD at an input frequency of 10 kHz. In case bandpass filters are used to filter the input, care  
should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the  
distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be  
increased to keep the input to the ADS8329/30 large to keep the SNR of the system high. Note that the gain of  
the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the  
AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage  
at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range.  
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THEORY OF OPERATION (continued)  
5 V  
Input  
Signal  
(0 V to 4 V)  
ADS8329/30  
+VA  
20 W  
+IN/(+IN1 or +IN0)  
THS4031  
470 pF  
20 W  
−IN/COM  
50 W  
Figure 52. Unipolar Input Drive Configuration  
5 V  
ADS8329  
1 V DC  
+VA  
20 W  
+IN/(+IN1 or +IN0)  
THS4031  
600 W  
470 pF  
Input  
Signal  
(−2V to 2 V)  
−IN/COM  
600 W  
20 W  
Figure 53. Bipolar Input Drive Configuration  
REFERENCE  
The ADS8329/30 can operate with an external reference with a range from 0.3 V to 5 V. A clean, low noise,  
well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low  
noise band-gap reference like the REF3240 can be used to drive this pin. A 22-µF ceramic decoupling capacitor  
is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as  
possible to the pins of the device. The REF- should be connected to its own via to the analog ground plane with  
the shortest possible distance.  
CONVERTER OPERATION  
The ADS8329/30 has an oscillator that is used as an internal clock which controls the conversion rate. The  
frequency of this clock is 21 MHz minimum. The oscillator is always on unless the device is in the deep  
powerdown state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum  
acquisition (sampling) time takes 3 CCLKs (this is equivalent to 120 ns at 24.5 MHz) and the conversion time  
takes 18 conversion clocks (CCLK) (~780 ns) to complete one conversion.  
The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This  
allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its  
frequency before it is used as the conversion clock (CCLK). For example, with a 42-MHz SCLK this provides a  
21-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the  
external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion is  
selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the  
conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization  
between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which  
results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is  
relaxed.  
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THEORY OF OPERATION (continued)  
The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns.  
Since the ADS8329/30 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to  
be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most  
1 µs (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic  
leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8329/30.  
CFR_D10  
Conversion Clock  
= 1  
= 0  
OSC  
(CCLK)  
SPI Serial  
Clock (SCLK)  
Divider  
1/2  
Figure 54. Converter Clock  
Manual Channel Select Mode  
The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command  
register (CMR). This cycle time can be as short as 4 serial clocks (SCLK).  
Auto Channel Select Mode  
Channel selection can also be done automatically if auto channel select mode is enabled. This is the default  
channel select mode. The dual channel converter, ADS8330, has a built-in 2-to-1 MUX. If the device is  
programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed  
order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for  
auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11  
to 0.  
Start of a Conversion  
The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by  
bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the  
CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common  
CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8329/30  
switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8329/30 requires 18  
conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a  
12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs.  
A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the  
converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK)  
after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case  
the time to complete one acquisition and conversion cycle is 21 CCLKs.  
Table 1. Different Types of Conversion  
MODE  
SELECT CHANNEL  
Auto Channel Select(1)  
START CONVERSION  
Auto Trigger  
Automatic  
No need to write channel number to the CMR. Use internal sequencer for the  
ADS8330.  
Start a conversion based on the  
conversion clock CCLK.  
Manual Channel Select  
Manual Trigger  
Manual  
Write the channel number to the CMR.  
Start a conversion with CONVST.  
(1) Auto channel select should be used with auto trigger and also with the TAG bit enabled.  
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Status Output EOC/INT  
When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following  
manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is  
programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has  
ended. The EOC output goes low for 3 conversion clocks (CCLK) after the previous rising edge of EOC, if auto  
trigger is programmed.  
This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is  
equal to the conversion time. This status pin can be used as INT. (CFR_D[7:6] = 1, 0) which is set LOW at the  
end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either  
function (EOC or INT), is programmable through CFR_D7.  
Power-Down Modes  
The ADS8329/30 has a comprehensive built-in power-down feature. There are three power-down modes: Deep  
power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are  
enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup  
command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works  
slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance  
(EOC) puts the device into auto nap powerdown. The beginning of sampling resumes operation of the converter.  
The contents of the configuration register is not affected by any of the power-down modes. Any ongoing  
conversion when nap or deep powerdown is activated is aborted.  
100  
10  
1
0.1  
20  
10020  
20020  
30020  
40020  
Settling Time − ns  
Figure 55. Typical Analog Supply Current Drop vs Time After Powerdown  
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Deep Power-Down Mode  
Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in  
deep power-down mode, all blocks except the interface are in powerdown. The external SCLK is blocked to the  
analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this  
mode, power dissipation falls from 5 mA to 1 µA in 2 µs. The wake-up time after a powerdown is 1 µs. When bit  
D2 in the configuration register is set to 0, the device is in deep powerdown. Setting this bit to 1 or sending a  
wake-up command can resume the converter from the deep power-down state.  
Nap Mode  
In nap mode the ADS8329/230 turns off biasing of the comparator and the mid-volt buffer. In this mode power  
dissipation falls from 7 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up  
(resume) time from nap power-down mode is 3 CCLKs (120 ns with a 24.5-MHz conversion clock). As soon as  
the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the  
conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap  
power-down state.  
Auto Nap Mode  
Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually  
powered down and the method to wake up the device. Configuration register bit D4 is only used to  
enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has  
finished, which means the end of conversion activates auto nap powerdown mode. Power dissipation falls from  
7 mA in normal mode to about 0.3 mA in 200 ns. A CONVST resumes the device and turns biasing on again in  
3 CCLKs (120 ns with a 24.5-MHz conversion clock). The device can also be woken up by disabling auto nap  
mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb, wake up  
command or the set default mode command 1111b can also wake up the device from auto nap powerdown.  
NOTE:  
1. This wake-up command is the word 1011b in the command word. This command sets  
bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command  
does remove the device from either one of these power-down states, deep/nap/auto  
nap powerdown.  
2. Wake-up time is defined as the time between when the host processor tries to wake up  
the converter and when a convert start can occur.  
Table 2. Power-Down Mode Comparisons  
TYPE OF  
POWERDOWN  
POWER  
CONSUMPTION  
ACTIVATED BY  
ACTIVATION TIME  
RESUME POWER BY  
RESUME TIME  
ENABLE  
Normal operation  
Deep powerdown  
7 mA/5.1 mA  
7 nA/1 nA  
Setting CFR  
Setting CFR  
100 µs  
Woken up by command 1011b  
1 µs  
Set CFR  
Woken up by command 1011b to achieve 6.6 mA  
since (1.3 + 12)/2 = 6.6  
Nap powerdown  
0.3 mA/0.2 mA  
200 µs  
200 µs  
3 CCLKs  
3 CCLKs  
Set CFR  
Set CFR  
Woken up by CONVST, any channel select  
command, default command 1111b, or wake up  
command 1011b.  
EOC (end of  
conversion)  
Auto nap powerdown  
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N
N+1  
Converter  
CONVST  
State  
Converter  
State  
N+1 −th Sampling  
N −th Conversion  
N+1 −th Conversion  
Read While Converting  
CS  
20 ns MIN  
Read N−1 −th Result  
1 CCLK MIN  
(For Read Result)  
Read While Sampling  
0 ns MIN  
20 ns MIN  
CS  
Read N −th Result  
(For Read Result)  
Figure 56. Read While Converting vs Read While Sampling (Manual trigger)  
Manual Trigger  
CONVST  
N
N+1  
Converter  
State  
Resume  
N −th Sampling  
>=3CCLK  
N −th Conversion  
=18 CCLK  
Activation  
Resume N+1 −th Sampling N+1 −th Conversion Activation  
>=3CCLK  
=18 CCLK  
20 ns MIN  
20 ns MIN  
1 CCLK MIN  
Read N−1 −th  
Result  
Read While Converting  
CS  
Read N −th  
Result  
20 ns MIN  
20 ns MIN  
Read While Sampling  
CS  
0 ns MIN  
20 ns MIN  
20 ns MIN  
20 ns MIN  
Read N−1 −th  
Result  
Read N −th  
Result  
20 ns MIN  
Figure 57. Read While Converting vs Read While Sampling with Deep or Nap Powerdown  
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40 ns MIN  
Manual Trigger Case 1  
CONVST  
N
N+1  
EOC  
(programmed  
Active Low)  
Converter  
N+1 −th Conversion  
=18 CCLK  
Resume  
POWERDOWN  
POWERDOWN  
N −th Sampling  
>=3CCLK  
N −th Conversion  
=18 CCLK  
Resume N+1 −th Sampling  
>=3CCLK  
State  
6 CCLKs  
6 CCLKs  
Read While Converting  
CS  
20 ns MIN  
20 ns MIN  
Read N −th  
Result  
Read N−1 −th  
Result  
20 ns MIN  
20 ns MIN  
1 CCLK MIN  
1 CCLK MIN  
20 ns MIN  
Read While Sampling  
CS  
0 ns MIN  
Read N −th  
Result  
Read N−1 −th  
Result  
20 ns MIN  
40 ns MIN  
N+1  
Manual Trigger Case 2 (wake up by CONVST)  
CONVST  
N
EOC  
(programmed  
Active Low)  
Converter  
State  
POWER  
DOWN  
POWER  
DOWN  
Resume  
N −th Sampling  
>=3CCLK  
N −th Conversion  
=18 CCLK  
N+1 −th Sampling N+1 −th Conversion  
Resume  
>=3CCLK  
=18 CCLK  
Read While Converting  
CS  
20 ns MIN  
20 ns MIN  
Read N −th  
Result  
Read N−1 −th  
Result  
20 ns MIN  
20 ns MIN  
20 ns MIN  
Read While Sampling  
0 ns MIN  
20 ns MIN  
Read N −th  
Result  
Read N−1 −th  
Result  
CS  
20 ns MIN  
20 ns MIN  
Figure 58. Read While Converting vs Read While Sampling with Auto Nap Powerdown  
Total Acquisition + Conversion Cycle Time:  
Automatic:  
Manual:  
= 21 CCLKs  
≥ 21 CCLKs  
Manual + deep powerdown: ≥ 4SCLK + 100 µs + 3 CCLK + 18 CCLK +16 SCLK + 1 µs  
Manual + nap powerdown: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK  
Manual + auto nap  
powerdown:  
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume)  
Manual + auto nap  
powerdown:  
≥ 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume)  
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DIGITAL INTERFACE  
The serial interface is compatible with Motorola SPI. The serial clock is designed to accommodate the latest  
high-speed processors with an SCLK up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The  
internal data register content which is made available to the output register at the EOC presented on the SDO  
output pin at the falling edge of FS/CS. This is the MSB. Output data are changed at the falling edge of SCLK so  
that the host processor can read it at the next rising edge. Serial data input is latched at the falling edge of  
SCLK.  
The complete serial I/O cycle starts with the first rising edge of SCLK after the falling edge of FS/CS and ends  
16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with both CPOL = 0 or  
CPOL = 1. The interface ignores data if a falling edge arrives before the first rising edge. This means the falling  
edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where  
SCLK may be high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.  
NOTE:  
There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read  
mode combination. See Table 3 for details.  
Internal Register  
The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration  
data register (CFR).  
Table 3. Command Set Defined by Command Register (CMR)(1)  
WAKE UP FROM  
AUTO NAP  
MINIMUM SCLKs  
REQUIRED  
D[15:12]  
HEX  
COMMAND  
D[11:0]  
R/W  
0000b  
0001b  
0010b  
0011b  
0100b  
0101b  
0110b  
0111b  
1000b  
1001b  
1010b  
1011b  
1100b  
1101b  
1110  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
8h  
9h  
Ah  
Bh  
Ch  
Dh  
Eh  
Fh  
Select analog input channel 0(2)  
Select analog input channel 1(2)  
Reserved  
Don't care  
Y
Y
Y
Y
Y
Y
Y
Y
–
4
4
–
–
Don't care  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Don't care  
Don't care  
Don't care  
CFR Value  
4
–
Reserved  
4
–
Reserved  
4
–
Reserved  
4
–
Reserved  
4
–
Reserved  
4
–
Reserved  
–
–
Reserved  
–
–
–
Reserved  
–
–
–
Wake up  
Y
–
4
W
R
R
W
W
Read CFR  
16  
16  
16  
4
Read data  
–
Write CFR  
–
1111b  
Default mode (load CFR with default value) Don't care  
Y
(1) When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are  
supplied) of the previous conversion result.  
(2) These two commands apply to the ADS8330 only.  
WRITING TO THE CONVERTER  
There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR  
plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes  
effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 5 for exceptions  
that require more than 16 SCLKs).  
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Configuring the Converter and Default Mode  
The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A  
write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th  
falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK.  
A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least  
four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of  
SCLK.  
CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8329 and is always read as a  
0). The same default values apply for the CFR after a power-on reset (POR) and SW reset.  
READING THE CONFIGURATION REGISTER  
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is  
similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin.  
The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents.  
Table 4. Configuration Register (CFR) Map  
SDI BIT  
DEFINITION  
CFR - D[11 - 0]  
Channel select mode  
D11 Default = 1  
0: Manual channel select enabled. Use channel select commands to  
access a different channel.  
1: Auto channel select enabled. All channels are sampled and  
converted sequentially until the cycle after this bit is set to 0.  
Conversion clock (CCLK) source select  
0: Conversion clock (CCLK) = SCLK/2  
D10 Default = 1  
1: Conversion clock (CCLK) = Internal OSC  
Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored.  
D9 Default = 1  
D8 Default = 1  
D7 Default = 1  
0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST  
Don't care  
Don't care  
Pin 10 polarity select when used as an output (EOC/INT)  
0: EOC Active high / INT active high  
Pin 10 function select when used as an output (EOC/INT)  
0: Pin used as INT  
1: EOC Active low / INT active low  
1: Pin used as EOC  
D6 Default = 1  
D5 Default = 1  
D4 Default = 1  
D3 Default = 1  
D2 Default = 1  
Pin 10 I/O select for chain mode operation  
0: Pin 10 is used as CDI input (chain mode enabled)  
1: Pin 10 is used as EOC/INT output  
Auto nap powerdown enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0.  
0: Auto nap powerdown enabled (not activated) 1: Auto nap powerdown disabled  
Nap powerdown (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command.  
0: Enable/activate device in nap powerdown  
1: Remove device from nap powerdown (resume)  
Deep powerdown. This bit is set to 1 automatically by wake-up command.  
0: Enable/activate device in deep powerdown  
1: Remove device from deep powerdown (resume)  
D1 Default =  
0: ADS8329  
1: ADS8330  
TAG bit enable. This bit is ignored by the ADS8329 and is alway read 0.  
0: TAG bit disabled.  
1: TAG bit output enabled. TAG bit appears at the 17th SCLK.  
1: Normal operation  
Reset  
D0 Default = 1  
0: System reset  
READING CONVERSION RESULT  
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the  
output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out  
via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling  
(EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or  
the end of the 3rd conversion clock (CCLK) after EOC if auto trigger is used.  
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The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion  
clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data is corrupt.  
If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed  
after the end of a conversion, the current conversion result is read.  
The conversion result is 16-bit data in straight binary format as shown in Table 4. Generally 16 SCLKs are  
necessary, but there are exceptions where more than 16 SCLKS are required (see Table 5). Data output from  
the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus  
all zeros. SDO remains low until FS/CS is brought high again.  
SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.  
NOTE:  
Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion  
of the conversion result is output at the SDO pin. The number of bits depends on how  
many SCLKs are supplied. For example, a manual select channel command cycle  
requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The  
exception is SDO outputs all 1s during the cycle immediately after any reset (POR or  
software reset).  
If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out  
all 16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is  
better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in auto nap mode).  
Table 5. Ideal Input Voltages and Output Codes  
DESCRIPTION  
Full scale range  
ANALOG VALUE  
DIGITAL OUTPUT  
STRAIGHT BINARY  
Vref  
Least significant bit (LSB)  
Full scale  
Vref/65536  
+Vref– 1 LSB  
Vref/2  
BINARY CODE  
HEX CODE  
FFFF  
1111 1111 1111 1111  
1000 0000 0000 0000  
0111 1111 1111 1111  
0000 0000 0000 0000  
Midscale  
8000  
Midscale – 1 LSB  
Zero  
Vref/2– 1 LSB  
0 V  
7FFF  
0000  
TAG Mode  
The ADS8330 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the  
converted result. An address bit is added after the LSB read out from SDO indicating which channel the result  
came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter  
requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because  
of the additional TAG bit.  
Chain Mode  
The ADS8329/30 can operate as a single converter or in a system with multiple converters. System designers  
can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain  
when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a  
secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is  
chain mode operation. A typical connection of three converters is shown in Figure 59.  
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Micro Controller  
GPIO2 GPIO3  
INT  
GPIO1  
SDOSCLK  
SDI  
SDI  
CONVST  
CONVST  
CONVST  
SDO  
SCLK  
SCLK  
SCLK  
SDI  
CS  
SDI  
CS  
CS  
ADS8329  
#1  
ADS8329  
#2  
ADS8329  
#3  
SDO  
CDI  
SDO  
CDI  
EOC/INT  
Program device #1 CFR_D[7:5] = XX0b Program device #2 and #3 CFR_D[7:5] = XX1b  
Figure 59. Multiple Converters Connected Using Chain Mode  
When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest  
of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the  
CDI input data goes straight to the output register, therefore the serial input data passes through the converter  
with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for  
detailed timing. In this timing the conversion in each converters are done simultaneously.  
Cascaded Manual Trigger/Read While Sampling  
(Use internal CCLK, EOC active low, and INT active low) CS held  
low during the N times 16 bits transfer cycle.  
CONVST #1,  
CONVST #2,  
CONVST #3  
Nth  
EOC #1  
(active low)  
tSAMPLE1 = 3 CCLKs min  
tCONV = 18 CCLKs  
INT #3  
(active low)  
td(CSR-EOS) = 20 ns min  
CS/FS #1  
SCLK #1,  
SCLK #2,  
SCLK #3  
1 . . . . . . . . . . . . . . . . . . 16  
1 . . . . . . . . . . . . . . . . . . 16  
1 . . . . . . . . . . . . . . . . . . 16  
Hi-Z  
Hi-Z  
SDO #1,  
CDI #2  
Nth from #1  
td(CSR-EOS) = 20 ns min  
CS/FS #2,  
CS/FS #3  
td(SDO-CDI)  
SDO #2,  
CDI #3  
Hi-Z  
Hi-Z  
Hi-Z  
N − 1th from #2  
Nth from #1  
Nth from #1  
Nth from #1  
td(SDO-CDI)  
Hi-Z  
SDO #3  
Nth from #3  
N − 1th from #2  
SDI #1,  
SDI #2,  
SDI #3  
1110............  
1101b  
1101b  
CONFIGURE  
READ Result  
READ Result  
Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS  
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Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The  
different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).  
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select  
signal.  
Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and  
so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example,  
the same data from the converter is going to be shown repeatedly.  
Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the  
same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired  
result.  
Cascaded Manual Trigger/Read While Sampling  
(Use internal CCLK, EOC, and INT polarity programmed as active low)  
CS held low during the N times 16 bits transfer cycle.  
These SCLKs are optional.  
CONVST #1,  
CONVST #2,  
CONVST #3  
Nth  
EOC #1  
(active low)  
tSAMPLE1 = 3 CCLKs min  
tCONV = 18 CCLKs  
INT #1  
(active low)  
td(EOS-CSF) = 20 ns min  
td(CSR-EOS) = 20 ns min  
CS/FS #1  
SCLK #1,  
SCLK #2,  
SCLK #3  
1
16  
1
16  
=
1
16  
SDO #1,  
CDI #2  
Nth from #1  
Nth from #1  
Nth from #1  
td(EOS-CSF)  
20 ns min  
td(CSR-EOS)  
20 ns min  
=
CS/FS #2  
SCLK #2,  
SDO #2,  
CDI #3  
N − 1th from #2  
Nth from #1  
t
Nth from #1  
t
=
=
d(EOS-CSF)  
d(CSR-EOS)  
20 ns min  
CS/FS #3  
SDO #3  
20 ns min  
SDI #1,  
SDI #2,  
SDI #3  
N − 1th from #2  
Nth from #1  
Nth from #3  
1110............  
1101b  
1101b  
CONFIGURE  
READ Result  
READ Result  
Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS  
Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters  
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data  
downstream.  
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Cascaded Manual Trigger/Read While Sampling  
(Use internal CCLK, EOC active low and INT active low)  
CS held low during the N times 16 bits transfer cycle.  
Note : old data shown.  
CONVST #1,  
CONVST #3  
CONVST #2 = 1  
Nth  
EOC #1  
(active low)  
tSAMPLE1 = 3 CCLKs min  
tCONV = 18 CCLKs  
INT #1  
(active low)  
td(CSR-EOS) = 20 ns min  
CS/FS #1  
SCLK #1,  
SCLK #2,  
1 . . . . . . . . . . . . . . . . . .16  
1 . . . . . . . . . . . . . . . . . .16  
1 . . . . . . . . . . . . . . . . . .16  
SCLK #3  
Hi-Z  
Hi-Z  
SDO #1,  
CDI #2  
Nth from #1  
td(CSR-EOS) = 20 ns min  
CS/FS #2,  
CS/FS #3  
td(SDO-CDI)  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
SDO #2,  
CDI #3  
Nth from #1  
N − 1th from #2  
td(SDO-CDI)  
SDO #3  
SDI #1,  
SDI #2,  
SDI #3  
N − 1th from #2  
Nth from #3  
Nth from #1  
1110............  
1101b  
1101b  
CONFIGURE  
READ Result  
READ Result  
Figure 62. Simplified Cascade Timing (Separate CONVST)  
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG  
bit, chain mode, and the way a channel is selected, i.e., auto channel select. This is listed in Table 6.  
Table 6. Required SCLKs For Different Read Out Mode Combinations  
CHAIN MODE  
ENABLED CFR.D5 SELECT CFR.D11  
AUTO CHANNEL  
NUMBER OF SCLK PER SPI  
READ  
TAG ENABLED CFR.D1  
TRAILING BITS  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16  
≥17  
16  
None  
MSB is TAG bit plus zero(s)  
None  
≥17  
16  
TAG bit plus 7 zeros  
None  
24  
TAG bit plus 7 zeros  
None  
16  
24  
TAG bit plus 7 zeros  
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SCLK skew between converters and data path delay through the converters configured in chain mode can affect  
the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be  
necessary to slow down the SCLK when the devices are configured in chain mode.  
ADS8329  
#3  
Serial data  
output  
CDI  
SDO  
Logic  
Delay  
Plus PAD  
2.7 ns  
Logic  
D
Q
Delay  
Plus PAD  
8.3 ns  
CLK  
ADS8329  
#2  
CDI  
SDO  
Logic  
Delay  
Logic  
Delay  
D
Q
CLK  
Plus PAD  
2.7 ns  
Plus PAD  
8.3 ns  
# 1  
ADS8329  
CDI  
SDO  
Logic  
Delay  
Plus PAD  
2.7 ns  
Logic  
D
Q
Delay  
Plus PAD  
8.3 ns  
Serial data  
input  
CLK  
SCLK input  
Figure 63. Typical Delay Through Converters Configured in Chain Mode  
RESET  
The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These  
two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to  
the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state  
machine is reset to the power-on state.  
SW RESET  
CDI  
POR  
SET  
SAR Shift  
Register  
Intermediate  
Latch  
Output  
Register  
SDO  
SCLK  
Conversion Clock  
EOC  
Latched by Falling Edge of CS  
Latched by End Of  
Conversion  
CS  
EOC  
Figure 64. Digital Output Under Reset Condition  
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APPLICATION INFORMATION  
TYPICAL CONNECTION  
Analog +5 V  
4.7 mF  
AGND  
Ext Ref Input  
Analog Input  
22 mF  
AGND  
+VA REF+ REF− AGND IN+ IN−  
FS/CS  
SDO  
SDI  
Interface  
Supply  
+1.8 V  
Host  
Processor  
SCLK  
ADS8329  
BDGND  
CONVST  
4.7 mF  
+VBD  
EOC/INT  
Figure 65. Typical Circuit Configuration  
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PACKAGING INFORMATION  
Orderable Device  
ADS8329IBRSAR  
ADS8329IBRSARG4  
ADS8329IBRSAT  
ADS8329IBRSATG4  
ADS8329IRSAR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
QFN  
RSA  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
QFN  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
RSA  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
ADS8329IRSARG4  
ADS8329IRSAT  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
ADS8329IRSATG4  
ADS8330IBRSAR  
ADS8330IBRSARG4  
ADS8330IBRSAT  
ADS8330IBRSATG4  
ADS8330IRSAR  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
ADS8330IRSARG4  
ADS8330IRSAT  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
ADS8330IRSATG4  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
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Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Jan-2007  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 2  
IMPORTANT NOTICE  
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