ADS8361IRHBT [BB]
Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER; 双通道， 500KSPS ， 16位， 2 + 2通道，同步采样模拟数字转换器
| 型号： | ADS8361IRHBT |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总23页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8361
ADS8361
A
D
S
8
3
6
1
SBAS230C – AUGUST 2002 – REVISED SEPTEMBER 2004
Dual, 500kSPS, 16-Bit, 2 + 2 Channel,
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS8361 is a dual, 16-bit, 500kSPS, Analog-to-Digital
(A/D) converter with four fully differential input channels grouped
into two pairs for high-speed, simultaneous signal acquisition.
Inputs to the sample-and-hold amplifiers are fully differential
and are maintained differentially to the input of the A/D con-
verter. This provides excellent common-mode rejection of
80dB at 50kHz, which is important in high-noise environments.
● 2 SIMULTANEOUS 16-BIT DACs
● 4 FULLY DIFFERENTIAL INPUT CHANNELS
● 2µs THROUGHPUT PER CHANNEL
● 4µs TOTAL THROUGHPUT FOR FOUR CHANNELS
● LOW POWER: 150mW
● INTERNAL REFERENCE
● FLEXIBLE SERIAL INTERFACE
● 16-BIT UPGRADE TO THE 12-BIT ADS7861
● PIN COMPATIBLE WITH THE ADS7861
The ADS8361 offers a high-speed, dual serial interface and
control inputs to minimize software overhead. The output data
for each channel is available as a 16-bit word. The ADS8361
is offered in SSOP-24 and QFN-32 (5x5) packages and is fully
specified over the –40°C to +85°C operating range.
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
CH A0+
SAR
CH A0–
COMP
SHA
CDAC
SERIAL DATA A
CH A1+
SERIAL DATA B
M0
CH A1–
M1
REFIN
A0
Serial
Interface
Internal
2.5V
Reference
REFOUT
CLOCK
CS
CH B0+
RD
CH B0–
SHA
COMP
BUSY
CDAC
CONVST
CH B1+
CH B1–
SAR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002-2004, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Absolute Maximum Ratings over operating free-air temperature (unless other-
wise noted)(1)
.
Supply Voltage, AGND to AVDD ............................................. –0.3V to 7V
Supply Voltage, BGND to BVDD ............................................. –0.3V to 7V
Analog Input Voltage ................................. AGND – 0.3V to AVDD + 0.3V
Reference Input Voltage ........................... AGND – 0.3V to AVDD + 0.3V
Digital Input Voltage .................................. BGND – 0.3V to BVDD + 0.3V
Ground Voltage Differences, AGND to BGND ................................ ±0.3V
Voltage Differences, BVDD to AGND ..................................... –0.3V to 7V
Input Current to Any Pin Except Supply ......................... –20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C
Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C
Storage Temperature Range, TSTG .................................. –65°C to 150°C
Lead Temperature 1.6mm (1/16 inch) from Case for 10s ...................... 260°C
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
completedevicefailure.Precisionintegratedcircuitsmaybemore
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under "recommended operating conditions" is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO MISSING
CODES
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ERROR (LSB) PACKAGE-LEAD DESIGNATOR(1)
ADS8361
±8
14
SSOP-24
DBQ
–40°C to +85°C
ADS8361IDBQ
Rails, 56
"
"
"
"
"
"
ADS8361IDBQR
Tape and Reel, 2500
ADS8361
±8
"
14
"
QFN-32
RHB
"
–40°C to +85°C
ADS8361IRHBT
ADS8361IRHBR
Tape and Reel, 250
Tape and Reel, 3000
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
CONDITIONS
MIN
NOM
MAX
UNITS
Supply Voltage, AGND to AVDD
Supply Voltage, BGND to BVDD
4.75
2.7
4.5
1.2
2.2
0
5
5.25
3.6
V
V
Low-Voltage Levels
5V Logic Levels
5
5.5
V
Reference Input Voltage
2.5
2.5
2.6
V
Operating Common-Mode Signal
Analog Inputs
–IN
2.8
V
+IN – (–IN)
±VREF
105
V
Operating Junction Temperature Range
TJ
–40
°C
PACKAGE DISSIPATION RATING
DERATING FACTOR
TA ≤ 25°C
TA ≤ 70°C
TA = 85°C
PACKAGE
RθJC
RθJA
ABOVE TA = 25°C
POWER RATING
POWER RATINGQ
POWER RATING
SSOP-24
28.5°C/W
88°C/W
11.364mW/°C
27.25mW/°C
1420mW
2725mW
909mW
738mW
QFN-32 (5x5)
1.007°C/W
36.7°C/W
1499mW
1090mW
EQUIVALENT INPUT CIRCUIT
AVDD
BVDD
C(SAMPLE) = 25pF
RON = 20Ω
AIN
DIN
AGND
BGND
Diode Turn on Voltage: 0.35V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
ADS8361
2
SBOS230C
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to 85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500 kSPS,
unless otherwise noted.
ADS8361
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNITS
ANALOG INPUT
Full-Scale Range(2)
(FSR)
+IN – (–IN)
±VREF
2.8
V
V
Ω
pF
nA
Ω
pF
dB
dB
Operating Common-Mode Signal
Input Switch Resistance
Input Capacitance
Input Leakage Current
Differential Input Switch Resistance
Differential Input Capacitance
2.2
–IN = VREF
–IN = VREF
–IN = VREF
20
25
±1
40
15
84
80
Common-Mode Rejection Ratio
(CMRR)
At DC
VIN = ±1.25Vp-p at 50kHz
DC ACCURACY
Resolution
16
14
Bits
Bits
LSB(3)
LSB
LSB
mV
mV
ppm/°C
%
No Missing Code
Integral Linearity Error
Integral Linearity Match
Differential Nonlinearity
Bipolar Offset Error
Bipolar Offset Error Match
Bipolar Offset Error Drift
Gain Error(6)
(NMC)
(INL)
±3
4
+1.5(4)
±0.5
0.5
±8
Channel 0/1, Same A/D
Channel 0/1, Same A/D
(DNL)
(VOS
)
±2
1
(TCVOS
(GERR
)
)
0.4
±0.05
0.05
20
60
–70
±0.5
0.15
Gain Error Match
Gain Error Drift
Noise
%
(TCGERR
)
ppm/°C
µVrms
dB
Power-Supply Rejection Ratio
(PSRR)
4.75V < AVDD < 5.25V, with
External Reference, at DC
SAMPLING DYNAMICS
Conversion Time per A/D
Acquisition Time
(tCONV
(tAQ
)
)
100kHz ≤ fCLK ≤ 10MHz
1.6
400
160
µs
ns
fCLK = 10MHz
Throughout Rate
Aperture Delay
500
5
kSPS
ns
Aperture Delay Matching
Aperture Jitter
100
50
ps
ps
Clock Frequency
0.1
10
MHz
AC ACCURACY
Total Harmonic Distortion
Spurious-Free Dynamic Range
Signal-to-Noise Ratio
Signal-to-Noise + Distortion
Channel-to-Channel Isolation
(THD)
(SFDR)
(SNR)
VIN = ±2.5Vp-p at 10kHz
VIN = ±2.5Vp-p at 10kHz
VIN = ±2.5Vp-p at 10kHz
VIN = ±2.5Vp-p at 10kHz
VIN = ±2.5Vp-p at 10kHz
–94
94
83
83
96
dB
dB
dB
dB
dB
(SINAD)
VOLTAGE REFERENCE OUTPUT
Reference Voltage Ouput
Initial Accuracy
(VOUT
)
2.475
2.5
2.525
±1
V
%
Output Voltage Temperature Drift (dVOUT/dT)
Output Voltage Noise
±20
10
12
60
10
ppm/°C
µVp-p
µVrms
dB
µA
mA
f = 0.1Hz to 10Hz, CL = 10µF
f = 10Hz to 10kHz, CL = 10µF
Power-Supply Rejection Ratio
Output Current
(PSRR)
(IOUT
)
)
Short-Circuit Current
Turn On Settling Time
(ISC
0.5
100
to 0.1% at CL = 0
µs
VOLTAGE REFERENCE INPUT
Reference Voltage Input
Reference Input Resistance
Reference Input Capacitance
Reference Input Current
(VIN
)
1.2
100
2.5
5
2.6
1
V
MΩ
pF
µA
NOTES: (1) All Values are at TA = 25°C. (2) Ideal input span; does not include gain or offset error. (3) LSB means Least Significant Bit, with VREF equal to +2.5V;
1LSB = 76µV. (4) Specified for 14-bit no missing code. (5) Specified for 15-bit no missing code. (6) Measured relative to an ideal, full-scale input (+IN – (–IN)) of
4.9999V. Thus, gain error does not include the error of the internal voltage reference.
ADS8361
SBOS230C
3
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to 85°C, AVDD = 5V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500 kSPS, unless otherwise
noted.
ADS8361
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNITS
DIGITAL INPUTS(2)
Logic Family
CMOS
High-Level Input Voltage
Low-Level Input Voltage
Input Current
(VIH
(VIL)
(IIN
(CI)
)
0.7 • VDD
–0.3
VDD + 0.3
0.3 • VDD
±50
V
V
nA
pF
)
VI = BVDD or BGND
Input Capacitance
5
DIGITAL OUTPUTS(2)
Logic Family
CMOS
High-Level Output Voltage
Low-Level Output Voltage
High-Impedance-State Output Current (IOZ
Output Capacitance
Load Capacitance
Data Format
(VOH
(VOL
)
)
)
BVDD = 4.5V, IOH = –100µA
BVDD = 4.5V, IOH = –100µA
CS = BVDD, VI = BVDD or BGND
4.44
V
V
nA
pF
pF
pF
0.5
±50
(CO)
(CL)
5
30
Binary Two’s Complement
DIGITAL INPUTS(3)
Logic Family
LVCMOS
High-Level Input Voltage
Low-Level Input Voltage
Input Current
(VIH
(VIL)
(IIN
(CI)
)
BVDD = 3.6V
BVDD = 2.7V
VI = BVDD or BGND
2
–0.3
VDD + 0.3
0.8
±50
V
V
nA
pF
)
Input Capacitance
5
DIGITAL OUTPUTS(3)
Logic Family
LVCMOS
High-Level Output Voltage
Low-Level Output Voltage
High-Impedance-State Output Current (IOZ
Output Capacitance
Load Capacitance
Data Format
(VOH
(VOL
)
)
)
BVDD = 2.7V, IOH = –100µA
BVDD = 2.7V, IOH = –100µA
CS = BVDD, VI = BVDD or BGND
VDD – 0.2
V
V
nA
pF
pF
pF
0.2
±50
(CO)
(CL)
5
30
Binary Two’s Complement
POWER SUPPLY
Analog Supply Voltage
Digital Supply Voltage
(AVDD
(BVDD
)
)
4.75
2.7
4.5
5.25
3.6
5.5
35
1(4)
1(4)
200
200
V
V
V
mA
µA
µA
mW
mW
Low-Voltage Levels
5V Logic Levels
Analog Operating Supply Current (AIDD
Digital Operating Supply Current
)
(BIDD
)
BVDD = 3V
BVDD = 5V
BVDD = 3V
BVDD = 5V
Power Dissipation
150
150
NOTES: (1) All Values are at TA = 25°C. (2) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (3) Applies for 3.0V nominal supply: BVDD
(min) = 2.7V and BVDD (max) = 3.6V. (4) No clock active (static).
ADS8361
4
SBOS230C
www.ti.com
BASIC CIRCUIT CONFIGURATION
+
10µF
0.1µF
ADS8361
+2.7V to +5.5V Digital Supply
1
2
3
4
5
6
7
8
9
BGND
BVDD 24
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
SERIAL DATA A 23
SERIAL DATA B 22
BUSY 21
CLOCK 20
CS 19
BUSY Output
Clock Input
Chip Select
Read Input
RD 18
Conversion Start
A0 Address Select
M0 Address Select
M1 Address Select
+5V Analog Supply
CONVST 17
A0 16
10 REFIN
11 REFOUT
12 AGND
M0 15
+
10µF
0.1µF
M1 14
AVDD 13
+
10µF
0.1µF
TRUTH TABLE
M0
0
M1
0
A0
0
TWO-CHANNEL/FOUR-CHANNEL OPERATION
DATA ON SERIAL OUTPUTS
CHANNELS CONVERTED
A0 and B0
Two-Channel
Two-Channel
Two-Channel
Two-Channel
Four-Channel
Four-Channel
A and B
A and B
A Only
0
0
1
A1 and B1
0
1
0
A0 and B0
0
1
1
A Only
A1 and B1
1
0
X
X
A and B
A Only
Sequential
1
1
Sequential
NOTE: X = Don’t Care.
ADS8361
SBOS230C
5
www.ti.com
PIN CONFIGURATION
Top View
QFN
Top View
SSOP
ADS8361
1
2
3
4
5
6
7
8
9
BGND
BVDD 24
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
SERIAL DATA A 23
SERIAL DATA B 22
BUSY 21
CLOCK 20
CS 19
1
2
3
4
5
6
7
8
24 SERIAL DATA B
23 BUSY
22 CLOCK
21 CS
CH B1+
CH B1−
CH B0+
CH B0−
CH A1+
CH A1−
CH A0+
CH A0−
ADS8361
RD 18
20 RD
CONVST 17
A0 16
19 CONVST
18 A0
17 M0
10 REFIN
11 REFOUT
12 AGND
M0 15
M1 14
AVDD 13
NOTE: NC = Not Connected.
PIN DESCRIPTIONS
SSOP QFN
PIN
PIN
NAME
DESCRIPTION
Digital I/O Ground. Connect directly to analog ground (pin 12).
1
2
28
1
BGND
CH B1+ Noninverting Input Channel B1
CH B1– Inverting Input Channel B1
CH B0+ Noninverting Input Channel B0
CH B0– Inverting Input Channel B0
CH A1+ Noninverting Input Channel A1
CH A1– Inverting Input Channel A1
CH A0+ Noninverting Input Channel A0
CH A0– Inverting Input Channel A0
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
11
12
13
14
9
REFIN
Reference Input
10
12
13
16
REFOUT 2.5V Reference Output
AGND
AVDD
M1
Analog Ground. Connect directly to digital ground (pin 1).
Analog Power Supply, +5VDC. Decouple to analog ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor.
Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1
isHIGH,SerialoutputAisconfiguredforbothChannelAdataandChannelBdata;SerialOutputBgoesintotri-state(i.e.,highimpedance).
15
17
M0
Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in
conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel
B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence
starting with Channels A0 and B0, followed by Channels A1 and B1.
16
17
18
A0
A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW,
Channel A0 and Channel B0 are converted.
19 CONVST Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status
of the external clock.
18
19
20
20
21
22
RD
CS
Synchronization Pulse for the Serial Output.
Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated.
CLOCK An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source.
The CLOCK pin controls the sampling rate by the equation: fSAMPLE (max) = CLOCK/20.
21
22
23
24
23
24
25
27
BUSY
BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output
pin.
SERIAL The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DATA B
DCLOCK for 20 edges after the rising edge of RD.
SERIAL The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DATA A
DCLOCK for 20 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available.
BVDD
Digital I/O Power Supply, 2.7V to 5.5V
ADS8361
6
SBOS230C
www.ti.com
TIMING CHARACTERISTICS
tCKH
11
CLOCK
0
1
2
3
4
10
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
tCKL
t6
t1
CONVST
t11
t2
t3
A0
t4
t5
t7
RD
t8
CS
t9
t8
t10
Serial
Data A
CH
0/1
CH
A/B
D15
D14
D8
D7
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
D15
D14
D13
D12
Serial
Data B
CH
0/1
0
D15
D14
D8
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
BUSY
tCONV
tACQ
tCONV
TIMING CHARACTERISTICS
Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = 5V, REFIN = REFOUT internal reference +2.5V,
CLK = 10MHz, fSAMPLE = 500kSPS, and BVDD = 2.7 ÷ 5.5V (unless otherwise noted).
f
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
COMMENTS
tCONV
tACQ
tCKP
tCKL
tCKH
tF
tR
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
DOUT Fall Time
DOUT Rise Time
CONVST HIGH
Address Setup Time
Address Hold Time
RD Setup Time
1.6
0.4
100
40
µs
µs
ns
ns
ns
ns
ns
ns
ns
When TCKP = 100ns
When TCKP = 100ns
10,000
40
25
30
15
15
15
15
15
20
20
15
Address latched on falling edge of CLK cycle ‘2’.
ns
ns
ns
ns
ns
ns
ns
ns
Before falling edge of CLOCK.
After falling edge of CLOCK.
RD to CS Hold Time
CONVST LOW
RD LOW
CS Setup Time
Before falling edge of CLOCK (for RD).
Maximum delay following rising edge of CLOCK.
Time data is valid after second rising edge of CLOCK.
Before CONVST
CLOCK to Data Valid Delay
Data Valid After CLOCK(3)
CS Setup Time
30
1
0
NOTES: (1) All input signals are specified with tr = tf = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram
above. (3) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
ADS8361
SBOS230C
7
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kHz, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
INTEGRAL LINEARITY ERROR vs CODE
Typical curve for all four channels.
3
2
5
4
3
2
1
1
0
–1
–2
–3
–4
0
–1
8000H
C000H
0000H
4000H
7FFFH
8000H
C000H
0000H
4000H
7FFFH
Output Code
Output Code
INTEGRAL LINEARITY MATCH OF
CHANNELS A0 AND B0 vs CODE
INTEGRAL LINEARITY MATCH OF
CHANNELS A0 AND A1 (or B0 and B1) vs CODE
4
3
4
3
2
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
–4
8000H
C000H
0000H
4000H
FFFFH
8000H
C000H
0000H
4000H
FFFFH
Output Code
Output Code
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
4.5
4
4
3
Max
3.5
3
2
1
2.5
2
0
1.5
1
–1
–2
–3
Min
0.5
0
–40
0
25
85
–40
0
25
85
Temperature (°C)
Temperature (°C)
ADS8361
8
SBOS230C
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 5kHz, –0.2dB)
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 10kHz, –0.2dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
BIPOLAR OFFSET MATCH vs TEMPERATURE
Channel A0/Channel B0
CHANGE IN BIPOLAR OFFSET vs TEMPERATURE
500
400
300
200
100
0
600
500
400
300
200
100
0
–100
–200
–40
0
25
85
–40
0
25
85
Temperature (°C)
Temperature (°C)
REFERENCE VOLTAGE vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
2.504
2.502
2.5
32
31
30
29
28
27
26
25
2.498
2.496
2.494
2.492
–40
0
25
85
–40
0
25
85
Temperature (°C)
Temperature (°C)
ADS8361
SBOS230C
9
www.ti.com
REFERENCE
INTRODUCTION
Under normal operation, the REFOUT pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS8361. The ADS8361 can
operate, however, with an external reference in the range of
1.2V to 2.6V for a corresponding full-scale range of 2.4V to
5.2V.
The ADS8361 is a high-speed, low-power, dual, 16-bit A/D
converter that operates from +3V/+5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual, 4µs successive
approximation A/D converter, two differential sample-and-
hold amplifiers, an internal +2.5V reference with REFIN and
REFOUT pins, and a high-speed serial interface. The ADS8361
requires an external clock. In order to achieve the maximum
throughput rate of 500kHz, the master clock must be set at
10MHz. A minimum of 20 clock cycles are required for each
16-bit conversion.
The internal reference of the ADS8361 is buffered. If the
internal reference is used to drive an external load, a buffer
is provided between the reference and the load applied to pin 2
(the internal reference can typically source 10µA of current—
load capacitance should be 0.1µF and 10µF). If an external
reference is used, the second buffer provides isolation be-
tween the external reference and the Capacitve Digital-to-
Analog Converter (CDAC). This buffer is also used to re-
charge all of the capacitors of both CDACs during conver-
sion.
There are four analog inputs that are grouped into two chan-
nels (A and B). Channel selection is controlled by the M0 (pin
14), M1 (pin 15), and A0 (pin 16) pins. Each channel has two
inputs (A0, A1 and B0, B1) that are sampled and converted
simultaneously, thus preserving the relative phase information
of the signals on both analog inputs. The part accepts an
analog input voltage in the range of –VREF to +VREF, centered
around the internal +2.5V reference. The part will also accept
bipolar input ranges when a level shift circuit is used at the front
end (see Figure 7).
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8361: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is
the (common-mode + VREF) and the (common-mode – VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
All conversions are initiated on the ADS8361 by bringing the
CONVST pin HIGH for a minimum of 15ns. CONVST HIGH
places both sample-and-hold amplifiers in the hold state
simultaneously and the conversion process is started on both
channels. The RD pin (pin 18) can be connected to CONVST
to simplify operation. Depending on the status of the M0, M1,
and A0 pins, the ADS8361 will (a) operate in either two-
channel or four-channel mode and (b) output data on both
the Serial A and Serial B output or both channels can be
transmitted on the A output only.
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or (+IN) – (–IN). The
peak-to-peak amplitude of each input is ±1/2 VREF around this
common voltage. However, since the inputs are 180° out-of-
phase, the peak-to-peak amplitude of the differential voltage is
+VREF to –VREF. The value of VREF also determines the range
of the voltage that may be common to both inputs (see
Figure 4).
NOTE: See the Timing and Control section of this data sheet
for more information.
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS8361 allow the
A/D converter to accurately convert an input sine wave of full-
scale amplitude to 16-bit accuracy. The input bandwidth of
the sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D converter
even when the A/D converter is operated at its maximum
throughput rate of 500kHz.
–VREF to +VREF
peak-to-peak
ADS8361
Common
Voltage
Single-Ended Input
Typical aperture delay time, or the time it takes for the
ADS8361 to switch from the sample to the hold mode
following the CONVST pulse, is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS8361 to capture AC input signals accurately at the
exact same moment in time.
VREF
peak-to-peak
ADS8361
Common
VREF
Voltage
peak-to-peak
Differential Input
FIGURE 1. Methods of Driving the ADS8361 Single-Ended or
Differential.
ADS8361
10
SBOS230C
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+IN
CM + VREF
CM Voltage
+VREF
–IN = CM Voltage
–VREF
t
CM – VREF
Single-Ended Inputs
+IN
+VREF
CM + 1/2 VREF
CM Voltage
CM – 1/2 VREF
–VREF
–IN
t
Differential Inputs
(+IN) + (–IN)
NOTES: Common-Mode Voltage (Differential Mode) =
, Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS8361 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 2. Using the ADS8361 in the Single-Ended and Differential Input Modes.
5
4
5
4
4.7
AVDD = 5V
AVDD = 5V
4.0
4.1
3
3
Differential Input
2.7
2.3
Single-Ended Input
2
2
1.0
1
1
0.9
0.3
0
0
–1
–1
2.52.6
3.0
1.0
2.0
REF (V)
2.52.6
3.0
1.2
1.0
1.2
2.0
REF (V)
V
V
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs VREF
FIGURE 3.Single-Ended Input: Common-Mode Voltage
Range vs VREF
.
.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, gain error,
and linearity error which will change with both temperature
and input voltage.
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to a 16-bit settling
level within 4 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8361 charges the inter-
nal capacitor array during the sampling period. After this
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
ADS8361
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11
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BIPOLAR INPUTS
TRANSITION NOISE
The differential inputs of the ADS8361 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resistors,
the ADS8361 can be configured to except bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS8361 using the resistor values shown in
Figure 7.
The transition noise of the ADS8361 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8361. This is true for all 16-
bit, Successive Approximation Register (SAR-type) A/D con-
verters. Using a histogram to plot the output codes, the
distribution should appear bell-shaped with the peak of the bell
curve representing the nominal code for the input value. The
±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the ±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peak-
to-peak noise of the input signal and reference must be
< 50µV.
R1
4kΩ
600Ω
+IN
OPA227
20kΩ
Bipolar Input
600Ω
–IN
R2
ADS8361
OPA227
REFOUT (pin 11)
2.5V
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TIMING AND CONTROL
0
The operation of the ADS8361 can be configured in four
different modes by using the address pins M0 (pin 14), M1
(pin 15), and A0 (pin 16).
32761
32762
32763
32764 32765
32766
Code (decimal)
The M0 pin selects between two- and four-channel operation
(in two-channel operation, the A0 pin selects between Chan-
nels 0 and 1; in four-channel operation the A0 pin is ignored
and the channels are switched automatically after each
conversion). The M1 pin selects between having serial data
transmitted simultaneously on both the Serial A data output
(pin 23) and the Serial B data output (pin 22) or having both
channels output data through the Serial A port. The A0 pin
selects either Channel 0 or Channel 1 (see Pin Descriptions
and Serial Output Truth Table for more information).
FIGURE 5. Histogram of 8000 Conversions of a DC Input.
1.4V
3kΩ
DATA
Test Point
The next four sections will explain the four different modes of
operation.
100pF
CLOAD
Mode I (M0 = 0, M1 = 0)
With the M0 and M1 pins both set to ‘0’, the ADS8361 will
operate in two-channel operation (the A0 pin must be used
to switch between Channels A and B). A conversion is
initiated by bringing CONVST HIGH for a minimum of 15ns.
It is very important that CONVST be brought HIGH a mini-
mum of 10ns prior to a falling edge of the external clock or
5ns after the falling edge. If CONVST is brought HIGH within
this window, it is then uncertain as to when the ADS8361 will
initiate conversion (see Figure 9 for a more detailed descrip-
VOH
DATA
VOL
tR
tF
Voltage Waveforms for DATA Rise-and-Fall Times tR, and tF.
FIGURE 6. Test Circuits for Timing Specifications.
12
ADS8361
SBOS230C
www.ti.com
Binary Two’s Complement
BTC
65535
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
65534
65533
32769
32768
32767
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
2
1
0
2.499962V
VNFS = VCM – VREF = 0V
0.000038V
2.500038V
VBPZ = 2.5V
Unipolar Analog Input Voltage
VPFS = VCM + VREF = 5V
VPFS – 1LSB = 4.999924V
4.999848V
0.000076V
0.000152V
1LSB = 76µV
VCM = 2.5V
VREF = 2.5V
16-BIT
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code
Bipolar Zero Code
= VNFS = 8000H, Vcode = VCM – VREF
= VBPZ = 0000H, Vcode = VCM
Positive Full-Scale Code
= VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB
FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX– = 2.5V, VREF = 2.5V)
tion). Twenty clock cycles are required to perform a single
conversion. Immediately following CONVST switching to
HIGH, the ADS8361 will switch from the sample mode to the
hold mode asynchronous to the external clock. The BUSY
output pin will then go HIGH and remain HIGH for the
duration of the conversion cycle. On the falling edge of the
first cycle of the external clock, the ADS8361 will latch in the
address for the next conversion cycle depending on the
status of the A0 pin (HIGH = Channel 1, LOW = Channel 0).
The address must be selected 15ns prior to the falling edge of
cycle one of the external clock and must remain ‘held’ for 15ns
following the clock edge. For maximum throughput time, the
CONVST and RD pins should be tied together. CS must be
brought LOW to enable the CONVST and RD inputs. Data will
be valid on the falling edge of all 20 clock cycles per conver-
sion. The first bit of data will be a status flag for either Channel
0 or 1, the second bit will be a second status flag for either
Channel A or B. First and second bit will be 0 in Mode I. See
Table II below. The subsequent data will be MSB-first through
the LSB, followed by two zeros (see Table III and Figures 9
and 10).
BIT 1
M1
BIT 2
CH0/1
MODE
M0
CHA/B
CHANNEL SELECTION
DATA OUTPUT
1
2
3
4
0
0
1
1
0
1
0
1
0
0
0/1
0/1
0
Ch0/1 Selected by A0
Ch0/1 Selected by A0
Ch0/1 Alternating
On Data A and B
Sequentially on Data A
On Data A and B
0 = A/1 = B
0
0 = A/1 = B
Ch0/1 Alternating
Sequentially on Data A
TABLE II. Mode Selection.
CLOCK CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SERIAL DATA CH0 OR CH1 CHA OR CHB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
0
0
TABLE III. Serial Data Output Format.
ADS8361
SBOS230C
13
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Mode II (M0 = 0, M1 = 1)
output of the analog comparator. Thus, driving any single
conversion for an n-bit SAR converter, there are n “windows”
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switch-
ing power supplies, nearby digital logic, or high power de-
vices. The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With M1 set to ‘1’, the ADS8361 will output data on the
Serial Data A pin only. All other pins function in the same
manner as Mode I except that the Serial Data B output will
tri-state (i.e., high impedance) after a conversion following
M1 going HIGH. Another difference in this mode involves
the CONVST pin. Since it takes 40 clock cycles to output
the results from both A/D converters (rather than 20 when
M1 = 0), the ADS8361 will take 4µs to complete a conver-
sion on both A/D converters (See Figure 11).
With this in mind, power to the ADS8361 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be used to
low-pass filter a noisy supply. On average, the ADS8361
draws very little current from an external reference as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the VREF input and the
reference source must be able to handle this. Whether the
reference is internal or external, the VREF pin should be
bypassed with a 0.1µF capacitor. An additional larger capaci-
tor may also be used, if desired. If the reference voltage is
external and originates from an op amp, make sure that it can
drive the bypass capacitor or capacitors without oscillation.
No bypass capacitor is necessary when using the internal
reference (tie pin 10 directly to pin 11).
Mode III (M0 = 1, M1 = 0)
With M0 set to ‘1’, the ADS8361 will cycle through Channels
0 and 1 sequentially (the A0 pin is ignored). At the same time,
setting M1 to ‘0’ places both Serial Outputs, A and B, in the
active mode (See Figure 12).
Mode IV (M0 = 1, M1 = 1)
Similar to Mode II, Mode IV uses the Serial A output line to
transmit data exclusively. Following the first conversion after
M1 goes HIGH, the serial B output will go into tri-state. See
Figure 13. As in Mode II, the second CONVST command is
always ignored when M1 = 1.
READING DATA
In all four timing diagrams, the CONVST pin and the RD pins
are tied together. If so desired, the two lines can be sepa-
rated. Data on the Serial Output pins (A and B) will become
valid following the third rising SCLK edge following RD rising
edge. Refer to Table III for data output format.
The GND pin should be connected to a clean ground point.
In many cases, this will be the ‘analog’ ground. Avoid
connections which are too near the grounding point of a
microcontroller or Digital Signal Processor (DSP). If required,
run a ground trace directly from the converter to the power-
supply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8361 circuitry. This is particularly
true if the CLOCK input is approaching the maximum through-
put rate.
APPLICATION INFORMATION
In Figures 14 through 17, different connection diagrams to
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
DSPs or microcontrollers are shown.
tCKP
100ns
CLOCK
Cycle 1
Cycle 2
10ns
10ns
5ns
5ns
CONVST
A
B
C
NOTE: All CONVST commands which occur more than 10ns before the falling edge before cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising
edge of cycle ‘1’. All CONVST commands which occur 5ns after the falling edge before cycle ‘1’ or 10ns before the falling edge before cycle 2 (Region ‘B’) will initiate a
conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the falling edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising
edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the falling edge of the CLOCK and 5ns after the
falling edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge.
FIGURE 9. Conversion Mode.
ADS8361
14
SBOS230C
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1
20
CLOCK
CONVST
A0
Conversion of Ch1
Conversion of Ch0
A0 HIGH, Next Conversion: Ch1
RD Connected to CONVST
A0 LOW, Next Conversion: Ch0
RD
CS
CS HIGH, Outputs in Tri-State
Serial
Data A
16-Bit Data of Chx
16-Bit Data of Chx
16-Bit Data of ChA1
16-Bit Data of ChB1
Serial
Data B
Conversion of Chx
Conversion of Ch1
Conversion of Ch0
BUSY
TIME
0
1µ
2µ
3µ
4µ
5µ
6µ
Time (seconds)
FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0.
1
20
CLOCK
CONVST
A0
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
Conversion of Chx
A0 HIGH
A0 LOW
Next Conversion Ch0
A0 LOW
Next Conversion Ch0
Next Conversion Ch1
M1 HIGH
M1
RD
Only Serial Data A Used as Output Starting with 1st Conversion
RD Connected with CONVST
CS LOW Output Active
CS
C
h
A
C
h
B
C
h
A
C
h
B
Serial
Data A
16-Bit Data of ChAx
16-Bit Data of ChBx
M1 = 1 and 1st CONVST
Data of ChA
M1 = 1 and 2nd CONVST
M1 = 1 and 1st CONVST
M1 = 1 and 2nd CONVST
Data of ChB
Data of ChA
Data of ChB
M1 = 1 Serial Data B in Tri-state
Serial
Data B
Conversion of Chx
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
BUSY
TIME 0
5µ
10µ
Time (seconds)
FIGURE 11. Mode II, Timing Diagram for M0 = 0 and M1 = 1.
ADS8361
SBOS230C
15
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1
20
CLOCK
CONVST
A0
4-Ch Operation and 1st Conversion Ch0
M0 = 1 A0 Ignored
4-Ch Operation and 2nd Conversion Ch1
M0
M0 = 1, 4-Ch Operation Starts with Next Conversion
RD Connected with CONVST
RD
CS
CS LOW, Output is Active
16-Bit Data of ChA0
C
h
0
C
h
1
Serial
Data A
16-Bit Data of ChA1
16-Bit Data of ChB1
16-Bit Data of ChAx
C
h
0
C
h
1
Serial
Data B
16-Bit Data of ChBx
16-Bit Data of ChB0
BUSY
TIME
0
1µ
2µ
3µ
4µ
5µ
6µ
Time (seconds)
FIGURE 12. Mode III, Timing Diagram for M0 = 1 and M1 = 0.
ADS8361
16
SBOS230C
www.ti.com
1
20
CLOCK
CONVST
A0
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
Conversion of Chx
M0 HIGH
4-Ch Operation Starts, A0 Ignored
M0 HIGH
4-Ch Operation Starts
M0 = 1 and 1st Active CONVST
Ch0
M0 = 1 and 2nd Active CONVST
Ch1
M0
M1 HIGH
M1
RD
Only Serial Data A Used as Output Starting with 1st Conversion
RD Connected with CONVST
CS LOW Output Active
CS
C C
h h
0 A
C
h
0
C
h
B
C
h
1
C
h
A
C C
h h
1 B
Serial
Data A
16-Bit Data of ChAx
16-Bit Data of ChBx
M1 = 1 and 1st CONVST
Data of ChA0
M1 = 1 and 2nd CONVST
Data of ChB0
M1 = 1 and 1st CONVST
Data of ChA1
M1 = 1 and 2nd CONVST
Data of ChB1
M1 = 1 Serial Data B in Tri-state
Serial
Data B
Conversion of Chx
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
M1 = 1 and 1st CONVST
Conversion
M1 = 1 and 2nd CONVST
No Conversion
BUSY
TIME 0
5µ
10µ
Time (seconds)
FIGURE 13. Mode IV, Timing Diagram for M0 = 1 and M1 = 1.
MSP430x1xx/4xx
ADS8361
SERIAL DATA A
CLOCK
MISO
SCLK
CONVST
P3.5
RD
BVDD
BUSY
P2.1(INT)
P3.6
M1
M0
A0
CS
FIGURE 14. 2x2 Channel Using A Output.
ADS8361
SBOS230C
17
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TMS320F28xx/
C54xx/C67xx
ADS8361
SERIAL DATA A
CONVST
RD
DR
FSX
FSR
CLOCK
CLKX
CLKR
BVDD
BUSY
A0
EXT_INT
DX
M1
M0
CS
FIGURE 15. 2x2 Channel Using A Output.
TMS320C54xx/
C67xx
ADS8361
SERIAL DATA A
DRA
DRB
SERIAL DATA B
CONVST
RD
FSXA
FSRA
FSRB
CLOCK
CLKXA
CLKRA
CLKRB
BVDD
M1
M0
CS
FIGURE 16. 4-Channel Sequential Mode Using A and B Outputs.
TMS320F28xx/
C54xx/C67xx
ADS8361
DRX
FSX
FSR
SERIAL DATA A
CONVST
RD
CLKX
CLKR
CLOCK
BVDD
M0
M1
CS
FIGURE 17. 4-Channel Sequential Mode Using A Output.
ADS8361
18
SBOS230C
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THERMAL PAD MECHANICAL DATA
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RHB (S-PQFP-N32)
THERMAL INFORMATION
This package incorporates an exposed thermal pad that is designed to be attached directly to an external
heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB
can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly
to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer
from the integrated circuit (IC).
For additional information on the Quad Flatpack No-Lead (QFN) package and how to take advantage of its heat
dissipating abilities, refer to Application Report, Quad Flatpack No-Lead Logic Packages, Texas Instruments
Literature No. SCBA017 and Application Report, 56-Pin Quad Flatpack No-Lead Logic Package, Texas
Instruments Literature No. SCEA032. Both documents are available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
1
8
32
9
Exposed Thermal Pad
+0,10
0,15
3,15
25
16
24
17
+0,10
0,15
3,15
Bottom View
NOTE: All linear dimensions are in millimeters
QFND028
Exposed Thermal Pad Dimensions
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS8361IDBQ
ADS8361IDBQR
ADS8361IRHBR
ADS8361IRHBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
QFN
DBQ
DBQ
RHB
RHB
24
24
32
32
56
2500
3000
250
QFN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MSOI004E JANUARY 1995 − REVISED MAY 2002
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.150 (3,81) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane
1
12
A
0.010 (0,25)
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
1
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