ADS8365IPAGR_技术文档

B

u

r

Ć

B

r

o

w

n

P

r

o

d

u

c

t

s

ADS8365

f

r

o

m

T

e

x

a

s

I

n

s

t

r

u

m

e

n

t

s

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling

SAR ANALOG-TO-DIGITAL CONVERTERS

FEATURES

DESCRIPTION

•

Six Input Channels

The ADS8365 includes six, 16-bit, 250kSPS

analog-to-digital converters (ADCs) with six fully

differential input channels grouped into three pairs

for high-speed simultaneous signal acquisition.

Inputs to the sample-and-hold amplifiers are fully

differential and are maintained differential to the input

of the ADC. This architecture provides excellent

common-mode rejection of 80dB at 50kHz, which is

important in high-noise environments.

Fully Differential Inputs

Six Independent 16-Bit ADCs

4µs Total Throughput per Channel

Low Power:

200mW in Normal Mode

5mW in Nap Mode

50µW in Power-Down Mode

The ADS8365 offers a flexible, high-speed parallel

interface with a direct address mode, a cycle, and a

FIFO mode. The output data for each channel is

available as a 16-bit word.

•

TQFP-64 Package Package

APPLICATIONS

•

Motor Control

Multi-Axis Positioning Systems

3-Phase Power Control

CH A0+

CDAC

CH A0-

S/H

Amp

Comp

SAR

HOLDA

CH A1+

Interface

A0

A1

A2

CDAC

CH A1-

S/H

Amp

Comp

Conversion

and

ADD

NAP

Control

CH B0+

RD

WR

CS

CH B0-

S/H

Amp

FD

EOC

CLK

FIFO

Register

HOLDB

CH B1+

RESET

BYTE

and

6x

16

CDAC

CH B1-

Comp

S/H

Amp

Data

Input/Output

CH C0+

CH C0-

S/H

Amp

HOLDC

CH C1+

CDAC

CH C1-

Comp

S/H

Amp

REF_IN

Internal

2.5V

Reference

REF_OUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

ORDERING INFORMATION⁽¹⁾

MAXIMUM

NO

INTEGRAL MISSING

LINEARITY CODES

SPECIFIED

TEMPERATURE PACKAGE

TRANSPORT

MEDIA,

QUANTITY

ERROR

(LSB)

ERROR PACKAGE-

(LSB)

PACKAGE

DESIGNATOR

ORDERING

NUMBER

PRODUCT

LEAD

RANGE

MARKING

ADS8365IPAG

Tray, 96

ADS8365

±4

14

TQFP-64

PAG

–40°C to +85°C

ADS8365I

Tape and

Reel, 1500

ADS8365IPAGR

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see

the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

ADS8365

–0.3 to 6

UNIT

V

Supply voltage, AGND to AV_DD

Supply voltage, BGND to BV_DD

Analog input voltage range

–0.3 to 6

V

AGND – 0.3 to AV_DD+ 0.3

BGND – 0.3 to BV_DD+ 0.3

±0.3

V

Reference input voltage range

V

Digital input voltage range

V

Ground voltage differences, AGND to BGND

Voltage differences, BV_DDto AGND

Input current to any pin except supply

Power dissipation

V

–0.3 to 6

V

–20 to 20

mA

See Dissipation Ratings Table

Operating virtual junction temperature range, T_J

Operating free-air temperature range, T_A

Storage temperature range, T_STG

–40 to +150

–40 to +85

–65 to +150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS

DERATING

FACTOR ABOVE

T_A≤ +25°C

T_A= +70°C

T_A= +85°C

BOARD

Low-K⁽¹⁾

High-K⁽²⁾

PACKAGE

PAG

R_θJC

R_θJA

T_A= +25°C

POWER RATING POWER RATING POWER RATING

8.6°C/W

68.5°C/W

42.8°C/W

14.598mW/°C

23.364mW/°C

1824mW

2920mW

1168mW

1869mW

949mW

PAG

1519mW

(1) The JEDEC Low K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top

of the board.

(2) The JEDEC High K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and

ground planes, and 2-ounce copper traces on the top and bottom of the board.

2

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

RECOMMENDED OPERATING CONDITIONS

MIN

4.75

2.7

4.5

1.5

2.2

0

NOM

MAX

5.25

3.6

UNIT

V

Supply voltage, AV_DDto AGND

5

Low-voltage levels

Supply voltage, BV_DDto BGND

V

5V logic levels

5

5.5

V

Reference input voltage

2.5

2.6

V

Operating common-mode signal, –IN

Analog inputs, +IN – (–IN)

2.8

V

±V_REF

+125

V

Operating junction temperature range, T_J

–40

°C

ELECTRICAL CHARACTERISTICS: 100kSPS

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 2MHz,

and f_SAMPLE= 100kSPS, unless otherwise noted.

ADS8365

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

ANALOG INPUT

Full-scale range

FSR +IN – (–IN)

±V_REF

V

Operating common-mode signal

Input resistance

2.2

2.8

–IN = V_REF

750

25

Ω

Input capacitance

–IN = V_REF

pF

nA

Ω

Input leakage current

–IN = V_REF

±1

Differential input resistance

Differential input capacitance

–IN = V_REF

1500

15

–IN = V_REF

pF

dB

MHz

At dc

84

Common-mode rejection ratio

CMRR

V_IN= ±1.25V_PPat 50kHz

80

Bandwidth

BW FS sinewave, –3dB

10

DC ACCURACY

Resolution

16

Bits

No missing codes

Integral linearity error

Differential nonlinearity

Bipolar offset error

Bipolar offset error match

Bipolar offset error drift

Gain error

NMC

14

INL

DNL

V_OS

±1.5

±1

±4

LSB

±2.3

mV

Only pair-wise matching

0.2

1

mV

TCV_OS

0.8

ppm/°C

%FSR

ppm/°C

µVrms

dB

G_ERRReferenced to V_REF

Only pair-wise matching

±0.05

0.005

2

±0.25

Gain error match

Gain error drift

0.05

TCG_ERR

Noise

60

Power-supply rejection ratio

SAMPLING DYNAMICS

Conversion time per ADC

Acquisition time

PSRR 4.75V < AV_DD< 5.25V

–87

t_CONV50kHz ≤ f_CLK≤ 5MHz

3.2

320

5

µs

ns

t_AQf_CLK= 5MHz

800

Aperture delay

ns

Aperture delay matching

Aperture jitter

100

50

ps

Clock frequency

0.05

5

MHz

(1) All typical values are at +25°C.

3

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS: 100kSPS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 2MHz,

and f_SAMPLE= 100kSPS, unless otherwise noted.

ADS8365

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

AC ACCURACY

Total harmonic distortion

Spurious-free dynamic range

Signal-to-noise ratio

THD V_IN= ±2.5V_PPat 50kHz

–94

95

dB

Bits

SFDR V_IN= ±2.5V_PPat 50kHz

SNR V_IN= ±2.5V_PPat 10kHz

SINAD V_IN= ±2.5V_PPat 10kHz

88

Signal-to-noise + distortion

Channel-to-channel isolation

Effective number of bits

VOLTAGE REFERENCE OUTPUT

Reference voltage output

Initial accuracy

87

95

ENOB

V_OUT

14.3

2.475

2.5

2.525

V

%

±1

Output voltage temperature drift

dV_OUT/dT

±20

40

ppm/°C

µV_PP

µVrms

dB

f = 0.1Hz to 10Hz, C_L= 10µF

f = 10Hz to 10kHz, C_L= 10µF

Output voltage noise

8

Power-supply rejection ratio

Output impedance

PSRR

R_OUT

I_SC

60

2

kΩ

Short-circuit current

Turn-on settling time

VOLTAGE REFERENCE INPUT

Reference voltage input

Reference input resistance

Reference input capacitance

Reference input current

DIGITAL INPUTS⁽²⁾

Logic family

1.25

100

mA

to 0.1% at C_L= 0pF

µs

V_IN

1.5

2.5

5

2.6

1

V

100

MΩ

pF

µA

CMOS

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

0.7 × BV_DD

BV_DD+ 0.3

0.3 × BV_DD

±50

V

–0.3

I_INV_I= BV_DDor GND

C_I

nA

pF

Input capacitance

5

DIGITAL OUTPUTS⁽²⁾

Logic family

CMOS

High-level output voltage

Low-level output voltage

High-impedance state output current

Output capacitance

Load capacitance

V_OHBV_DD= 4.5V, I_OH= –100µA

4.44

V

V_OLBV_DD= 4.5V, I_OL= 100µA

0.5

I_OZCS = BV_DD, V_I= BV_DDor GND

±50

nA

pF

C_O

C_L

5

30

DIGITAL INPUTS⁽³⁾

Logic family

LVCMOS

High-level input voltage

Low-level input voltage

Input current

V_IHBV_DD= 3.6V

V_ILBV_DD= 2.7V

I_INV_I= BV_DDor GND

C_I

2

BV_DD+ 0.3

0.8

V

–0.3

±50

nA

pF

Input capacitance

5

(2) Applies for 5.0V nominal supply: BV_DD(min) = 4.5V and BV_DD(max) = 5.5V.

(3) Applies for 3.0V nominal supply: BV_DD(min) = 2.7V and BV_DD(max) = 3.6V.

4

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS: 100kSPS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 2MHz,

and f_SAMPLE= 100kSPS, unless otherwise noted.

ADS8365

PARAMETER

DIGITAL OUTPUTS⁽⁴⁾

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

Logic family

LVCMOS

High-level output voltage

Low-level output voltage

High-impedance state output current

Output capacitance

V_OHBV_DD= 2.7V, I_OH= –100µA

BVDD – 0.2

V

V_OLBV_DD= 2.7V, I_OL= 100µA

0.2

I_OZCS = BV_DD, V_I= BV_DDor GND

±50

nA

pF

C_O

C_L

5

Load capacitance

30

DATA FORMAT

Bit DB4 = 1

Bit DB4 = 0

Binary two's complement

Straight binary coding

Data format

POWER SUPPLY

Analog supply voltage

AV_DD

4.75

2.7

4.5

38

5.25

3.6

5.5

45

V

Low-voltage levels

5V logic levels

Buffer I/O supply voltage

BV_DD

AI_DD

BI_DD

V

Analog operating supply current

Buffer I/O operating supply current

mA

µA

mW

µW

BV_DD= 3V

60

90

BV_DD= 5V

100

190

150

225

5

BV_DD= 3V

BV_DD= 5V

Power dissipation

Nap mode enabled

Powerdown enabled

50

(4) Applies for 3.0V nominal supply: BV_DD(min) = 2.7V and BV_DD(max) = 3.6V.

5

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS: 250kSPS

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 5MHz,

and f_SAMPLE= 250kSPS, unless otherwise noted

ADS8365

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

ANALOG INPUT

Full-scale range

FSR +IN – (–IN)

±V_REF

V

Operating common-mode signal

Input resistance

2.2

2.8

–IN = V_REF

750

25

Ω

Input capacitance

–IN = V_REF

pF

nA

Ω

Input leakage current

–IN = V_REF

±1

Differential input resistance

Differential input capacitance

–IN = V_REF

1500

15

–IN = V_REF

pF

dB

MHz

At dc

84

Common-mode rejection ratio

CMRR

V_IN= ±1.25V_PPat 50kHz

80

Bandwidth

BW FS sinewave, –3dB

10

DC ACCURACY

Resolution

16

Bits

No missing codes

Integral linearity error

Differential nonlinearity

Bipolar offset error

Bipolar offset error match

Bipolar offset error drift

Gain error

NMC

14

INL

±3

±1.5

±1

±8

LSB

DNL Specified for 14 bit

V_OS

LSB

±2.3

mV

Only pair-wise matching

0.2

1

mV

TCV_OS

0.8

ppm/°C

%FSR

ppm/°C

µVrms

dB

G_ERRReferenced to V_REF

Only pair-wise matching

±0.05

0.005

2

±0.25

Gain error match

0.05

Gain error drift

TCG_ERR

Noise

60

Power-supply rejection ratio

SAMPLING DYNAMICS

Conversion time per ADC

Acquisition time

PSRR 4.75V < AV_DD< 5.25V

–87

t_CONV50kHz ≤ f_CLK≤ 5MHz

3.2

320

µs

ns

t_AQf_CLK= 5MHz

800

Throughput rate

250

5

kSPS

ns

Aperture delay

Aperture delay matching

Aperture jitter

100

50

ps

Clock frequency

0.05

5

MHz

AC ACCURACY

Total harmonic distortion

Spurious-free dynamic range

Signal-to-noise ratio

Signal-to-noise + distortion

Channel-to-channel isolation

Effective number of bits

THD V_IN= ±2.5V_PPat 50kHz

SFDR V_IN= ±2.5V_PPat 50kHz

SNR V_IN= ±2.5V_PPat 10kHz

SINAD V_IN= ±2.5V_PPat 10kHz

–94

95

dB

Bits

88

87

95

ENOB

14.3

(1) All typical values are at +25°C.

6

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS: 250kSPS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 5MHz,

and f_SAMPLE= 250kSPS, unless otherwise noted

ADS8365

PARAMETER

VOLTAGE REFERENCE OUTPUT

Reference voltage output

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

V_OUT

2.475

2.5

2.525

V

%

Initial accuracy

±1

Output voltage temperature drift

dV_OUT/dT

±20

40

ppm/°C

µV_PP

µVrms

dB

f = 0.1Hz to 10Hz, C_L= 10µF

f = 10Hz to 10kHz, C_L= 10µF

Output voltage noise

8

Power-supply rejection ratio

Output impedance

PSRR

R_OUT

I_SC

60

2

kΩ

Short-circuit current

Turn-on settling time

VOLTAGE REFERENCE INPUT

Reference voltage input

Reference input resistance

Reference input capacitance

Reference input current

DIGITAL INPUTS⁽²⁾

Logic family

1.25

100

mA

to 0.1% at C_L= 0pF

µs

V_IN

1.5

2.5

5

2.6

1

V

100

MΩ

pF

µA

CMOS

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

0.7 × BV_DD

BV_DD+ 0.3

0.3 × BV_DD

±50

V

–0.3

I_INV_I= BV_DDor GND

C_I

nA

pF

Input capacitance

5

DIGITAL OUTPUTS⁽²⁾

Logic family

CMOS

High-level output voltage

Low-level output voltage

High-impedance state output current

Output capacitance

V_OHBV_DD= 4.5V, I_OH= –100µA

4.44

V

V_OLBV_DD= 4.5V, I_OL= 100µA

0.5

I_OZCS = BV_DD, V_I= BV_DDor GND

±50

nA

pF

C_O

C_L

5

Load capacitance

30

DIGITAL INPUTS⁽³⁾

Logic family

LVCMOS

High-level input voltage

Low-level input voltage

Input current

V_IHBV_DD= 3.6V

V_ILBV_DD= 2.7V

I_INV_I= BV_DDor GND

C_I

2

BV_DD+ 0.3

0.8

V

–0.3

±50

nA

pF

Input capacitance

5

DIGITAL OUTPUTS⁽³⁾

Logic family

LVCMOS

High-level output voltage

Low-level output voltage

High-impedance state output current

Output capacitance

V_OHBV_DD= 2.7V, I_OH= –100µA

BVDD – 0.2

V

V_OLBV_DD= 2.7V, I_OL= 100µA

0.2

I_OZCS = BV_DD, V_I= BV_DDor GND

±50

nA

pF

C_O

C_L

5

Load capacitance

30

(2) Applies for 5.0V nominal supply: BV_DD(min) = 4.5V and BV_DD(max) = 5.5V.

(3) Applies for 3.0V nominal supply: BV_DD(min) = 2.7V and BV_DD(max) = 3.6V.

7

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ELECTRICAL CHARACTERISTICS: 250kSPS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, AV_DD= 5V, BV_DD= 3V, V_REF= internal +2.5V, f_CLK= 5MHz,

and f_SAMPLE= 250kSPS, unless otherwise noted

ADS8365

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

DATA FORMAT

Data format

Bit DB4 = 1

Binary two's complement

Straight binary coding

Bit DB4 = 0

POWER SUPPLY

Analog supply voltage

AV_DD

BV_DD

AI_DD

BI_DD

4.75

2.7

5.25

3.6

5.5

48

V

Low-voltage levels

5V logic levels

Buffer I/O supply voltage

4.5

V

Analog operating supply current

Buffer I/O operating supply current

40

mA

µA

mW

µW

BV_DD= 3V

150

250

200

201

225

375

240

241

5

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

Power dissipation

Nap mode enabled

Powerdown enabled

50

EQUIVALENT INPUT CIRCUIT

Diode Turn-on Voltage: 0.35V

AV_DD

BV_DD

R_ON

C_(SAMPLE)

20pF

750W

A_IN

D_IN

AGND

BGND

Equivalent Digital Input Circuit

Equivalent Analog Input Circuit

8

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

PIN CONFIGURATION

PAG PACKAGE

TQFP-64

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

CH A1-

CH A1+

AV_DD

1

2

3

4

5

6

7

8

9

48 D0

47 D1

46 D2

45 D3

44 D4

43 D5

42 D6

41 D7

40 D8

39 D9

38 D10

37 D11

36 D12

35 D13

34 D14

33 D15

AGND

SGND

CH B0+

CH B0-

AV_DD

ADS8365

AGND

SGND 10

CH B1- 11

CH B1+ 12

AV_DD13

AGND 14

SGND 15

CH C0+ 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

TERMINAL FUNCTIONS

TERMINAL

NAME

CH A1–

NO.

1

I/O⁽¹⁾

AI

P

DESCRIPTION

Inverting input channel A1

Noninverting input channel A1

Analog power supply

Analog ground

CH A1+

AV_DD

2

3

AGND

SGND

CH B0+

CH B0–

AV_DD

4

P

5

P

Signal Ground

6

AI

P

Noninverting input channel B0

Inverting input channel B0

Analog power supply

Analog ground

7

8

AGND

SGND

CH B1–

CH B1+

AV_DD

9

P

10

11

12

13

14

15

16

17

18

P

Signal ground

AI

P

Inverting input channel B1

Noninverting input channel B1

Analog power supply

Analog ground

AGND

SGND

CH C0+

CH C0–

CH C1–

P

Signal ground

AI

Noninverting input channel C0

Inverting input channel C0

Inverting input channel C1

(1) AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, and P = Power Supply

Connection.

9

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

PIN CONFIGURATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

CH C1+

NO.

19

20

21

22

23

24

25

26

27

I/O⁽¹⁾

AI

DESCRIPTION

Noninverting input channel C1

Nap mode.Low level or unconnected = normal operation; high level = Nap mode.

Analog ground

NAP

DI

P

AGND

AV_DD

BYTE

BV_DD

BGND

FD

P

+5V power supply

DI

P

2 x 8 output capability (active high)

Power supply for digital interface from 3V to 5V

Buffer digital ground

P

DO

First data (A0 data)

EOC

End of conversion (active low)

An external CMOS compatible clock can be applied to the CLK input to synchronize the conversion process to an

external source.

CLK

28

DI

RD

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

DI

Read (active low)

WR

Write (active low)

CS

DI

Chip select (active low)

Buffer digital ground

BGND

D15

P

DO

DIO

P

Data bit 15 (MSB)

D14

Data bit 14

D13

Data bit 13

D12

Data bit 12

D11

Data bit 11

D10

Data bit 10

D9

Data bit 9

D8

Data bit 8

D7

Data bit 7 (software input 7)

Data bit 6 (software input 6)

Data bit 5 (software input 5)

Data bit 4 (software input 4)

Data bit 3 (software input 3)

Data bit 2 (software input 2)

Data bit 1 (software input 1)

Data bit 0 (software input 0) (LSB)

Buffer digital ground

D6

D5

D4

D3

D2

D1

D0

BGND

BV_DD

RESET

ADD

A2

P

Power supply for digital interface from 3V to 5V

Global reset (active low)

Address mode select

Address line 3

DI

A1

DI

Address line 2

A0

DI

Address line 1

HOLDA

HOLDB

HOLDC

AV_DD

AGND

REF_OUT

REF_IN

CH A0+

CH A0–

DI

Hold command A (active low)

Hold command B (active low)

Hold command C (active low)

Analog power supply

Analog ground

DI

P

AO

AI

Reference output; attach 0.1µF and 10µF capacitors

Reference input

AI

Noninverting input channel A0

Inverting input channel A0

AI

10

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

TIMING INFORMATION

t_C1

CLK

1

2

16

17

18

20

1

2

19

t_W1

t_D1

CONVERSION

t_CONV

ACQUISITION

t_ACQ

HOLDX

t_W3

t_W2

EOC

CS

t_D4

t_D5

t_W6

RD

t_W5

t_D7

t_D6

D15–D8

D7–D0

Bits 15–8

Bits 7–0

Bits 15–8

Bits 7–0

BYTE

Figure 1. Read and Convert Timing

CS

WR

WR or CS

DB7:0

t_D10

t_W6

t_D11

Figure 2. Write Timing

11

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

TIMING CHARACTERISTICS^(1)(2)(3)(4)

Over recommended operating free-air temperature range, T_MINto T_MAX, AV_DD= 5V, REF_IN= REF_OUT, V_REF= internal +2.5V,

f_CLK= 5MHz, f_SAMPLE= 250kSPS, and BV_DD= 2.7 to 5V, unless otherwise noted,

SYMBOL

t_ACQ

DESCRIPTION

MIN

TYP

MAX

0.8

UNIT

µs

ns

Acquisition time

t_CONV

Conversion time

3.2

t_C1

Cycle time of CLK

200

10

20

40

0

(5)

t_D1

Delay time of rising edge of CLK after falling edge of HOLDX

BV_DD= 5V

t_D2

Delay time of first hold after RESET

BV_DD= 3V

t_D4

t_D5

Delay time of falling edge of RD after falling edge of CS

Delay time of rising edge of CS after rising edge of RD

0

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

40

60

5

t_D6

Delay time of data valid after falling edge of RD

Delay time of data hold from rising edge of RD

Delay time of RD high after CS low

t_D7

10

50

60

10

20

10

20

10

20

60

15

30

20

30

20

40

30

40

50

70

t_D8

t_D9

Delay time of RD low after address setup

Delay time of data valid to WR low

t_D10

t_D11

t_W1

t_W2

Delay time of WR or CS high to data release

Pulse width CLK high time or low time

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

BV_DD= 5V

BV_DD= 3V

Pulse width of HOLDX high time to be recognized again

t_W3

t_W4

t_W5

t_W6

Pulse width of HOLDX low time

Pulse width of RESET

Pulse width of RD high time

Pulse width of RD and CS both low time

(1) Assured by design.

(2) All input signals are specified with rise time and fall time = 5ns (10% to 90% of BV_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

(3) See Figure 1.

(4) BYTE is asynchronous; when BYTE is 0, bits 15 to 0 appear at DB15 to DB0. When BYTE is 1, bits 15 to 8 appear on DB7 to DB0. RD

may remain LOW between changes in BYTE.

(5) Only important when synchronization to clock is important.

12

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

At T_A= +25°C, AV_DD= +5V, BV_DD= +3V, V_REF= internal +2.5V, f_CLK= 5MHz, and f_SAMPLE= 250kSPS, unless otherwise noted.

INTEGRAL LINEARITY ERROR

vs CODE (100kSPS)

DIFFERENTIAL LINEARITY ERROR

vs CODE (100kSPS)

2.0

1.5

1.0

0.5

0

4

3

2

1

0

1

2

3

4

-0.5

-1.0

0

8192 16384 24576 32768 40960 49152 57344 65535

Code

0

8192 16384 24576 32768 40960 49152 57344 65535

Code

Figure 3.

Figure 4.

MINIMUM AND MAXIMUM INL OF ALL CHANNELS

vs TEMPERATURE (100kSPS)

MINIMUM AND MAXIMUM INL OF ALL CHANNELS

vs TEMPERATURE (250kSPS)

1.5

1.0

1.5

1.0

Max

Min

0.5

0

-0.5

-1.0

-1.5

-2.0

-2.5

-0.5

-1.0

-1.5

-2.0

-2.5

Min

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

Figure 5.

Figure 6.

MINIMUM AND MAXIMUM DNL OF ALL CHANNELS

vs TEMPERATURE (100kSPS)

MINIMUM AND MAXIMUM DNL OF ALL CHANNELS

vs TEMPERATURE (250kSPS)

3.0

2.5

2.0

2.5

Max

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

-0.5

-1.0

-1.5

-2.0

Min

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

Figure 7.

Figure 8.

13

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= +5V, BV_DD= +3V, V_REF= internal +2.5V, f_CLK= 5MHz, and f_SAMPLE= 250kSPS, unless otherwise noted.

FREQUENCY SPECTRUM

(16384 point FFT, f_IN= 10kHz, –0.2dB)

FREQUENCY SPECTRUM

(16384 point FFT, f_IN= 45kHz, –0.2dB)

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

25

50

75

100

125

0

25

50

75

100

125

100

Frequency (kHz)

Figure 9.

Figure 10.

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-NOISE + DISTORTION

vs INPUT FREQUENCY (ALL CHANNELS)

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY (ALL CHANNELS)

100

95

90

85

80

75

70

120

115

110

105

100

95

SFDR

THD

SNR

SINAD

90

85

80

1

10

100

1

10

Frequency (kHz)

Figure 11.

Figure 12.

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-NOISE + DISTORTION

vs TEMPERATURE (ALL CHANNELS)

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs TEMPERATURE (ALL CHANNELS)

90.0

89.5

89.0

88.5

88.0

87.5

87.0

86.5

86.0

85.5

85.0

107

105

103

101

99

SFDR

THD

SNR

SINAD

97

95

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

Temperature (°C)

Figure 13.

Figure 14.

14

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= +5V, BV_DD= +3V, V_REF= internal +2.5V, f_CLK= 5MHz, and f_SAMPLE= 250kSPS, unless otherwise noted.

OFFSET OF ALL CHANNELS

vs TEMPERATURE

OFFSET MATCHING OF CHANNEL PAIRS

vs TEMPERATURE

-0.8

-0.9

-1.0

-1.1

-1.2

-1.3

-1.4

0.25

0.20

0.15

0.10

0.05

0

C0

A0

A1

B

A

C1

-0.05

-0.10

-0.15

-0.20

-0.25

B0

B1

C

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

Figure 15.

Figure 16.

GAIN ERROR OF ALL CHANNELS

vs TEMPERATURE

GAIN-ERROR MATCHING OF CHANNEL PAIRS

vs TEMPERATURE

100

50

100

50

B1

A0

B0

A1

B

C

A

0

C1

C0

-50

-100

-150

-50

-100

-150

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

Figure 17.

Figure 18.

REFERENCE VOLTAGE OUTPUT

vs TEMPERATURE

ANALOG SUPPLY CURRENT

vs TEMPERATURE

2.498

2.496

2.494

2.492

2.490

42

40

38

36

34

32

30

250kSPS

100kSPS

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

Figure 19.

Figure 20.

15

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

INTRODUCTION

signal) is 5ns. The average delta of repeated

aperture delay values (also known as aperture jitter)

is typically 50ps. These specifications reflect the

ability of the ADS8365 to capture ac input signals

accurately at the exact same moment in time.

The ADS8365 is

a

high-speed, low-power,

six-channel simultaneous sampling and converting,

16-bit ADC that operates from a single +5V supply.

The input channels are fully differential with a typical

common-mode rejection of 80dB. The ADS8365

contains six 4µs successive approximation ADCs, six

differential sample-and-hold amplifiers, an internal

+2.5V reference with REF_INand REF_OUTpins, and a

high-speed parallel interface. There are six analog

inputs that are grouped into three channel pairs (A,

B, and C). There are six ADCs, one for each input

that can be sampled and converted simultaneously,

thus preserving the relative phase information of the

signals on both analog inputs. Each pair of channels

has a hold signal (HOLDA, HOLDB, and HOLDC) to

allow simultaneous sampling on each channel pair,

on four or on all six channels. The part accepts a

differential analog input voltage in the range of –V_REF

to +V_REF, centered on the common-mode voltage

(see the Analog Input section). The ADS8365 also

accepts bipolar input ranges when a level shift circuit

is used at the front end (see Figure 26).

REFERENCE

Under normal operation, REF_OUT(pin 61) can be

directly connected to REF_IN(pin 62) to provide an

internal +2.5V reference to the ADS8365. The

ADS8365 can operate, however, with an external

reference in the range of 1.5V to 2.6V, for a

corresponding full-scale range of 3.0V to 5.2V, as

long as the input does not exceed the AV_DD+ 0.3V

limit.

The reference output of the ADS8365 has an

impedance of 2kΩ. The high impedance reference

input can be driven directly. For an external resistive

load, an additional buffer is required.

A load

capacitance of 0.1µF to 10µF should be applied to

the reference output to minimize noise. If an external

reference is used, the three input buffers provide

isolation between the external reference and the

CDACs. These buffers are also used to recharge all

the capacitors of all CDACs during conversion.

A conversion is initiated on the ADS8365 by bringing

the HOLDX pin low for a minimum of 20ns. HOLDX

low places the sample-and-hold amplifiers of the X

channels in the hold state simultaneously and the

conversion process is started on each channel. The

EOC output goes low for half a clock cycle when the

conversion is latched into the output register. The

data can be read from the parallel output bus

following the conversion by bringing both RD and CS

low. Conversion time for the ADS8365 is 3.2µs when

a 5MHz external clock is used. The corresponding

acquisition time is 0.8µs. To achieve the maximum

output data rate (250kSPS), the read function can be

performed during the next conversion. NOTE: This

mode of operation is described in more detail in the

Timing and Control section of this data sheet.

ANALOG INPUT

The analog input is bipolar and fully differential.

There are two general methods of driving the analog

input of the ADS8365: single-ended or differential, as

shown in Figure 21 and Figure 22. When the input is

single-ended, the –IN input is held at the

common-mode voltage. The +IN input swings around

the same common voltage and the peak-to-peak

amplitude is the (common-mode + V_REF) and the

(common-mode –V_REF). The value of V_REF

determines the range over which the common-mode

voltage may vary (see Figure 23).

SAMPLE AND HOLD

Single-Ended Input

The sample-and-hold amplifiers on the ADS8365

allow the ADCs to accurately convert an input sine

wave of full-scale amplitude to 16-bit resolution. The

input bandwidth of the sample-and-hold amplifiers is

greater than the Nyquist rate (Nyquist = 1/2 of the

sampling rate) of the ADC, even when the ADC is

operated at its maximum throughput rate of

250kSPS. The typical small-signal bandwidth of the

sample-and-hold amplifiers is 10MHz. Typical

aperture delay time (or the time it takes for the

ADS8365 to switch from the sample to the hold

mode following the negative edge of the HOLDX

-V_REFto +V_REF

ADS8365

peak-to-peak

Common

Voltage

Differential Input

V_REF

peak-to-peak

ADS8365

Common

V_REF

Voltage

peak-to-peak

Figure 21. Methods of Driving the ADS8365

Single-Ended or Differential

16

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

+IN

CM +V_REF

+V_REF

CM Voltage

-IN = CM Voltage

-V_REF

t

CM -V_REF

Single-Ended Inputs

+IN

+V_REF

CM +1/2V_REF

CM Voltage

-V_REF

-IN

t

CM -1/2V_REF

Differential Inputs

NOTES:

Common−mode voltage (Differential mode) =

(+IN) ) (−IN)

. Common−mode voltage (Single−ended mode) = −IN

2

The maximum differential voltage between +IN and –IN of the ADS8365 is V_REF. See Figure 23 and Figure 24 for a

further explanation of the common voltage range for single-ended and differential inputs.

Figure 22. Using the ADS8365 in the Single-Ended and Differential Input Modes

5

4

5

AV_DD= 5V

4.55

3.8

4

3

4.0

3

2.7

2.3

Differential Input

Single-Ended Input

2

1.2

1

1.0

0.45

0

- 1

2.6

2.5

2.6

2.5

1.0

1.5

2.0

3.0

1.0

1.5

2.0

3.0

V_REF(V)

Figure 23. Single-Ended Input: Common-Mode

Voltage Range vs V_REF

Figure 24. Differential Input: Common-Mode

Voltage Range vs V_REF

When the input is differential, the amplitude of the

input is the difference between the +IN and –IN

input, or: (+IN) – (–IN). The peak-to-peak amplitude

of each input is ±1/2V_REFaround this common

voltage. However, since the inputs are 180°

out-of-phase, the peak-to-peak amplitude of the

differential voltage is +V_REFto –V_REF. The value of

V_REFalso determines the range of the voltage that

may be common to both inputs, as shown in

Figure 24.

In each case, care should be taken to ensure that

the output impedance of the sources driving the +IN

and –IN inputs are matched. Often, a small capacitor

(20pF) between the positive and negative input helps

to match the impedance. Otherwise, a mismatch may

result in offset error, which will change with both

temperature and input voltage.

The input current on the analog inputs depends on a

number of factors, such as sample rate or input

voltage. Essentially, the current into the ADS8365

17

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

charges the internal capacitor array during the

sampling period. After this capacitance has been

fully charged, there is no further input current. The

source of the analog input voltage must be able to

charge the input capacitance (25pF) to a 16-bit

settling level within three clock cycles if the minimum

acquisition time is used. When the converter goes

into the hold mode, the input impedance is greater

than 1GΩ. Care must be taken regarding the

absolute analog input voltage. The +IN and –IN

inputs should always remain within the range of

AGND – 0.3V to AV_DD+ 0.3V.

BIPOLAR INPUTS

The differential inputs of the ADS8365 were

designed to accept bipolar inputs (–V_REFand +V_REF

)

around the common-mode voltage (2.5V), which

corresponds to a 0V to 5V input range with a 2.5V

reference. By using a simple op amp circuit featuring

four, high-precision external resistors, the ADS8365

can be configured to accept a bipolar input range.

The conventional ±2.5V, ±5V, and ±10V input ranges

could be interfaced to the ADS8365 using the

resistor values shown in Figure 26.

The OPA365 is a good choice for driving the analog

inputs in a 5V, single-supply application.

R₁

4kW

1.2kW

TRANSITION NOISE

+IN

OPA227

20kW

Bipolar

Input

The transition noise of the ADS8365 itself is low, as

shown in Figure 25 These histograms were

generated by applying a low-noise dc input and

initiating 8000 conversions. The digital output of the

ADC will vary in output code due to the internal noise

of the ADS8365; this feature is true for all 16-bit,

successive approximation register (SAR) type ADCs.

Using a histogram to plot the output codes, the

distribution should appear bell-shaped, with the peak

of the bell curve representing the nominal code for

the input value. The ±1σ , ±2σ , and ±3σ distributions

represent the 68.3%, 95.5%, and 99.7%,

respectively, of all codes. The transition noise can be

calculated by dividing the number of codes

measured by 6, yielding the ±3σ distribution, or

99.7%, of all codes. Statistically, up to three codes

could fall outside the distribution when executing

1000 conversions. Remember, in order to achieve

this low-noise performance, the peak-to-peak noise

of the input signal and reference must be < 50µV.

1.2kW

-IN

R₂

ADS8365

OPA227

REF_OUT(pin 61)

2.5V

BIPOLAR INPUT

R¹

R2

±10V

±5V

1kW

2kW

4kW

5kW

10kW

20kW

±2.5V

Figure 26. Level Shift Circuit for Bipolar Input

Ranges

TIMING AND CONTROL

The ADS8365 uses an external clock (CLK, pin 28)

that controls the conversion rate of the CDAC. With a

5MHz external clock, the ADC sampling rate is

250kSPS which corresponds to a 4µs maximum

throughput time. Acquisition and conversion take a

total of 20 clock cycles.

4000

3379

3500

3000

2500

2000

1500

1000

500

3290

649

603

37

42

0

32782 32783 32784 32785 32786 32787

Code

Figure 25. 8000 Conversion Histogram of a DC

Input

18

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

THEORY OF OPERATION

switches. The reset signal must stay

low for at least 20ns (see Figure 27,

t_W4). The reset signal should be back

The ADS8365 contains six 16-bit ADCs that can

operate simultaneously in pairs. The three hold

signals (HOLDA, HOLDB, and HOLDC) initiate the

conversion on the specific channels. A simultaneous

hold on all six channels can occur with all three hold

signals strobed together. The converted values are

saved in six registers. For each read operation, the

ADS8365 outputs 16 bits of information (16 data or 3

high for at least 20ns (Figure 27, t_D2

)

before starting the next conversion

(negative hold edge).

EOC

End of conversion goes low when new

data from the internal ADC are latched

into the output registers, which usually

happens 16.5 clock cycles after hold

initiated the conversion. It remains low

for half a clock cycle. If more than one

channel

address,

data

valid,

and

some

synchronization information). The address/mode

signals (A0, A1, and A2) select how the data are

read from the ADS8365. These address/mode

signals can define a selection of a single channel, a

cycle mode that cycles through all channels, or a

FIFO mode that sequences the data determined by

the order of the hold signals. The FIFO mode will

allow the six registers to be used by a single-channel

pair; therefore, three locations for CH X0 and three

locations for CH X1 can be updated before they are

read from the device.

channel

pair

is

converted

simultaneously, the A-channels get

stored to the registers first (16.5 clock

cycles after hold), followed by the

B-channels one clock cycle later, and

finally the C-channels another clock

cycle later. If a reading (both RD and

CS are low) is in process, then the

latch process is delayed until the read

operation is finished.

EXPLANATION OF CLOCK, RESET, FD, AND

EOC PINS

FD

First data or A0 data are high if channel

A0 is chosen to be read next. In FIFO

mode, the channel (X0) that is written

to the FIFO first is latched into the A0

register. For example, when the FIFO

is empty, FD is 0. The first result

latched into the FIFO register A0 is,

therefore, chosen to be read next, and

FD rises. After the first channel is read

(one to three read cycles, depending

on BYTE and ADD), FD goes low

again.

Clock

An external clock has to be provided for

the ADS8365. The maximum clock

frequency is 5MHz. The minimum clock

cycle is 200ns (see Figure 1, t_C1), and

the clock has to remain high (Figure 1,

t_W1) or low for at least 60ns.

RESET

Bringing the RESET signal low will

reset the ADS8365. Resetting clears

the control register and all the output

registers, aborts any conversion in

process, and closes the sampling

t_C1

CLK

t_W1

tD1

HOLD A

tW3

HOLD B

HOLD C

tD2

tW2

tW4

RESET

Figure 27. Start of the Conversion

19

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

START OF A CONVERSION AND READING

DATA

The ADS8365 can also convert one channel

continuously (see Figure 28). Therefore, HOLDA and

HOLDC are kept high all the time. To gain

acquisition time, the falling edge of HOLDB takes

place just before the rising edge of clock. One

conversion requires 20 clock cycles. Here, data are

read after the next conversion is initiated by HOLDB.

To read data from channel B, A1 is set high and A2

is low. Since A0 is low during the first reading (A2 A1

A0 = 010), data B0 are put to the output. Before the

second RD, A0 switches high (A2 A1 A0 = 011) so

that data from channel B1 are read, as shown in

Table 1. However, reading data during the

conversion or on a falling hold edge might cause a

loss in performance.

By bringing one, two, or all three of the HOLDX

signals low, the input data of the corresponding

channel X are immediately placed in the hold mode

(5ns). The conversion of this channel X follows with

the next rising edge of clock. If it is important to

detect a hold command during a certain clock-cycle,

then the falling edge of the hold signal has to occur

at least 10ns before the rising edge of clock, as

shown in Figure 27, t_D1. The hold signal can remain

low without initiating a new conversion. The hold

signal must be high for at least 15ns (as shown in

Figure 27, t_W2) before it is brought low again, and

hold must stay low for at least 20ns (Figure 27, t_W3).

Table 1. Address Control for RD Functions

Once a particular hold signal goes low, further

impulses of this hold signal are ignored until the

conversion is finished or the device is reset. When

the conversion is finished (after 16 clock cycles) the

sampling switches close and sample the selected

channel. The start of the next conversion must be

delayed to allow the input capacitor of the ADS8365

to be fully charged. This delay time depends on the

driving amplifier, but should be at least 800ns.

A2

0

A1

0

A0

0

CHANNEL TO BE READ

CH A0

CH A1

CH B0

CH B1

CH C0

CH C1

0

1

0

1

0

1

0

1

0

1

Cycle mode reads registers CH A0

to CH C1 on successive transitions

of the read line

1

0

1

FIFO mode

CONVERSION

ACQUISITION

19

CLK

1

2

16

17

18

20

1

2

HOLD B

EOC

CS

RD

A0

Figure 28. Timing of One Conversion Cycle

20

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

Reading data (RD and CS)

CS being low tells the ADS8365 that the bus on the

board is assigned to the ADS8365. If an ADC shares

a bus with digital gates, there is a possibility that

digital (high-frequency) noise will be coupled into the

ADC. If the bus is just used by the ADS8365, CS can

be hardwired to ground. Reading data at the falling

edge of one of the HOLDX signals might cause

noise.

In general, the channel/data outputs are in tri-state.

Both CS and RD must be low to enable these

outputs. RD and CS must stay low together for at

least 40ns (see Figure 1, t_D6) before the output data

are valid. RD must remain HIGH for at least 30ns

(see Figure 1, t_W5) before bringing it back low for a

subsequent read command.

The new data are latched into its output register 16.5

clock cycles after the start of a conversion (next

rising edge of clock after the falling edge of HOLDX).

Even if the ADS8365 is forced to wait until the read

process is finished (RD signal going high) before the

new data are latched into its output register, the

possibility still exists that the new data was latched to

the output register just before the falling edge of RD.

If a read process is initiated around 16.5 clock cycles

after the conversion started, RD and CS should stay

low for at least 50ns (see Figure 1, t_W6) to get the

new data stored to its register and switched to the

output.

BYTE

If there is only an 8-bit bus available on a board,

then BYTE can be set high (see Figure 29). In this

case, the lower eight bits can be read at the output

pins D15 to D8 or D7 to D0 at the first RD signal,

and the higher bits after the second RD signal. If the

ADS8365 is used in the cycle or the FIFO mode,

then the address and data valid information is added

to the data (if ADD is high). In this case, the address

will be read first, then the lower eight bits, and finally

the higher eight bits. If BYTE is low, then the

ADS8365 operates in the 16-bit output mode. Here,

data are read between pins DB15 and DB0. As long

as ADD is low, with every RD impulse, data from a

new channel are brought to the output. If ADD is high

and the cycle or the FIFO mode is chosen; the first

output word contains the address, while the second

output word contains the 16-bit data.

CS

RD

BYTE

A0

A1

B0

B1

C0

C1

A0

D7 – D0

LOW

HIGH

LOW

HIGH

LOW

HIGH

Figure 29. Reading Data in Cycling Mode

21

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

ADD Signal

If conversion timing between ADCs is not critical,

Soft Trigger mode can allow all three HOLDX signals

to be triggered simultaneously. This simultaneous

triggering can be done by tying all three HOLDX pins

high, and issuing a write (CS and WR low) with the

DB0, DB1, DB2, and DB7 bits low, and the reset bit

(DB3) high. Writing a low to the reset bit (DB3) while

the RESET pin is high forces a device reset, and all

HOLDX signals that occur during that time are

ignored.

In the cycle and the FIFO mode, it might be desirable

to have address information with the 16-bit output

data. Therefore, ADD can be set high. In this case,

two RD signals (or three readings if the part is

operated with BYTE being high) are necessary to

read data of one channel, while the ADS8365

provides channel information on the first RD signal

(see Table 2 and Table 3).

Soft Trigger Mode

The HOLDX signals start conversion automatically

on the next clock cycle. The format of the two words

that can be written to the ADS8365 are shown in

Table 4.

Signals NAP, ADD, A0, A1, A2, RESET, HOLDA,

HOLDB, and HOLDC are accessible through the

data bus and control word. Bits NAP, ADD, A0, A1

and A2 are in an OR configuration with hardware

pins. When software configuration is used, these

pins must be connected to ground. Conversely, the

RESET, HOLDA, HOLDB, and HOLDC bits are in a

NAND configuration with the hardware pins. When

software configuration is used, these pins must be

Bits DB5 and DB4 do not have corresponding

hardware pins. Bit DB5 = 1 enables Powerdown

mode. Bit DB4 = 1 inverts the MSB of the output

data, putting the output data in two's complement

format. When DB4 is low, the data is in straight

binary format.

connected to BV_DD

.

Table 2. Overview of the Output Formats Depending on Mode When ADD = 0

ADD = 0

A2 A1 A0

000

BYTE = 0

BYTE = 1

2nd RD

1st RD

2nd RD

1st RD

3rd RD

DB15...DB0

No 2nd RD

DB7...DB0

DB15...DB8

No 3rd RD

001

010

011

100

101

110

111

Table 3. Overview of the Output Formats Depending on Mode When ADD = 1

ADD = 1

A2 A1 A0

000

BYTE = 0

BYTE = 1

2nd RD

1st RD

2nd RD

1st RD

DB7...DB0

3rd RD

DB15...DB0

No 2nd RD

DB15...DB0

DB15...DB8

DB7...DB0

No 3rd RD

DB15...DB8

001

DB7...DB0

010

DB15...DB0

DB7...DB0

011

DB15...DB0

DB7...DB0

100

DB15...DB0

DB7...DB0

101

DB15...DB0

DB7...DB0

110

1000 0000 0000 DV A2 A1 A0

DV A2 A1 A0 DB3 DB2 DB0

111

Table 4. Control Register Bits

DB7 (MSB)

DB6

NAP

X

DB5

PD

X

DB4

Invert MSB

X

DB3

ADD

DB2

A2

DB1

A1

DB0 (LSB)

A0

1

0

RESET

HOLDA

HOLDB

HOLDC

22

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

NAP AND POWERDOWN MODE CONTROL

B1, C0, and finally, C1 before reading A0 again.

Data from channel A0 are brought to the output first

after a reset signal, or after powering up the device.

The third mode is a FIFO mode that is addressed

with (A2, A1, A0 = 111). Data of the channel that is

converted first is read first. So, if a particular channel

pair is most interesting and is converted more

frequently (for example, to get a history of a

particular channel pair), then there are three output

registers per channel available to store data.

In order to minimize power consumption when the

ADS8365 is not in use, two low-power options are

available. Nap mode minimizes power without

shutting down the biasing circuitry and internal

reference, allowing immediate recovery after it is

disabled. It can be enabled by either the NAP pin

going high, or setting DB6 in the data register high.

Enabling Powerdown mode results in lower power

consumption than Nap mode, but requires a short

recovery period after disabling. It can only be

enabled by setting DB5 in the data register high.

If all the output registers are filled up with unread

data and new data from an additional conversion

must be latched in, then the oldest data is discarded.

If a read process is going on (RD signal low) and

new data must be stored, then the ADS8365 waits

until the read process is finished (RD signal going

high) before the new data gets latched into its output

register. Again, with the ADD signal, it can be

chosen whether the address should be added to the

output data.

GETTING DATA

Flexible Output Modes: A0 A1, and A2.

The ADS8365 has three different output modes that

are selected with A2, A1, and A0. The A2, A1 and

A0 pins are held with a transparent latch that triggers

on a falling edge of the RD pin negative-ANDed with

the CS pin (that is, if either RD or CS is low, the

falling edge of the other will latch A0-2).

New data is always written into the next available

register. At t₀(see Figure 31), the reset deletes all

the existing data. At t₁, the new data of the channels

A0 and A1 are put into registers 0 and 1. At t₂, a

dummy read (RD low) is performed to latch the

address data correctly. At t₃, the read process of

channel A0 data is finished; therefore, these data are

dumped and A1 data are shifted to register 0. At t₄,

new data are available, this time from channels B0,

B1, C0, and C1. These data are written into the next

available registers (registers 1, 2, 3, and 4).

When (A2, A1, A0) = 000 to 101, a particular channel

can be directly addressed (see Table

1 and

Figure 30). The channel address should be set at

least 10ns (see Figure 30, t_D9) before the falling edge

of RD and should not change as long as RD is low.

In this standard address mode, ADD will be ignored,

but should be connected to either ground or supply.

When (A2, A1, A0) = 110, the interface is running in

a cycle mode (see Figure 29). Here, data 7 down to

data 0 of channel A0 is read on the first RD signal,

and data 15 down to data 8 on the second as BYTE

is high. Then A1 on the second RD, followed by B0,

CLK

16

17

18

19

20

1

2

t_D1

HOLD X

t_ACQ

EOC

CS

t_D8

t_D7

RD

A0

t_D9

Figure 30. Timing for Reading Data

23

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

RESET

EOC

RD

Conversion

Channel A

Conversion

Channel C

Channels B and C

empty

CH A1

CH A0

empty

CH A1

empty

CH C1

CH C0

empty

CH C1

CH C0

CH B1

CH B0

CH C1

CH C0

CH C1

CH C0

CH B1

CH B0

Register 5

Register 4

Register 3

Register 2

CH B1

CH B0

CH A1

Register 1

Register 0

t₀

t₁

t₂

t₃

t₄

t₅

t₆

Figure 31. Functionality Diagram of the FIFO Registers

On t₅, the new read process of channel A1 data is

finished. The new data of channel C0 and C1 at t₆

are put on top (registers 4 and 5).

second RD, the 16-bit data word can be read

(DB15…DB0). If BYTE = 1, then three RD impulses

are needed. On the first RD impulse, data valid, the

three address bits, and data bits DB3…DB0 (DV, A2,

A1, A0, DB3, DB2, DB1, DB0) are read, followed by

the eight lower bits of the 16-bit data word

(db7…db0), and finally the higher eight data bits

(DB15…DB8). 1000 0000 0000 is added before the

address in case BYTE = 0, and DB3…DB0 is added

after the address if BYTE = 1. This provides the

possibility to check if the counting of the RD signals

inside the ADS8365 are still tracking with the

external interface (see Table 2 and Table 3).

In Cycle mode and in FIFO mode, the ADS8365

offers the ability to add the address of the channel to

the output data. Since there is only a 16-bit bus

available (or 8-bit bus in the case BYTE is high), an

additional RD signal is necessary to get the

information (see Table 2 and Table 3).

In FIFO mode, a dummy read signal (RD) is required

after

a reset signal to set the address bits

appropriately; otherwise, the first conversion will not

be valid. This is only necessary in FIFO mode.

The data valid bit is useful for the FIFO mode. Valid

data can simply be read until the data valid bit equals

0. The three address bits are listed in Table 5. If the

FIFO is empty, 16 zeroes are loaded to the output.

The Output Code (DB15 …DB0)

In the standard address mode (A2 A1 A0

=

000…101), the ADS8365 has a 16-bit output word

on pins DB15…DB0, if BYTE = 0. If BYTE = 1, then

two RD impulses are necessary to first read the

lower bits, and then the higher bits on either

DB7…DB0 or DB15...DB8.

Table 5. Address Bit in the Output Data

DATA FROM ...

Channel A0

Channel A1

Channel B0

Channel B1

Channel C0

Channel C1

A2

0

A1

0

A0

0

1

If the ADS8365 operates in Cycle or in FIFO mode

and ADD is set high, then the address of the channel

(A2A1A0) and a data valid (DV) bit are added to the

data. If BYTE = 0, then the data valid and the

address of the channel is active during the first RD

impulse (1000 0000 0000 DV A2 A1 A0). During the

0

1

0

1

0

1

0

1

24

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

Binary Two's Complement (BTC)

65535

0111111111111111

0111111111111110

0111111111111101

65534

65533

32769

32768

32767

0000000000000001

0000000000000000

1111111111111111

1000000000000010

1000000000000001

1000000000000000

2

1

0

VNFS = V_CM- V_REF= 0V

2.499962V

2.500038V

VPFS = V_CM+ V_REF= 5V

VPFS - 1LSB = 4.999924V

4.999848V

0.000038V

0.000076V

0.000152V

VBPZ = 2.5V

Unipolar Analog Input Voltage

1LSB = 76V

V_CM= 2.5V

V_REF= 2.5V

16-BIT

Bipolar Input, Binary Two’s Complement Output: (BTC)

Negative Full-Scale Code = VNFS = 8000H, Vcode = V_CM- V_REF

Bipolar Zero Code = VBPZ = 0000H, Vcode = V_CM

Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (V_CM+ V_REF) - 1LSB

Figure 32. Ideal Conversion Characteristics (Condition: Single-Ended, V_CM= chXX– = 2.5V, V_REF= 2.5V)

25

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

LAYOUT

capacitor and a 5Ω or 10Ω series resistor may be

used to low-pass filter a noisy supply. On average,

the ADS8365 draws very little current from an

external reference because the reference voltage is

internally buffered. A bypass capacitor of 0.1µF and

10µF are suggested when using the internal

reference (tie pin 61 directly to pin 62).

For optimum performance, care should be taken with

the physical layout of the ADS8365 circuitry. This

recommendation is particularly true if the CLK input

is approaching the maximum throughput rate.

The basic SAR architecture is sensitive to glitches or

sudden changes on the power supply, reference,

ground connections, and digital inputs that occur just

prior to latching the output of the analog comparator.

Thus, driving any single conversion for an n-bit SAR

converter, there are n windows in which large

external transient voltages can affect the conversion

result. Such glitches might originate from switching

power supplies, nearby digital logic, or high-power

devices. The degree of error in the digital output

depends on the reference voltage, layout, and the

exact timing of the external event. Their error can

change if the external event changes in time with

respect to the CLK input.

GROUNDING

The AGND pins should be connected to a clean

ground point. In all cases, this point should be the

analog ground. Avoid connections that are too close

to the grounding point of a microcontroller or digital

signal processor. If required, run a ground trace

directly from the converter to the power-supply entry

point. The ideal layout includes an analog ground

plane dedicated to the converter and associated

analog circuitry. Three signal ground pins (SGND)

are the input signal grounds that are on the same

potential as analog ground.

With this information in mind, power to the ADS8365

should be clean and well-bypassed. A 0.1µF ceramic

bypass capacitor should be placed as close to the

device as possible. In addition, a 1µF to 10µF

capacitor is recommended. If needed, an even larger

26

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

APPLICATION INFORMATION

Different connection diagrams to DSPs or microcontrollers are shown in Figure 33 through Figure 39.

5V

2.048V

AV_DD

REF3220

REF_IN

100nF

5V

V+

REF_OUT

100kW

20kW

OPA343

-IN

SENSE

OUT

0.5V to 4.5V

100W

CH A0+

100kW

40kW

1nF

V_REF

V_IN+IN

A0

REF 2

REF 1

CH A0-

2.5V

±10V

INA159

ADS8365

100W

-IN

OUT

CH A1+

1nF

INA159

V_IN

A1

CH A1-

+IN

REF 1/2

CH B0+

CH B0-

CH B1+

CH B1-

CH C0+

CH C0-

100W

-IN

OUT

CH C1+

1nF

INA159

V_IN

C1

CH C1-

+IN

REF 1/2

SGND

AGND

Figure 33. ±10V Input Range By Using the INA159

27

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

APPLICATION INFORMATION (continued)

3.3V

ADS8365

C28xx

BV_DD

DV_DD

PWM1

PWM2

PWM3

EA0

56

57

58

54

53

52

BV_DD

HOLDA

HOLDB

HOLDC

A0

26

FD

30

23

WR

A1

EA1

ADD

BYTE

55

A2

EA2

EA3

31

8:1

OE

CS

IS

29

RD

EOC

RE

27

28

51

EXT_INT1

MCLKX

CLK

ADC_RST (MFSX)

RESET

DATA [0]

...

D0

...

48

...

DATA [15]

33

D15

V_SS

BGND

Figure 34. Typical C28xx Connection (Hardware Control)

3.3V

BV_DD

ADS8365

C28xx

56

57

BV_DD

DV_DD

HOLDA

HOLDB

58

26

A2

A1

A0

IS

HOLDC

FD

8:1

OE

23

55

54

53

52

ADD

BYTE

A0

31

29

30

CS

RD

RE

WE

A1

WR

27

28

EXT_INT1

MCLKX

EOC

A2

CLK

D0

...

DATA [0]

...

48

...

33

D15

DATA [15]

V_SS

BGND

Figure 35. Typical C28xx Connection (Software Control)

28

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

APPLICATION INFORMATION (continued)

3.3V

ADS8365

C67xx

BV_DD

DV_DD

BV_DD

56

57

58

TOUT1

HOLDA

HOLDB

HOLDC

30

53

WR

A1

A2

A1

8:1

OE

52

23

54

A0

A2

31

55

29

ADD

A0

CS

IS

BE0

RE

BYTE

RD

27

28

51

INT0

TOUT0

EOC

CLK

DB_CNTL0 (ED27)

RESET

D0

...

DATA [0]

...

48

...

33

D15

DATA [15]

V_SS

BGND

Figure 36. Typical C67xx Connection (Cycle Mode—Hardware Control)

BV_DD

3.3V

ADS8365

HOLDA

C67xx

56

57

58

26

23

55

BV_DD

DV_DD

HOLDB

HOLDC

FD

A2

A1

8:1

OE

A0

ADD

BYTE

A0

31

29

30

CS

RD

IS

54

53

52

RE

WE

INT0

TOUT0

A1

WR

27

28

EOC

A2

CLK

D0

...

DATA [0]

...

48

...

33

D15

DATA [15]

V_SS

BGND

Figure 37. Typical C67xx Connection (Software Control)

29

Submit Documentation Feedback

ADS8365

www.ti.com

SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006

APPLICATION INFORMATION (continued)

3.3V

ADS8365

C54xx

BV_DD

DV_DD

56

57

58

BV_DD

TOUT0

HOLDA

HOLDB

HOLDC

A2

A1

A0

IS

26

54

53

FD

8:1

OE

A0

31

29

30

CS

RD

A1

52

30

23

55

A2

<

1

WR

ADD

BYTE

27

28

51

I/OSTRB

(1G32)

INT0

EOC

CLK

BCLKX1

XF

RESET

DATA [0]

...

D0

...

48

...

33

DATA [15]

D15

V_SS

BGND

Figure 38. Typical C54xx Connection (FIFO Mode—Hardware Control)

3.3V

ADS8365

MSP430x1xx

DV_DD

BV_DD

56

57

58

31

51

27

28

TACLK (P1.0)

HOLDA

HOLDB

HOLDC

CS

30

52

54

WR

ADD

A1

P1.1

53

23

55

A2

RESET

EOC

P1.2

P1.3 (ADC_INT)

SMCLK (P1.4)

BYTE

A0

CLK

29

DATA [0]

...

RD

P2.0

...

48

...

41

DATA [7]

P2.7

V_SS

BGND

Figure 39. Typical MSP430x1xx Connection (Cycle Mode—Hardware Control)

30

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2006

PACKAGING INFORMATION

Orderable Device

ADS8365IPAG

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TQFP

PAG

64

96 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

ADS8365IPAGR

ADS8365IPAGRG4

TQFP

PAG

1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PAG (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

48

M

0,08

33

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

11,80

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4040282/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Low Power Wireless www.ti.com/lpw

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	ADS8365IPAGR
厂家：	BURR-BROWN CORPORATION
描述：	16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS 16位， 250ksps的， 6通道，同步采样SAR模拟数字转换器转换器
文件：	总33页 (文件大小：643K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8365IPAGR [BB]

相关型号：

ADS8365IPAGRG4

ADS8370

ADS8370

ADS8370I

ADS8370IB

ADS8370IBRHPR

ADS8370IBRHPRG4

ADS8370IBRHPT

ADS8370IBRHPTG4

ADS8370IRHPR

ADS8370IRHPRG4

ADS8370IRHPT