DAC2932PFBR [BB]
DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER; 双通道12位40MSPS数字模拟转换器
| 型号： | DAC2932PFBR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER |
| 文件： | 总24页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ
ꢒ
ꢕ
ꢆ
ꢙ
ꢚ
ꢆ
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇ ꢈꢉ ꢊ ꢄ ꢋꢌ ꢍꢎ ꢏꢎ
ꢀ ꢉꢐ ꢉꢊ ꢂꢃꢇ ꢊ ꢑꢇ ꢒ ꢓꢂ ꢃꢑ ꢐꢔ ꢕꢑꢓꢖ ꢗ ꢘ ꢊꢗ ꢘ
FEATURES
DESCRIPTION
The DAC2932 is
a
dual 12-bit, current-output
D
D
Dual, 12-Bit, 40MSPS Current Output DAC
digital-to-analog converter (DAC) designed to combine the
features of high dynamic range and very low power
consumption. The DAC2932 converter supports update
rates of up to 40MSPS. In addition, the DAC2932 features
four 12-bit voltage output DACs, which can be used to
perform system control functions.
Four 12-Bit Voltage Output DACs—for
Transmit Control
D
D
D
D
Single +3V Operation
Very Low Power: 29mW
The advanced segmentation architecture of the DAC2932
is optimized to provide a high spurious-free dynamic range
(SFDR).
High SFDR: 75dB at f
= 5MHz
OUT
Low-Current Standby or Full Power-Down
Modes
The DAC2932 has a high impedance (> 200kΩ) differential
current output with a nominal range of 2mA and a
compliance voltage of up to 0.8V. The differential outputs
allow for either a differential or single-ended analog signal
interface. The close matching of the current outputs
ensures superior dynamic performance in the differential
D
D
D
Internal Reference
Optional External Reference
Adjustable Full-Scale Range: 0.5mA to 2mA
configuration, which can be implemented with
a
transformer. Using a small geometry CMOS process, the
monolithic DAC2932 is designed to operate within a
single-supply range of 2.7V to 3.3V. Low power
consumption makes it ideal for portable and
battery-operated systems. Further optimization by
lowering the output current can be realized with the
adjustable full-scale option. The full-scale output current
can be adjusted over a span of 0.5mA to 2mA.
APPLICATIONS
D
Transmit Channels
− I and Q
− PC Card Modems: GPRS, CDMA
− Wireless Network Cards (NICs)
For noncontinuous operation of the DAC2932, a full
power-down mode can reduce the power dissipation to as
little as 25µW.
D
D
D
Signal Synthesis (DDS)
Portable Medical Instumentation
Arbitrary Waveform Generation (AWG)
The DAC2932 is designed to operate with a single parallel
data port. While it alternates the loading of the input data
into separate input latches for both current output DACs
(I-DACs), the updating of the analog output signal occurs
simultaneously. The DAC2932 integrates a temperature
compensated 1.22V bandgap reference. The DAC2932
also allows for additional flexibility of using an external ref-
erence.
The DAC2932 is available in a TQFP-48 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢏꢛ ꢜ ꢀꢝ ꢕ ꢞꢟ ꢜꢠ ꢀ ꢒꢞꢒ ꢉꢓ ꢡꢑ ꢘ ꢢꢂ ꢊꢉꢑꢓ ꢉꢣ ꢤꢁ ꢘ ꢘ ꢗꢓꢊ ꢂꢣ ꢑꢡ ꢥꢁꢦ ꢃꢉꢤ ꢂꢊꢉ ꢑꢓ ꢧꢂ ꢊꢗꢨ ꢏꢘ ꢑꢧꢁ ꢤꢊꢣ
ꢤ ꢑꢓ ꢡꢑꢘ ꢢ ꢊꢑ ꢣ ꢥꢗ ꢤ ꢉ ꢡꢉ ꢤ ꢂ ꢊꢉ ꢑꢓꢣ ꢥ ꢗꢘ ꢊꢩꢗ ꢊꢗ ꢘ ꢢꢣ ꢑꢡ ꢞꢗꢪ ꢂꢣ ꢟꢓꢣ ꢊꢘ ꢁꢢ ꢗꢓꢊ ꢣ ꢣꢊ ꢂꢓꢧ ꢂꢘ ꢧ ꢫ ꢂꢘ ꢘ ꢂ ꢓꢊꢬꢨ
ꢏꢘ ꢑ ꢧꢁꢤ ꢊ ꢉꢑ ꢓ ꢥꢘ ꢑ ꢤ ꢗ ꢣ ꢣ ꢉꢓ ꢐ ꢧꢑ ꢗ ꢣ ꢓꢑꢊ ꢓꢗ ꢤꢗ ꢣꢣ ꢂꢘ ꢉꢃ ꢬ ꢉꢓꢤ ꢃꢁꢧ ꢗ ꢊꢗ ꢣꢊꢉ ꢓꢐ ꢑꢡ ꢂꢃ ꢃ ꢥꢂ ꢘ ꢂꢢ ꢗꢊꢗ ꢘ ꢣꢨ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
ꢀ
ꢒ
ꢕ
ꢆ
ꢙ
ꢚ
ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
DAC2932PFBT
DAC2932PFBR
Tape and Reel, 250
Tape and Reel, 2000
DAC2932
TQFP-48
PFB
−40°C to +85°C
DAC2932
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
DAC2932
−0.3 to +4
−0.3 to +4
−0.2 to +0.2
−0.7 to +0.7
UNIT
proper handling and installation procedures can cause damage.
+V to AGND
V
V
A
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
+V to DGND
D
AGND to DGND
V
+V to +V
V
A
D
CLK, PD, STBY, CS to DGND
D0−D11 to DGND
−0.3 to V + 0.3
V
D
−0.3 to V + 0.3
V
D
I
, I
to AGND
−0.5 to V + 0.3
V
OUT OUT
A
REFV to AGNDV
−0.3 to V + 0.3
AV
V
GSET, REF , FSA to AGND
−0.3 to V + 0.3
V
IN
x to AGNDV
A
V
OUT
−0.3 to V + 0.3
AV
V
DIN to DGNDV
−0.3 to V
DV
+ 0.3
V
Junction temperature
Case temperature
+150
°C
°C
°C
+100
Storage temperature range
−40 to +150
FUNCTIONAL BLOCK DIAGRAM
REFIN GSET
FSA1 FSA2
+VA
AGND
+VD
DGND
STBY
DAC2932
+1.22V Reference
Clock
Reference Control Amp
CS
PD
IOUT1
IOUT1
12−Bit
40MSPS
I−DAC1
Data1
CLK1
DAC
Latch 1
CLK
Parallel Data Input,
[D0:D11]
12−Bit Data,
Interleaved
IOUT2
IOUT2
12−Bit
40MSPS
I−DAC2
Data2
CLK2
DAC
Latch 2
I−DAC Section
V−DAC Section
A
12
A0
Dx
12−Bit
String−DAC1
VOUT1
VOUT2
VOUT3
VOUT4
Latch
Latch
Latch
Latch
DIN
12−Bit
String−DAC2
A
A1
A2
A3
SCLK
SYNC
12−Bit
String−DAC3
A
A
12−Bit
String−DAC4
REFV
PDV +VDV DGNDV +VAV AGNDV
2
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS: I-DAC
At T = T
to T
(typical values are at T = 25°C), +V = +3V, +V = +3V, Update Rate = 40MSPS, I
= 2mA, R = 250Ω, C ≤ 10pF,
A
MIN
MAX
A
A
D
OUTFS
L
L
GSET = H, and internal reference, unless otherwise noted.
DAC2932
TYP
PARAMETER
Resolution
TEST CONDITIONS
MIN
MAX
+85
UNITS
12
40
Bits
MSPS
°C
Output update rate (f
)
CLOCK
Specified temperature range, operating
(1)(2)
Ambient, T
−40
A
Static Accuracy
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
−3.5
−8
0.5
1.5
+3.5
+8
LSB
LSB
(3)
Dynamic Performance
Spurious-free dynamic range (SFDR)
To Nyquist, 0dBFS
f
f
f
f
f
f
f
= 0.2MHz, f
CLOCK
= 20MSPS
= 40MSPS
(4)
68
71
70
72
75
69
57
dBc
dBc
dBc
dBc
dBc
dBc
dBc
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 0.55MHz, f
CLOCK
= 1MHz, f
CLOCK
= 25MSPS
= 40MSPS
= 40MSPS
58
= 2.2MHz, f
CLOCK
= 5MHz, f
CLOCK
= 10MHz, f
= 40MSPS
= 40MSPS
CLOCK
CLOCK
= 20MHz, f
Spurious-free dynamic range within a
window
f
f
= 2.2MHz, f
= 40MSPS
= 40MSPS
1MHz span
2MHz span
76
74
dBc
dBc
OUT
CLOCK
= 10MHz, f
OUT
CLOCK
Total harmonic distortion (THD)
f
f
f
= 0.55MHz, f
CLOCK
= 40MSPS
(4)
−70
−69
−70
dBc
dBc
dBc
OUT
OUT
OUT
= 1MHz, f
= 25MSPS
−58
52
CLOCK
= 2.2MHz, f
CLOCK
= 40MSPS
Signal-to-noise and distortion (SINAD)
(4)
f
= 1MHz, f
= 25MSPS
61
20
dBc
ns
OUT
CLOCK
(1)
Output settling time
to 0.1%
(1)
Output rise time
10% to 90%
10% to 90%
7.7
7.4
ns
(1)
Output fall time
ns
DC Accuracy
(5)(6)
Full-scale output range
(FSR)
All bits high, I
, I
0.5
−0.5
−2
2
mA
V
OUT1 OUT2
(7)
Output compliance range , V
Gain error (Full-Scale)
Gain error drift
+0.5
0.5
+0.8
+2
CO
%FSR
ppmFSR/°C
%FSR
%FSR
%FSR/V
%FSR/V
kΩ
70
Gain matching
−2.5
+0.6
0.001
+0.5
+0.03
200
5
+2.5
Offset error
Power-supply rejection, +V
+3V, 10%, at 25°C
+3V, 10%, at 25°C
−0.9
+0.9
A
Power-supply rejection, +V
Output resistance
−0.12
+0.12
D
Output capacitance
I
, I
to Ground
pF
OUT OUT
(1)
At output I
Measured at f
, I
, while driving a 250Ω load, transition from 000h to FFFh.
OUT1 OUT2
(2)
(3)
(4)
= 25MSPS and f
= 1.0MHz.
CLOCK OUT
Differential, transformer (n = 4:1) coupled output, R = 400Ω.
Differential outputs with a 250Ω load.
L
V
Nominal full−scale output current is IOUTFS + 32 IREF + 32 REF ; with VREF + 1.22V (typ) and R
Ensured by design and characterization; not production tested.
Gain error to remain ≤10% FSR over the full compliance range.
Combined power dissipation of I-DAC and V-DAC.
+ 19.6kW (1%)
(5)
SET
RSET
(6)
(7)
(8)
3
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS: I-DAC (continued)
At T = T
to T
(typical values are at T = 25°C), +V = +3V, +V = +3V, Update Rate = 40MSPS, I
= 2mA, R = 250Ω, C ≤ 10pF,
A
MIN
MAX
A
A
D
OUTFS
L
L
GSET = H, and internal reference, unless otherwise noted.
DAC2932
TYP
PARAMETER
Reference
TEST CONDITIONS
MIN
MAX
UNITS
Voltage, V
Tolerance
+1.14
+1.22
30
+1.26
V
mV
REF
Voltage drift
−40
10
ppm/°C
µA
Output current
Input resistance
1
MΩ
Input compliance range
Small-signal bandwidth
External V
REF
+1.22
0.1
V
MHz
(6)
Digital Inputs
Logic coding
Straight binary
Logic high voltage, V
IH
+2
+3
0
V
Logic low voltage, V
Logic high current
Logic low current
Input capacitance
Power Supply
+0.8
V
IL
1
µA
µA
pF
1
5
Analog supply voltage, +V , +V
AV
2.7
2.7
3
3
3.3
3.3
V
A
Digital supply voltage, +V , +V
V
D
DV
Analog supply current, I
f
= 25MSPS, digital inputs at 0
4.7
5.4
0.4
2
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
µW
VA
VA
VA
VD
VD
VD
VD
CLOCK
I
I
f
= 40MSPS, f = 2.2MHz
OUT
Standby mode
CLOCK
Digital supply current, I
f
CLOCK
f
= 25MSPS, digital inputs at 0
l
= 40MSPS, f
OUT
= 2.2MHz
4.3
0.02
1.3
20
CLOCK
I
I
Standby mode, clock off
Standby mode, CS = 0, f = 25MSPS
CLOCK
= 25MSPS, digital inputs at 0
(8)
Power dissipation, PD
f
25
7
CLOCK
PD
f
= 40MSPS, f
= 2.2MHz
OUT
= 25MSPS
29
CLOCK
Standby mode, f
PD
PD
5.5
25
CLOCK
Power-down mode, clock off, digital inputs at 0
Thermal resistance
TQFP-48
θ
JA
θ
JC
97.5
20
°C/W
°C/W
(1)
At output I
Measured at f
, I
, while driving a 250Ω load, transition from 000h to FFFh.
= 25MSPS and f = 1.0MHz.
OUT1 OUT2
(2)
(3)
(4)
CLOCK OUT
Differential, transformer (n = 4:1) coupled output, R = 400Ω.
Differential outputs with a 250Ω load.
L
V
Nominal full−scale output current is IOUTFS + 32 IREF + 32 REF ; with VREF + 1.22V (typ) and R
Ensured by design and characterization; not production tested.
Gain error to remain ≤10% FSR over the full compliance range.
Combined power dissipation of I-DAC and V-DAC.
+ 19.6kW (1%)
(5)
SET
RSET
(6)
(7)
(8)
4
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS: V-DAC
At T = T
MIN
to T
MAX
(typical values are at T = 25°C), +V = +3V, +V
= +3V, R = 2kΩ to GND, and C = 40pF, unless otherwise noted.
DV L L
A
A
AV
DAC2932
TYP
MIN
MAX
PARAMETER
TEST CONDITIONS
UNITS
(1)
Static Performance
Resolution
12
8
Bits
LSB
Relative accuracy
Differential nonlinearity, DNL
(2)
Zero code error
At 25°C
−16
−1
+16
+1
Tested; monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
0.2
0.2
−3
5
LSB
+0.8
+2
%FSR
%FSR
µV/°C
ppmFSR/°C
(2)
Full-scale error
−10
Zero code error drift
Full-scale error drift
Output Characteristics
−15
(3)
Reference voltage setting, REFV
Output voltage settling time
0
+V
AV
V
µs
1/4 scale to 3/4 scale change (400h to C00h)
3
5
C
L
= 470pF
µs
Slew rate
1
V/µs
pF
Capacitive load stability
Code change glitch impulse
Digital feedthrough
DC output impedance
Short-circuit current
Power-up time
R
= 2kΩ
470
11
0.5
4
L
1LSB change around major carry
nV-s
nV-s
Ω
20
8
mA
µs
Coming out of power-down mode
(3)
Logic Inputs
Input current
1
0
µA
V
Input low voltage, V
IL
0.8
Input high voltage, V
2
3
V
IH
Input capacitance
5
pF
(1)
(2)
(3)
Linearity calculated using a reduced code range of 48 to 3976.
Full-scale range (FSR) based on reference REFV = +V = +3.0V.
AV
Ensured by design and characterization; not production tested.
5
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
TIMING INFORMATION
tCP
tCL
tCH
CLK
−
−
DAC1 (n 1)
DAC2 (n 1)
DAC1 (n)
tH1
DAC2 (n)
tH2
DAC1 (n +1)
DAC2 (n + 1)
Data In[D0:D11]
tS1
tS2
−
−
(n 2)
(n 1)
(n)
(n)
I−DAC OUT1
I−DAC OUT2
tDO1
−
−
(n 1)
(n 2)
tDO2
Figure 1. Timing Diagram of I-DAC
(1,2)
TIMING REQUIREMENTS
: I-DAC
PARAMETER
DESCRIPTION
MIN
TYP
MAX UNIT
t
t
t
t
t
t
t
t
t
Clock cycle time (period)
Clock low time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
CP
10
10
CL
Clock high time
CH
S1
Data setup time, I-DAC1
Data setup time, I-DAC2
Data hold time, I-DAC1
Data hold time, I-DAC2
Output delay time, I-DAC1
Output delay time, I-DAC2
CS hold time (pulse width)
0.5
0.5
2.2
2.2
5
5
5
5
S2
H1
H2
(3)
(3)
t
+ t
DO1
DO2
S1 CP
t
+(t
)
S2 CP/2
t
+ 3.5
CP
CS to clock rising or falling edge setup time
−1.5
17
STBY rise time to I
OUT
(I-DAC coming out of power-down mode)
PD fall time to I
OUT
22
(1)
(2)
(3)
Based on design simulation and characterization; not production tested.
All input signals are specified with t = t ≤ 2ns (10% to 90% of +V ) and timed from a voltage level of (V + V )/2.
r
f
DV IL IH
Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.
6
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
t1
SCLK
SYNC
t8
t2
t3
t7
t4
t6
t5
DIN
DB15
DB0
Figure 2. Serial Write Operation of V-DAC
: V-DAC
(1,2)
TIMING REQUIREMENTS
PARAMETER
DESCRIPTION
MIN
50
13
22.5
0
TYP
MAX
UNIT
ns
(3)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
SCLK cycle time
SCLK high time
SCLK low time
ns
ns
SYNC to SCLK rising edge setup time
Data setup time
ns
5
7.5
2.5
ns
Data hold time
1.5
0
ns
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
−6.0
ns
50
ns
PDV fall time to V
OUT
(V-DAC coming out of power-down mode)
8
µs
(1)
(2)
(3)
All input signals are specified with t = t ≤ 2ns (10% to 90% of +V ) and timed from a voltage level of (V + V )/2.
DV IL IH
r
f
Based on design simulation and characterization; not production tested.
Maximum SCLK frequency is 20MHz at +V = +V = +2.7V to 3.3V.
AV DV
V−DAC: SERIAL DATA INPUT FORMAT
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
D3
DB2
DB1
D1
DB0
A0
A1
A2
A3
D11
D10
D9
D8
D7
D6
D5
D4
D2
D0
DAC1 DAC2 DAC3 DAC4 (MSB)
(LSB)
Address Bits
12-Bit Data Word
NOTE: A logic high in the address bit will select the corresponding V-DAC and write the data word into its register. If more than one address bit
is set high, the selected V-DACs are updated with the same data word simultaneously.
7
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
PIN ASSIGNMENTS
48 47 46 45 44 43 42 41 40 39 38 37
Bit_1 (MSB)
Bit_2
1
2
3
4
5
6
7
8
9
36 NC
(V−DAC Section)
35 +VAV
34 IOUT2
33 IOUT2
Bit_3
Bit_4
Bit_5
32
31
30
29
28
AGND
AGND
+VA
Bit_6
DAC2932
Bit_7
+VA
Bit_8
Bit_9
AGND
Bit_10 10
Bit_11 11
27 IOUT1
26 IOUT1
25 REFIN
Bit_12 (LSB) 12
13 14 15 16 17 18 19 20 21 22 23 24
Terminal Functions
TERMINAL
NAME
D0:D11
DGND
NO.
1:12
13
I/O
DESCRIPTION
I
Parallel data input port for the dual I-DACs; MSB = D11, LSB = D0; interleaved operation.
Digital ground of I-DAC
+V
D
14
Digital supply of I-DAC; 2.7V to 3.3V
CLK
PD
15
I
I
I
Clock input of I-DAC
16
Power-down pin; active high; a logic high initiates power-down mode.
Standby pin of I-DAC; active low; a logic low initiates Standby mode with PD = Low.
STBY
17
A logic high configures the I-DAC for normal operation; pin will resume a high state if left open.
CS
18
19
I
I
Chip select; active low; enables the parallel data port of the I-DACs.
Pin will resume a low state if left open.
GSET
Gain-setting mode. A logic high enables the use of two separate full-scale adjust resistors on pins FSA1
and FSA2. A logic low allows the use of a common full-scale adjust resistor connected to FSA1. The
function of the FSA2 pin is disabled, and any remaining resistor has no effect. The value for the R
SET
resistor remains the same for a given full-scale range, regardless of the selected GSET mode. Pin will
resume a low state if left open.
DGND
AGND
AGND
FSA2
FSA1
20
21
22
23
24
25
Digital ground of I-DAC
Analog ground of I-DAC
Analog ground of I-DAC
I
I
I
Full-scale adjust of I-DAC2; connect external gain setting resistor R
Full-scale adjust of I-DAC1; connect external gain setting resistor R
= 19.6kΩ.
= 19.6kΩ.
SET2
SET1
REF
IN
External reference voltage input; internal reference voltage output; bypass with 0.1µF to AGND for internal
reference operation.
8
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
TERMINAL
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
Terminal Functions (continued)
NAME
NO.
I/O
DESCRIPTION
I
I
26
O
Complementarycurrent ouput of I-DAC1
Current output of I-DAC1
OUT1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
OUT1
AGND
+V
Analog ground of I-DAC
Analog supply of I-DAC; 2.7V to 3.3V
Analog supply of I-DAC; 2.7V to 3.3V
Analog ground of I-DAC
A
+V
A
AGND
AGND
Analog ground of I-DAC
I
I
O
O
Current output of I-DAC2
OUT2
Complementary current ouput of I-DAC2
Analog supply of V-DAC; 2.7V to 3.3V
No internal connection
OUT2
+V
AV
NC
V
V
V
V
O
O
O
O
Voltage output of V-DAC1
OUT1
OUT2
OUT3
OUT4
Voltage output of V-DAC2
Voltage output of V-DAC3
Voltage output of V-DAC4
AGNDV
REFV
Analog ground of V-DAC
I
Reference voltage input for V-DACs; typically connected to supply (+V )
AV
+V
DV
Digital supply of V-DAC; 2.7V to 3.3V
PDV
I
I
I
I
Power-down of V-DACs; active high; a logic high initiates the power-down mode
Serial digital input for V−DAC; see timing and application sections for details
Clock input of V-DAC
DIN
SCLK
SYNC
DGNDV
Frame synchronization signal for the serial data at DIN. Refer to timing section for details.
Digital ground of V-DAC.
9
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
T
R
= +25°C, +V = +V = +3V, +V = +V
= +3V, I
OUTFS
= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,
A
L
A
AV
D
DV
L
= 2kΩ on V-DAC, and GSET = H unless otherwise noted.
I−DAC, INL
I−DAC, DNL
2.0
1.0
1.6
1.2
0.8
0.4
0
0.8
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
0.4
0.8
1.2
1.6
2.0
0.2
0.4
0.6
0.8
1.0
0
500 1000 1500 2000 2500 3000 3500 4000
Codes
0
500 1000 1500 2000 2500 3000 3500 4000
Codes
Figure 3
Figure 4
SFDR vs fOUT AT 5MSPS
SFDR vs fOUT AT 10MSPS
80
78
76
74
72
70
68
66
64
62
60
80
75
70
65
60
55
50
0
0.5
1.0
1.5
2.0
2.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
fOUT (MHz)
fOUT (MHz)
Figure 5
Figure 6
SFDR vs fOUT AT 20MSPS
SFDR vs fOUT AT 40MSPS
80
75
70
65
60
55
50
80
75
70
65
60
55
50
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
14
16 18
20
fOUT (MHz)
fOUT (MHz)
Figure 7
Figure 8
10
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
T
R
= +25°C, +V = +V = +3V, +V = +V
= 2kΩ on V-DAC, and GSET = H unless otherwise noted.
= +3V, I
OUTFS
= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,
A
L
A
AV
D
DV
L
SFDR vs TEMPERATURE
80
SFDR vs IOUT FS AND fOUT AT 40MSPS, 0dBFS
80
1mA
75
75
70
2.2MHz, 40MSPS
70
1.5mA
0.5mA
2mA
1MHz, 20MSPS
65
65
60
55
50
10MHz, 40MSPS
60
55
19.9MHz, 40MSPS
50
−
−
−
−
40 30 20 10
0
10 20 30 40 50 60 70 80 85
0
2
4
6
8
10
12 14 16
18
20
_
Temperature ( C)
fOUT (MHz)
Figure 9
Figure 10
TOTAL HARMONIC DISTORTION vs
fCLK AT fOUT = 2.2MHZ
TOTAL HARMONIC DISTORTION vs TEMPERATURE
fOUT = 1MHz at 20MSPS
−
−
−
−
−
60
65
70
75
80
−
−
−
−
−
−
−
−
−
50
55
60
65
70
75
80
85
90
5
10
15
20
25
30
35
40
−
−
−
−
40 30 20 10
0
10 20 30 40 50 60 70 80 85
f
CLK (MSPS)
_
Temperature ( C)
Figure 11
Figure 12
REFERENCE VOLTAGE vs SUPPLY VOLTAGE
REFERENCE VOLTAGE vs TEMPERATURE
1.2201
1.2200
1.2199
1.223
1.222
1.221
1.220
1.219
1.218
1.217
1.216
1.215
2.7
2.8
2.9
3.0
3.1
3.2
3.3
−
−
20
40
0
20
40
60
80 85
Supply Voltage (V)
_
Temperature ( C)
Figure 13
Figure 14
11
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
T
R
= +25°C, +V = +V = +3V, +V = +V
= 2kΩ on V-DAC, and GSET = H unless otherwise noted.
= +3V, I
OUTFS
= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,
A
L
A
AV
D
DV
L
IA vs TEMPERATURE
5.60
ID vs TEMPERATURE AT fOUT AND fCLK
6.5
19.9MHz, 40MSPS
6.0
5.55
5.50
5.45
5.40
5.35
5.30
5.25
5.20
10MHz, 40MSPS
2.2MHz, 40MSPS
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1MHz, 20MSPS
−
−
20
40
0
20
40
60
80 85
−
−
20
40
0
20
40
60
80 85
_
Temperature ( C)
_
Temperature ( C)
Figure 15
Figure 16
IA vs SUPPLY VOLTAGE
ID vs SUPPLY VOLTAGE AT fOUT AND fCLK
5.43
5.42
5.41
5.40
5.39
5.38
5.37
5.36
5.35
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
19.9MHz, 40MSPS
10MHz, 40MSPS
2.2MHz, 40MSPS
1MHz, 20MSPS
2.7
2.8
2.9
3.0
3.1
3.2
3.3
2.7
2.8
2.9
3.0
3.1
3.2
3.3
Supply Voltage (V)
Supply Voltage (V)
Figure 17
Figure 18
I−DAC2 OUTPUT SPECTRUM
I−DAC1 OUTPUT SPECTRUM
0
0
fOUT = 2.2MHz
fCLK = 40MSPS
fOUT = 2.2MHz
fCLK = 40MSPS
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
10
20
30
40
50
60
70
80
90
−
−
100
100
0
2
4
6
8
10
12 14
16
18
20
0
2
4
6
8
10
12 14
16 18
20
Frequency (MHz)
Frequency (MHz)
Figure 19
Figure 20
12
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
T
R
= +25°C, +V = +V = +3V, +V = +V
= 2kΩ on V-DAC, and GSET = H unless otherwise noted.
= +3V, I
OUTFS
= 2mA, differential transformer-coupled output (n = 4:1), R = 400Ω on I-DAC,
A
L
A
AV
D
DV
L
DUAL−TONE OUTPUT SPECTRUM
FOUR−TONE OUTPUT SPECTRUM
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
f1 = 1.2MHz
f2 = 2.2MHz
f3 = 3.2MHz
f4 = 4.2MHz
fCLK = 40MSPS
f1 = 1.2MHz
f2 = 2.2MHz
fCLK = 40MSPS
−
100
110
−
100
−
−
110
0
2
4
6
8
10
12 14
16
18
20
0
2
4
6
8
10
12 14
16 18 20
Frequency (MHz)
Frequency (MHz)
Figure 21
Figure 22
I−DAC CHANNEL ISOLATION vs fOUT AT 40MSPS
V−DAC, INL
−
60
70
80
90
16
12
8
−
Channel 2
Channel 1
−
−
4
0
−
−
4
8
−
100
−
110
−
12
16
−
120
−
0
2
4
6
8
10
12 14
16
18
20
0
500 1000 1500 2000 2500 3000 3500 4000
Codes
Frequency (MHz)
Figure 23
Figure 24
V−DAC, DNL
VOUT vs CODE
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
1.0
0.8
0.6
0.4
0.2
0
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
0
500 1000 1500 2000 2500 3000 3500 4000
Codes
0
500 1000 1500 2000 2500 3000 3500 4000
Codes
Figure 25
Figure 26
13
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
The segmented architecture results in a significant
reduction of the glitch energy, and improves the dynamic
performance (SFDR) and DNL. The current outputs
maintain a very high output impedance of greater than
200kΩ.
The full-scale output current is determined by the ratio of
the internal reference voltage (approximately +1.2V) and
an external resistor, RSET. The resulting IREF is internally
multiplied by a factor of 32 to produce an effective DAC
output current that can range from 0.5mA to 2mA,
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC2932 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a
full-scale output current of up to 2mA, as shown in
Figure 27. An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
currents to either output summing node, IOUT or IOUT. The
complementary outputs deliver a differential output signal,
which improves the dynamic performance through
reduction of even-order harmonics and common-mode
signals (noise), and doubles the peak-to-peak output
signal swing by a factor of two, compared to single-ended
operation.
depending on the value of RSET
.
The DAC2932 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and
the decoder logic, while the analog section comprises the
current source array with its associated switches, and the
reference circuitry.
REFIN GSET
FSA1
FSA2
+VA
AGND
+VD
DGND
STBY
CS
DAC2932
+1.22V Reference
Reference Control Amp
PD
IOUT1
IOUT1
12−Bit
40MSPS
I−DAC1
Data1
CLK1
Clock
DAC
Latch 1
CLK
Parallel Data Input,
[D0:D11]
12−Bit Data,
Interleaved
IOUT2
IOUT2
12−Bit
40MSPS
I−DAC2
Data2
CLK2
DAC
Latch 2
I−DAC Section
V−DAC Section
A
12
A0
Dx
12−Bit
String−DAC1
VOUT1
VOUT2
VOUT3
VOUT4
Latch
Latch
Latch
Latch
DIN
12−Bit
String−DAC2
A
A1
A2
A3
SCLK
SYNC
12−Bit
String−DAC3
A
A
12−Bit
String−DAC4
REFV
PDV +VDV DGNDV +VAV AGNDV
Figure 27. Block Diagram of the DAC2932
14
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
The two single-ended output voltages can be combined to
find the total differential output swing:
DAC TRANSFER FUNCTION
Each of the I-DACs in the DAC2932 has a complementary
current output, IOUT1 and IOUT2. The full-scale output
VOUTDIFF + VOUT * VOUT
current, IOUTFS
,
is the summation of the two
(7)
(2 Code * 4095)
complementary output currents:
+
IOUTFS RLOAD
4096
IOUTFS + IOUT ) IOUT
The individual output currents depend on the DAC code
and can be expressed as:
(1)
POWER-DOWN MODES
The DAC2932 has several modes of operation. Besides
normal operation, the I-DAC section features a Standby
mode and a full power-down mode, while the V-DAC
section has one power-down mode. All modes are
controlled by appropriate logic levels on the assigned pins
of the DAC2932. Table 1 lists all pins and possible modes.
The pins have internal pull-ups or pull-downs; if left open,
all pins will resume logic levels that place the I-DAC and
V-DAC in a normal operating mode (fully functional).
IOUT + IOUTFS (Codeń4096)
(2)
IOUT + IOUTFS (4095 * Code)ń4096
(3)
where Code is the decimal representation of the DAC data
input word (0 to 4095).
Additionally, IOUTFS is a function of the reference current
I
REF, which is determined by the reference voltage and the
external setting resistor, RSET
.
When in Standby mode the analog functions of the I-DAC
section are powered down. The internal logic is still active
and will consume some power if the clock remains applied.
To further reduce the power in Standby mode the CS pin
may be pulled high, which disables the internal logic from
being clocked, even with the clock signal applied.
VREF
RSET
(4)
IOUTFS + 32 IREF + 32
In most cases, the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
If CS remains low during the Standby mode and a running
clock remains applied, any new data on the parallel data
port will be latched into the DAC. The analog output,
however, will not be updated as long as the I-DACs remain
in Standby mode.
VOUT + IOUT RLOAD
VOUT + IOUT RLOAD
(5)
(6)
The value of the load resistance is limited by the output
compliance specification of the DAC2932. To maintain
optimum linearity performance, the compliance voltage at
I
OUT and IOUT should be limited to +0.5V or less.
Table 1. Power-Down Modes
PD (16) STBY(17) CS (18) PDV (44)
DAC
MODE
DAC OUTPUTS
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
I-DAC enabled
I-DAC disabled
I-DAC enabled
I-DAC disabled
Standby; data can still be written into the DACs
with running clock applied
High-Z
Standby; writing into DAC disabled—clock input
disabled by CS
High-Z
Normal operation (return from Standby)
Last state prior to
Standby
Data input and clock input disabled; use when
multiple devices on one bus
Last data held
1
X
X
X
X
X
X
X
X
X
0
1
I-DAC disabled
V-DAC enabled
Full power-down; STBY and CS have no effect
V-DAC normal operation
High-Z
V-DAC disabled V-DAC in power-down mode; independent
operation of any I-DAC power-down
configuration
All outputs; High-Z
NOTE: X = don’t care.
15
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
0.5mA may be considered for applications that require low
power consumption, but can tolerate a slightly reduced
performance level.
ANALOG OUTPUTS
The DAC2932 provides two sets of complementary
current outputs, IOUT and IOUT. The simplified circuit of the
analog output stage representing the differential topology
is shown in Figure 28. The output impedance of IOUT and
The current-output DACs of the DAC2932 have a straight
offset binary coding format. With all bits high, the full-scale
output current (for example, 2mA) will be sourced at pins
I
OUT results from the parallel combination of the differential
I
OUT1 and IOUT2, as shown in Table 2.
switches, along with the current sources and associated
parasitic capacitances.
Table 2. Input Coding vs Analog Output Current
+VA
INPUT CODE
(D11−D0)
I
I
OUT
(mA)
OUT
DAC2932
(mA)
1111 1111 1111
1000 0000 0000
0000 0000 0000
2
1
0
0
1
2
OUTPUT CONFIGURATIONS
As mentioned previously, utilizing the differential outputs
of the converter yields the best dynamic performance.
Such a differential output circuit may consist of an RF
transformer or a differential amplifier configuration. The
transformer configuration is ideal for most applications
with ac coupling, while op amps are suitable for a
dc-coupled configuration.
IOUT
RL
IOUT
RL
Figure 28. Equivalent Analog Output
The signal voltage swing that develops at the two outputs,
IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –0.5V is given by the
breakdown voltage of the CMOS process, and exceeding
it will compromise the reliability of the DAC2932, or even
cause permanent damage. With the full-scale output set to
2mA, the positive compliance equals 0.8V, operating with
an analog supply of +VA = 3V. To avoid degradation of the
distortion performance and integral linearity, care must be
taken so that the configuration of the DAC2932 does not
exceed the compliance range.
The single-ended configuration may be considered for ap-
plications requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground converts the
output current into a ground-referenced voltage signal. To im-
prove on the dc linearity by maintaining a virtual ground, an
I-to-V or op-amp configuration may be considered.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance
(see Figure 3). The appropriate transformer should be
carefully selected based on the output frequency spectrum
and impedance requirements. The differential transformer
configuration has the benefit of significantly reducing
common-mode signals, thus improving the dynamic
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5VPP. This is the case for a 250Ω load and a 2mA
full-scale output current. A variety of loads can be adapted
to the output of the DAC2932 by selecting a suitable
transformer while maintaining optimum voltage levels at
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer is
performance over
a
wide range of frequencies.
Furthermore, by selecting a suitable impedance ratio
(winding ratio), the transformer can be used to provide
optimum impedance matching while controlling the
compliance voltage for the converter outputs. The model
shown, ADT16-6T (by Mini-Circuits), has a 4:1 ratio and
may be used to interface the DAC2932 to a 50Ω load. This
results in a 400Ω load for each of the outputs, IOUT and
IOUT. The output signals are ac coupled and inherently
isolated by the transformer.
instrumental
in
achieving
excellent
distortion
performance. Common-mode errors, such as even-order
harmonics or noise, can be substantially reduced. This is
particularly the case with high output frequencies.
For those applications requiring the optimum distortion
and noise performance, it is recommended to select a
full-scale output of 2mA. A lower full-scale range down to
16
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
As shown in Figure 29, the transformer center tap is
connected to ground. This forces the voltage swing on
IOUT and IOUT to be centered at 0V. In this case the two
resistors, RL, may be replaced with one, RDIFF, or omitted
altogether. Alternatively, if the center tap is not connected,
the signal swing will be centered at RL × IOUTFS/2.
However, in this case, the two resistors (RL) must be used
to enable the necessary dc-current flow for both outputs.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer
solution because the amplifier introduces another source
of distortion. Suitable amplifiers should be selected based
on their slew-rate, harmonic distortion, and output swing
capabilities. A high-speed amplifier like the OPA690 may
be considered. The ac performance of this circuit can be
improved by adding a small capacitor (CDIFF) between the
outputs IOUT and IOUT, as shown in Figure 30. This will
introduce a real pole to create a low-pass filter in order to
slew-limit the fast output signal steps of the DAC, which
otherwise could drive the amplifier into slew-limitations or
into an overload condition; both would cause excessive
distortion. The difference amplifier can easily be modified
to add a level shift for applications requiring the
single-ended output voltage to be unipolar (that is, swing
between 0V and +2V).
RF
Transformer
IOUT
RL
Ω
250
DAC2932
RDIFF
RS
IOUT
RL
Ω
250
DUAL TRANSIMPEDANCE OUTPUT
CONFIGURATION
Figure 29. Differential Output Configuration
Using an RF Transformer
The circuit example of Figure 31 shows the signal output
currents connected into the summing junctions of the
OPA2690 dual voltage-feedback op amp, which is set up as
a transimpedance stage or I-to-V converter. With this circuit,
the DAC output will be kept at a virtual ground, minimizing the
effects of output impedance variations, which results in the
best dc linearity (INL). As mentioned previously, care should
be taken not to drive the amplifier into slew-rate limitations
and produce unwanted distortion.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a dc−coupled output, a difference
amplifier may be considered, as shown in Figure 30. Four
external resistors are needed to configure the OPA690
voltage-feedback op amp as a difference amplifier
performing the differential to single-ended conversion. Under
the configuration shown, the DAC2932 generates a
differential output signal of 0.5VPP at the load resistors, RL.
+5V
Ω
50
R2
1/2
−
•
VOUT = IOUT RF1
Ω
499
OPA2690
R1
Ω
249
RF1
CF1
DAC2932
IOUT
VOUT
DAC2932
OPA690
IOUT
IOUT
CD1
R3
COPT
Ω
249
−
5V +5V
RF2
CF2
RL
RL
R4
Ω
499
Ω
249
Ω
249
CD2
IOUT
1/2
Figure 30. Difference Amplifier Provides
Differential-to-Single-Ended Conversion and
DC-Coupling
−
•
VOUT = IOUT RF2
OPA2690
Ω
50
The OPA690 is configured for a gain of two. Therefore,
operating the DAC2932 with a 2mA full-scale output
produces a voltage output of 1V. This requires the
amplifier to operate from a dual power supply ( 5V). The
tolerance of the resistors typically sets the limit for the
achievable common-mode rejection. An improvement can
be obtained by fine tuning resistor R4.
−
5V
Figure 31. The OPA2690 Dual, Voltage-Feedback
Amplifier Forms a Transimpedance Amplifier
17
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2
)
produces a zero in the noise gain for the OPA2690 that can
cause peaking in the closed-loop frequency response. CF is
added across RF to compensate for this noise gain peaking.
To achieve a flat transimpedance frequency response, the
pole in each feedback network should be set to:
IOUTFS = 2mA
IOUT
VOUT = 0V to +0.5V
DAC2932
Ω
250
IOUT
Ω
250
Ǹ
GBP
4pRFCF
1
(8)
+
2pRFCF
where GBP = gain bandwidth product of the op amp, which
gives a corner frequency f−3dB of approximately:
Figure 32. Differential Output Configuration
Using an RF Transformer
Ǹ
GBP
2pRFCD
f
+
*3dB
(9)
Different load resistor values may be selected, as long as
the output compliance range is not exceeded. Additionally,
the output current (IOUTFS) and the load resistor can be
mutually adjusted to provide the desired output signal
swing and performance.
The full-scale output voltage is simply defined by the
product of IOUTFS • RF, and has a negative unipolar
excursion. To improve on the ac performance of this circuit,
adjustment of RF and/or IOUTFS should be considered.
Further extensions of this application example may
include adding a differential filter at the OPA2690 output
followed by a transformer, in order to convert to a
single-ended signal.
INTERFACING ANALOG QUADRATURE
MODULATORS
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital
communications. In this application, the DAC is followed
by an analog quadrature modulator, modulating an IF
carrier with the baseband data, as shown in Figure 33.
Often, the input stages of these quadrate modulators
consist of npn-type transistors that require a dc bias (base)
voltage of > 0.8V.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the DAC
outputs, a simple current-to-voltage conversion can be
accomplished. The circuit in Figure 32 shows a 250Ω
resistor connected to IOUT. Therefore, with a nominal
output current of 2mA, the DAC produces a total signal
swing of 0V to 0.5V.
VOUT ~ 0VP to 0.5VP
VIN ~ 0.6VP to 1.8VP
IIN
IREF
IIN
DAC2932
IOUT
1
IREF
I
OUT1
Signal
Conditioning
∑
RF
QIN
IOUT
2
2
QREF
IOUT
Quadrature Modulator
Figure 33. Generic Interface to a Quadrature Modulator. Signal conditioning (level shifting) may be
required to ensure correct dc common-mode levels at the input of the quadrature modulator.
18
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
Figure 34 shows an example of a dc-coupled interface
with dc level-shifting, using a precision resistor network.
An ac-coupled interface, as shown in Figure 35, has the
advantage in that the common-mode levels at the input of
the modulator can be set independently of those at the
output of the DAC. Furthermore, no voltage loss occurs in
this setup.
The external resistor RSET connects to the FSA pin
(full-scale adjust) as shown in Figure 36. The reference
control amplifier operates as a V-to-I converter producing
a reference current, IREF, which is determined by the ratio
of VREF and RSET, as shown in Equation 10. The full-scale
output current, IOUTFS, results from multiplying IREF by a
fixed factor of 32.
VDC
+3V
R3
+VA
DAC2932
VOUT
VOUT
1
1
VREF
IREF
=
RSET
FSA
Ref
Control
Amp
Current
Sources
R4
IOUT
1
REFIN
DAC2932
RSET
19.6k
IOUT
1
Ω
µ
0.1 F
IOUT
1
I
OUT1
+1.22V Ref.
R5
Figure 34. DC-Coupled Interface to a Quadrature
Modulator Applying Level Shifting
Figure 36. Internal Reference Configuration
Using the internal reference, a 19.6kΩ resistor value
results in a full-scale output of approximately 2mA.
Resistors with a tolerance of 1% or better should be
considered. Selecting higher values, the output current
can be adjusted from 2mA down to 0.5mA. Operating the
DAC2932 at lower than 2mA output currents may be
desirable for reasons of reducing the total power
consumption or observing the output compliance voltage
limitations for a given load condition.
VDC
R1
IOUT1
DAC2932
IOUT
µ
0.01 F
1
VOUT
1
1
VOUT
IOUT
1
µ
0.01 F
It is recommended to bypass the REFIN pin with a ceramic
chip capacitor of 0.1µF or more. The control amplifier is
internally compensated, and its small signal bandwidth is
approximately 0.1MHz.
IOUT1
RLOAD
RLOAD
Ω
250
R2
Ω
250
GAIN SETTING OPTIONS
Figure 35. AC-Coupled Interface to a Quadrature
Modulator Applying Level Shifting
The full-scale output current on the DAC2932 can be set
two ways: either for each of the two DAC channels
independently or for both channels simultaneously. For the
independent gain set mode, GSET (pin 19) must be high
(that is, connected to +VA). In this mode, two external
resistors are required—one RSET connected to the FSA1
pin (pin 24) and the other to the FSA2 pin (pin 23). In this
configuration, the user has the flexibility to set and adjust
the full-scale output current for each DAC independently,
allowing for the compensation of possible gain
mismatches elsewhere within the transmit signal path.
INTERNAL REFERENCE OPERATION
The DAC2932 has an on-chip reference circuit that
comprises a 1.22V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current,
OUTFS, of the DAC2932 is determined by the reference
voltage, VREF, and the value of resistor RSET. IOUTFS can
be calculated by:
I
VREF
RSET
(10)
IOUTFS + 32 IREF + 32
19
ꢀꢒ ꢕ ꢆ ꢙꢚ ꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
Alternatively, bringing GSET low (that is, connected to
AGND), switches the DAC2932 into the simultaneous gain
set mode. Now the full-scale output current of both DAC
channels is determined by only one external RSET resistor
connected to the FSA1 pin. The resistor at the FSA2 pin
may be removed; however, this is not required since this
pin is not functional in this mode and the resistor has no
effect on the gain equation. The formula for deriving the
correct RSET remains unchanged. For example,
V−DAC
The architecture consists of a resistor string DAC followed
by an output buffer amplifier. Figure 38 shows a block
diagram of the DAC architecture.
REFV
(+VDV
)
R
SET = 19.6kΩ will result in a 2mA output for both DACs.
REF (+)
Resistor
String
The DAC2932 is specified with GSET being high and
operating in inpendent gain mode. It should be noted that
when using the simultaneous gain mode, the gain error
and gain matching error will increase.
VOUT
DAC Register
−
REF( )
Output
Amplifier
GND
EXTERNAL REFERENCE OPERATION
Figure 38. V-DAC Architecture
The internal reference can be disabled by simply applying
an external reference voltage into the REFIN pin, which in
this case functions as an input, as shown in Figure 37. The
use of an external reference may be considered for
applications that require higher accuracy and drift
performance.
The input coding to the V-DAC is straight binary, so the
ideal output voltage is given by:
D
4096
VOUT + REFV
(11)
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
+3V
SERIAL INTERFACE
+VA
DAC2932
The V−DACs have a three-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI, and
Microwire interface standards as well as most Digital
Signal Processors (DSPs).
VREF
RSET
IREF
=
FSA
Ref
Control
Amp
Current
Sources
REFIN
External
Reference
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift
register on the falling edge of SCLK. The serial clock
frequency can be as high as 20MHz, making the V-DACs
compatible with high-speed DSPs. On the 16th falling
edge of the serial clock, the last data bit is clocked in and
the programmed function is executed (that is, a change in
DAC register contents and/or a change in the mode of
operation).
RSET
+1.22V Ref.
At this point, the SYNC line may be kept low or brought
high. In either case, it must be brought high for a minimum
of 50ns before the next write sequence so that a falling
edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when the SYNC
signal is high than it does when it is low, SYNC should be
idled low between write sequences for lowest power
operation of the part. As mentioned above, however, it
must be brought high again just before the next write
sequence.
Figure 37. External Reference Configuration
While a 0.1µF capacitor is recommended for use with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance and can easily be driven by various sources.
20
ꢀ ꢒꢕ ꢆꢙ ꢚꢆ
www.ti.com
SBAS279C − AUGUST 2003 − REVISED OCTOBER 2004
each supply pin are adequate to provide a low impedance
decoupling path. Keep in mind that their effectiveness
largely depends on the proximity to the individual supply
and ground pins. Therefore, they should be located as
close as physically possible to those device leads.
Whenever possible, the capacitors should be located
immediately under each pair of supply/ground pins on the
reverse side of the PCB. This layout approach minimizes
the parasitic inductance of component leads and PCB
runs.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. The first four bits are
the address bits to the four V-DACs. The next 12 bits are
the data bits. These are transferred to the DAC register on
the 16th falling edge of the clock (SCLK).
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
at least 16 falling edges of SCLK and the DAC is updated
on the 16th falling edge. However, if SYNC is brought high
before the 16th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents nor a change in the operating mode
occurs, as shown in Figure 39.
Further supply decoupling with surface-mount tantalum
capacitors (1µF to 4.7µF) can be added as needed in
proximity of the converter.
Low noise is required for all supply and ground
connections to the DAC2932. It is recommended to use a
multilayer PCB with separate power and ground planes.
Mixed signal designs require particular attention to the
routing of the different supply currents and signal traces.
Generally, analog supply and ground planes should only
extend into analog signal areas, such as the DAC output
signal and the reference signal. Digital supply and ground
planes must be confined to areas covering digital circuitry,
including the digital input lines connecting to the converter,
as well as the clock signal. The analog and digital ground
planes should be joined together at one point underneath
the DAC. This can be realized with a short track of
approximately 1/8” (3mm).
POWER-ON RESET
The V-DACs contain a power-on reset circuit that controls
the output voltage during power-up. On power-up, the
DAC register is filled with zeros and the output voltage is
0V; it remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is important
to know the state of the output of the DAC while it is in the
process of powering up.
GROUNDING, DECOUPLING, AND LAYOUT
INFORMATION
The power to the DAC2932 should be provided through
the use of wide PCB runs or planes. Wide runs present a
lower trace impedance, further optimizing the supply
decoupling. The analog and digital supplies for the
converter should only be connected together at the supply
connector of the PCB. In the case of only one supply
voltage being available to power the DAC, ferrite beads
along with bypass capacitors can be used to create an LC
filter. This will generate a low-noise analog supply voltage
that can then be connected to the +VA supply pin of the
DAC2932.
Proper grounding and bypassing, short lead length, and
the use of ground planes are particularly important for
high-frequency designs. Multilayer printed circuit boards
(PCBs) are recommended for best performance since they
offer distinct advantages such as minimization of ground
impedance, separation of signal layers by ground layers,
etc.
The DAC2932 uses separate pins for its analog and digital
supply and ground connections. The placement of the
decoupling capacitor should be such that the analog
supply (+VA) is bypassed to the analog ground (AGND),
and the digital supply bypassed to the digital ground
(DGND). In most cases, 0.1µF ceramic chip capacitors at
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
CLK
SYNC
DIN
DB15
DB0
DB15
DB0
Invalid Write Sequence:
SYNC high before 16th falling edge
Valid Write Sequence:
Output updates on the 16th falling edge
Figure 39. SYNC Interrupt Facility
21
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
TQFP
Drawing
DAC2932PFBR
DAC2932PFBT
DAC2932PFBTG4
ACTIVE
ACTIVE
ACTIVE
PFB
48
48
48
2000
250
TBD
TBD
CU NIPDAU Level-2-240C-1 YEAR
CU NIPDAU Level-2-240C-1 YEAR
PFB
PFB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
DAC312BIHR
IC PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, CDIP20, HERMETIC SEALED, CERDIP-20, Digital to Analog Converter
ADI
DAC312BIHS
IC PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, PDSO20, SOL-20, Digital to Analog Converter
ADI
©2020 ICPDF网 联系我们和版权申明