DAC7541AJP_技术文档

®

DAC7541A

Low Cost 12-Bit CMOS

Four-Quadrant Multiplying

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

● FULL FOUR-QUADRANT

The Burr-Brown DAC7541A is a low cost 12-bit,

four-quadrant multiplying digital-to-analog converter.

Laser-trimmed thin-film resistors on a monolithic

CMOS circuit provide true 12-bit integral and differ-

ential linearity over the full specified temperature

range.

MULTIPLICATION

● 12-BIT END-POINT LINEARITY

● DIFFERENTIAL LINEARITY ±1/2LSB MAX

OVER TEMPERATURE

● MONOTONICITY GUARANTEED OVER

DAC7541A is a direct, improved pin-for-pin replace-

ment for 7521, 7541, and 7541A industry standard

parts. In addition to a standard 18-pin plastic package,

the DAC7541A is also available in a surface-mount

plastic 18-pin SOIC.

TEMPERATURE

● TTL-/CMOS-COMPATIBLE

● SINGLE +5V TO +15V SUPPLY

● LATCH-UP RESISTANT

● 7521/7541/7541A REPLACEMENT

● PACKAGES: Plastic DIP, Plastic SOIC

● LOW COST

V_REF

10kΩ

20kΩ

SPDT NMOS

Switches

I_{OUT 2}

I_{OUT 1}

10kΩ

Bit 1

(MSB)

Bit 2

Bit 3

Bit 11

Bit 12

(LSB)

R_FB

Digital Inputs (DTL-/TTL-/CMOS-compatible)

Logic: A switch is closed to I_{OUT 1}for its digital input in a “HIGH” state.

Switches shown for digital inputs “HIGH”.

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (520) 746-1111 Twx: 910-952-1111

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-639C

Printed in U.S.A. September, 1993

SBAS147

SPECIFICATIONS

ELECTRICAL

At +25°C, +V_DD= +12V or +15V, V_REF= +10V, V_{PIN 1}= V_{PIN 2}= 0V, unless otherwise specified.

DAC7541A

(1)

PARAMETER

GRADE

T_A= +25°C T_A= T_MAX, T_MIN

UNITS

TEST CONDITIONS/COMMENTS

ACCURACY

Resolution

Relative Accuracy

All

J

K

J

K

J

K

12

±1

±1/2

±1

±1/2

±6

±1

12

±1

±1/2

±1

±1/2

±8

±3

Bits

LSB max

±1LSB = ±0.024% of FSR.

±1/2LSB = ±0.012% of FSR.

All grades guaranteed monotonic to 12 bits,

T_MINto T_MAX.

Measured using internal R_FBand includes effect

of leakage current and gain T.C.

Gain error can be trimmed to zero.

Differential Non-linearity

Gain Error

Gain Temperature Coefficient

(∆Gain/∆Temperature)

Output Leakage Current: Out₁(Pin 1)

Out₂(Pin 2)

ALL

J, K

5

±10

ppm/°C max

nA max

Typical value is 2ppm/°C.

All digital inputs = 0V.

All digital inputs = V_DD.

±5

REFERENCE INPUT

Voltage (Pin 17 to GND)

Input Resistance (Pin 17 to GND)

All

–10/+10

7-18

–10/+10

7-18

V min/max

kΩ min/max

Typical input resistance = 11kΩ.

Typical input resistance temperature coefficient is

–50ppm/°C.

DIGITAL INPUTS

V

_IN(Input HIGH Voltage)

_IL(Input LOW Voltage)

All

2.4

0.8

±1

2.4

0.8

±1

V min

V max

µA max

I

_IN(Input Current)

Logic inputs are MOS gates.

I

_INtyp (25°C) = 1nA

C

_IN(Input Capacitance)⁽²⁾

All

8

pF max

V_IN= 0V

POWER SUPPLY REJECTION

∆Gain/∆V_DD

±0.01

±0.02

% per % max

V_DD= +11.4V to +16V

POWER SUPPLY

V_DDRange

+5 to +16

V min to

V max

Accuracy is not guaranteed over this range.

I_DD

All

2

100

2

500

mA max

µA max

All digital inputs V_ILor V_IN

All digital inputs 0V or V_DD.

.

NOTES: (1) Temperature ranges are: = 0°C to + 70°C for JP, KP, JU and KU versions. (2) Guaranteed by design but not production tested.

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance only and are not production tested.

V_DD= +15V, V_REF= +10V except where stated, V_{PIN 1}= V_{PIN 2}= 0V, output amp is OPA606 except where stated.

DAC7541A

(1)

PARAMETER

GRADE

T_A= +25°C T_A= T_MAX, T_MIN

UNITS

TEST CONDITIONS/COMMENTS

PROPAGATION DELAY

(from Digital Input change to 90% of

final Analog Output)

Out₁Load = 100Ω, C_EXT= 13pF.

Digital Inputs = 0V to V_DDor V_DDto 0V.

All

100

—

ns typ

DIGITAL-TO-ANALOG GLITCH

IMPULSE

V_REF= 0V, all digital inputs 0V to V_DDor V_DDto

0V. Measured using OPA606 as output amplifier.

1000

nV-s typ

MULTIPLYING FEEDTHROUGH

ERROR

(V_REFto Out₁)

All

1.0

—

mVp-p max

V_REF= ±10V, 10kHz sine wave.

OUTPUT CURRENT SETTLING TIME

All

0.6

1.0

—

µs typ

To 0.01% of Full Scale Range.

Out₁Load = 100Ω, C_EXT= 13pF.

Digital Inputs: 0V to V_DDor V_DDto 0V.

µs max

OUTPUT CAPACITANCE

C_{OUT 1}(Pin 1)

C_{OUT 2}(Pin 2)

C_{OUT 1}(Pin 1)

C_{OUT 2}(Pin 2)

All

100

60

70

100

60

70

pF max

Digital Inputs = V_IH

Digital Inputs = V_IL

100

NOTE: (1) Temperature ranges are: = 0°C to + 70°C for JP, KP, JU and KU versions.

®

2

DAC7541A

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONNECTIONS

V_DD(Pin 16) to Ground ...................................................................... +17V

Top View

DIP/SOIC

V_REF(Pin 17) to Ground ..................................................................... +25V

V_RPB(Pin 18) to Ground ..................................................................... ±25V

Digital Input Voltage (pins 4-15) to Ground ...............................–0.4V, V_DD

V_{PIN 1}, V_{PIN 2}to Ground ............................................................. –0.4V, V_DD

Power Dissipation (any Package):

To +75°C ..................................................................................... 450mW

Derates above +75°C .............................................................. –6mW/°C

Lead Temperature (soldering, 10s)................................................ +300°C

Storage Temperature: Plastic Package ......................................... +125°C

1

2

3

4

5

6

7

8

9

18 R_FB

I_{OUT 1}

I_{OUT 2}

17 V_REF

16 +V_DD

15 Bit 12 (LSB)

14 Bit 11

13 Bit 10

12 Bit 9

GND

Bit 1 (MSB)

Bit 2

DAC7541A

NOTE: (1) Stresses above those listed above may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at

these or any other condition above those indicated in the operational sections of

thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditions

for extended periods may affect device reliability.

Bit 3

Bit 4

Bit 5

11 Bit 8

Bit 6

10 Bit 7

ELECTROSTATIC

DISCHARGE SENSITIVITY

PACKAGE INFORMATION

PACKAGE DRAWING

NUMBER⁽¹⁾

The DAC7541A is an ESD (electrostatic discharge) sensi-

tive device. The digital control inputs have a special FET

structure, which turns on when the input exceeds the supply

by 18V, to minimize ESD damage. However, permanent

damage may occur on unconnected devices subject to high

energy electrostatic fields. When not in use, devices must be

stored in conductive foam or shunts. The protective foam

should be discharged to the destination socket before

devices are removed.

MODEL

PACKAGE

DAC7541JP

DAC7541KP

Plastic DIP

218

DAC7541JU

DAC7541KU

Plastic SOIC

219

DAC7541JP-BI

DAC7541KP-BI

Plastic DIP

218

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

BURN-IN SCREENING

Burn-in screening is an option available for the models in the

Ordering Information table. Burn-in duration is 160 hours at

the indicated temperature (or equivalent combination of time

and temperature).

All units are tested after burn-in to ensure that grade speci-

fications are met. To order burn-in, add “-BI” to the base

model number.

ORDERING INFORMATION

TEMPERATURE

RELATIVE

MODEL

PACKAGE

RANGE

ACCURACY (LSB)

GAIN ERROR (LSB)

DAC7541AJP

DAC7541AKP

DAC7541AJU

DAC7541AKU

Plastic DIP

Plastic SOIC

0°C to +70°C

±1

±1/2

±1

±6

±1

±6

±1

±1/2

BURN-IN SCREENING OPTION

See text for details.

TEMPERATURE

RANGE

RELATIVE

ACCURACY (LSB)

BURN-IN TEMP.

(160 Hours)⁽¹⁾

MODEL

PACKAGE

DAC7541AJP-BI

DAC7541AKP-BI

Plastic DIP

0°C to +70°C

±1

±1/2

+85°C

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

3

DAC7541A

PAD

FUNCTION

PAD

FUNCTION

1

2

3

4

5

6

7

8

9

I_OUT1

I_OUT2

GND

Bit 1 (MSB)

Bit 2

10

11

12

13

14

15

16

17

18

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12 (LSB)

+V_DD

V_REF

R_FEEDBACK

Bit 3

Bit 4

Bit 5

Bit 6

Substrate Bias: Isolated.

NC: No Connection.

MECHANICAL INFORMATION

MILS (0.001")

MILLIMETERS

Die Size

Die Thickness

Min. Pad Size

104 x 105 ±5

20 ±3

2.64 x 2.67 ±0.13

0.51 ±0.08

0.10 x 0.10

4 x 4

Metalization

Aluminum

DIE TOPOLOGY DAC7541A

TYPICAL PERFORMANCE CURVES

T_A= +25°C, V_DD= +15V, unless otherwise noted.

GAIN ERROR vs SUPPLY VOLTAGE

3

FEEDTHROUGH ERROR vs FREQUENCY

10

1

5/2

2

3/2

1

0.10

0.010

0.001

1/2

0

5

10

15

100

1k

10k

100k

1M

Supply Voltage (V)

Frequency (Hz)

LINEARITY vs SUPPLY VOLTAGE

SUPPLY CURRENT vs SUPPLY VOLTAGE

3/2

5/4

1

3/2

5/4

1

3/4

1/2

3/4

1/2

V_IH= +2.4V

1/4

0

1/4

0

V_IH= V_DD

0

5

10

15

0

5

10

15

Supply Voltage (V)

®

4

DAC7541A

DISCUSSION

OF SPECIFICATIONS

CIRCUIT DESCRIPTION

The DAC7541A is a 12-bit multiplying D/A converter

consisting of a highly stable thin-film R-2R ladder network

and 12 pairs of current steering switches on a monolithic

chip. Most applications require the addition of a voltage or

current reference and an output operational amplifier.

RELATIVE ACCURACY

This term (also known as linearity) describes the transfer

function of analog output to digital input code. The linearity

error describes the deviation from a straight line between

zero and full scale.

A simplified circuit of the DAC7541A is shown in Figure 1.

The R-2R inverted ladder binarily divides the input currents

that are switched between I_{OUT 1}and I_{OUT 2}bus lines. This

switching allows a constant current to be maintained in each

ladder leg independent of the input code.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB

change in the output, from one adjacent output state to the

next. A differential nonlinearity specification of ±1.0LSB

guarantees monotonicity.

The input resistance at V_REF(Figure 1) is always equal to

R_LDR(R_LDRis the R/2R ladder characteristic resistance and

is equal to value “R”). Since R_INat the V_REFpin is constant,

the reference terminal can be driven by a reference voltage

or a reference current, AC or DC, of positive or negative

polarity.

GAIN ERROR

Gain error is the difference in measure of full-scale output

versus the ideal DAC output. The ideal output for the

DAC7541A is –(4095/4096) X (V_REF). Gain error may be

adjusted to zero using external trims.

V_REF

10kΩ

OUTPUT LEAKAGE CURRENT

The measure of current which appears at Out₁with the DAC

loaded with all zeros, or at Out₂with the DAC loaded with

all ones.

20kΩ

S₁

20kΩ

S₂

20kΩ

S₃

20kΩ

S₁₂

20kΩ

I_{OUT 2}

I_{OUT 1}

R_FB

MULTIPLYING FEEDTHROUGH ERROR

This is the AC error output due to capacitive feedthrough

from V_REFto Out₁with the DAC loaded with all zeros. This

test is performed at 10kHz.

Bit 1

(MSB)

Bit 2

Bit 3

Bit 12

(LSB)

Digital Inputs (DTL-/TTL-/CMOS-compatible)

Switches shown for digital inputs “HIGH”.

OUTPUT CURRENT SETTLING TIME

This is the time required for the output to settle to a tolerance

of ±0.5LSB of final value from a change in code of all zeros

to all ones, or all ones to all zeros.

FIGURE 1. Simplified DAC Circuit.

EQUIVALENT CIRCUIT ANALYSIS

Figures 2 and 3 show the equivalent circuits for all digital

inputs low and high, respectively. The reference current is

switched to I_{OUT 2}when all inputs are low and I_{OUT 1}when

inputs are high. The I_Lcurrent source is the combination of

surface and junction leakages to the substrate; the

1/4096 current source represents the constant one-bit current

drain through the ladder terminal.

PROPAGATION DELAY

This is the measure of the delay of the internal circuitry and

is measured as the time from a digital code change to the

point at which the output reaches 90% of final value.

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the measure of the area of the glitch energy measured

in nV-seconds. Key contributions to glitch energy are digital

word-bit timing differences, internal circuitry timing differ-

ences, and charge injected from digital logic.

DYNAMIC PERFORMANCE

Output Impedance

The output resistance, as in the case of the output capaci-

tance, is also modulated by the digital input code. The

resistance looking back into the I_{OUT 1}terminal may be

anywhere between 10kΩ (the feedback resistor alone when

all digital inputs are low) and 7.5kΩ (the feedback resistor

in parallel with approximately 30kΩ of the R-2R ladder

network resistance when any single bit logic is high). The

static accuracy and dynamic performance will be affected by

this modulation. The gain and phase stability of the output

MONOTONICITY

Monotonicity assures that the analog output will increase or

stay the same for increasing digital input codes. The

DAC7541A is guaranteed monotonic to 12 bits.

POWER SUPPLY REJECTION

Power supply rejection is the measure of the sensitivity of

the output (full scale) to a change in the power supply

voltage.

®

5

DAC7541A

R_FB

R = 10kΩ

I_REF

R ≈ 10kΩ

I_{OUT 1}

V_REF

I_L

1/4096

I_L

60pF

90pF

55pF

I_REF

R ≈ 10kΩ

I_{OUT 2}

V_REF

1/4096

I_L

FIGURE 2. DAC7541A Equivalent Circuit (All inputs

LOW).

FIGURE 3. DAC7541A Equivalent Circuit (All inputs

HIGH).

amplifier, board layout, and power supply decoupling will

all affect the dynamic performance of the DAC7541A. The

use of a compensation capacitor may be required when high-

speed operational amplifiers are used. It may be connected

across the amplifier’s feedback resistor to provide the nec-

essary phase compensation to critically dampen the output.

See Figures 4 and 6.

BINARY INPUT

ANALOG OUTPUT

MSB

LSB

1111 1111 1111

1000 0000 0000

0000 0000 0001

0000 0000 0000

–V_REF(4095/4096)

–V_REF(2048/4096)

–V_REF(1/4096)

0V

TABLE I. Unipolar Codes.

C₁phase compensation (10 to 25pF) in Figure 4 may be

required for stability when using high speed amplifiers. C₁

is used to cancel the pole formed by the DAC internal

feedback resistance and output capacitance at Out₁.

APPLICATIONS

OP AMP CONSIDERATIONS

The input bias current of the op amp flows through the

feedback resistor, creating an error voltage at the output of

the op amp. This will show up as an offset through all codes

of the transfer characteristics. A low bias current op amp

such as the OPA606 is recommended.

R₁in Figure 5 provides full scale trim capability—load the

DAC register to 1111 1111 1111, adjust R₁for V_OUT= –

V_REF(4095/4096). Alternatively, full scale can be adjusted

by omitting R₁and R₂and trimming the reference voltage

magnitude.

Low offset voltage and V_OSdrift are also important. The

output impedance of the DAC is modulated with the digital

code. This impedance change (approximately 10kΩ to 30kΩ)

is a change in closed-loop gain to the op amp. The result is

that V_OSwill be multiplied by a factor of one to two

depending on the code. This shows up as a linearity error.

Offset can be adjusted out using Figure 4. Gain may be

adjusted using Figure 5.

BIPOLAR FOUR-QUADRANT OPERATION

Figure 6 shows the connections for bipolar four-quadrant

operation. Offset can be adjusted with the A₁to A₂summing

resistor, with the input code set to 1000 0000 0000. Gain

may be adjusted by varying the feedback resistor of A₂. The

input/output relationship is shown in Table II.

BINARY INPUT

ANALOG OUTPUT

UNIPOLAR BINARY OPERATION

(Two-Quadrant Multiplication)

MSB

LSB

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

+V_REF(2047/2048)

0V

–V_REF(1/2048)

–V_REF(2048/2048)

Figure 4 shows the analog circuit connections required for

unipolar binary (two-quadrant multiplication) operation. With

a DC reference voltage or current (positive or negative

polarity) applied at pin 17, the circuit is a unipolar D/A

converter. With an AC reference voltage or current, the

circuit provides two-quadrant multiplication (digitally con-

trolled attenuation). The input/output relationship is shown

in Table I.

TABLE II. Bipolar Codes.

®

6

DAC7541A

MSB

B₁

•

• B₁₂

B₁

2

B₂

4

B₃

8

B₁₂

V_OUT= –V_REF

+

+ • • • +

(

)

4096

4

5

6

7

8

9

10 11 12 13 14 15

R_F

Out₁

Out₂

C₁

16

17

18

1

+15V

–10V ≤ V_REF≤ +10V

DAC7541A

V_OUT

4095

0 ≤ V_OUT≤ –

V_REF

OPA604

V_REF

4096

2

3

Where: B_N= 1 if the B_Ndigital input is HIGH.

B_N= 0 if the B_Ndigital input is LOW.

10kΩ

Single-Point Ground

+V_CC

FIGURE 4. Basic Connection With Op Amp V_OSAdjust: Unipolar (two-quadrant) Multiplying Configuration.

MSB

B₁

R₁

200Ω

•

B₁₂

R₂

200kΩ

4

5

6

7

8

9

10 11 12 13 14 15

16

17

18

+15V

1

DAC7541A

OPA604

V_REF

2

3

10kΩ

+V_CC

FIGURE 5. Basic Connection With Gain Adjust (allows adjustment up or down).

47Ω

+V_DD

20kΩ

OPA604

or

1/2 OPA2604

C₁

33pF

16

18

1

10kΩ

V_REF

17

A₁

DAC7541A

V_OUT

A₂

4...15

2

OPA604

or

1/2 OPA2604

3

5kΩ

Bits 1-12

B₁

1

B₂

B₃

4

B₁₂

V_OUT= +V_REF

+

+ • • • +

– 1

(

)

2

2048

FIGURE 6. Bipolar Four-Quadrant Multiplier.

®

7

DAC7541A

DIGITALLY CONTROLLED GAIN BLOCK

The DAC7541A may be used in a digitally controlled gain

block as shown in Figure 7. This circuit gives a range of gain

from one (all bits = one) to 4096 (LSB = one). The transfer

function is:

Bits 1 to 12

V_IN

V_DD

18

DAC7541A

17

16

–V_IN

V_OUT

=

1

B₁

2

B₂

4

B₃

8

B₁₂

2

3

+

+ • • • +

(

)

4096

All bits off is an illegal state, as division by zero is impos-

sible (no op amp feedback). Also, errors increase as gain

increases, and errors are minimized at major carries (only

one bit on at a time).

V_OUT

OPA604

FIGURE 7. Digitally Programmable Gain Block.

®

8

DAC7541A

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jan-2007

PACKAGING INFORMATION

Orderable Device

DAC7541AJP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

PDIP

N

18

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DAC7541AJPG4

DAC7541AJU

PDIP

SOP

PDIP

SOP

N

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DTC

N

43 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

DAC7541AJUG4

DAC7541AKP

43 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DAC7541AKPG4

DAC7541AKU

N

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DTC

43 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

DAC7541AKU/1K

DAC7541AKU/1KG4

DAC7541AKUG4

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

43 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

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Addendum-Page 1

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型号：	DAC7541AJP
厂家：	BURR-BROWN CORPORATION
描述：	Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER 低成本12位CMOS四象限乘法数位类比转换器转换器
文件：	总10页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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