DAC7613E [BB]
12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER; 12位电压输出数位类比转换器
| 型号： | DAC7613E |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总9页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC7613
DAC7613
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 1.8mW
The DAC7613 is a 12-bit, voltage output digital-to-
analog converter with guaranteed 12-bit monotonic
performance over the specified temperature range.
The DAC7613 accepts a 12-bit parallel input data, has
double-buffered DAC input logic and provides a
readback mode of the internal input register. An asyn-
chronous reset clears all registers to a mid-scale code
of 800H or to a zero-scale of 000H. The DAC7613 can
operate from a single +5V supply or from +5V and
–5V supplies.
● UNIPOLAR OR BIPOLAR OPERATION
● SETTLING TIME: 10µs to 0.012%
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● DATA READBACK
● DOUBLE-BUFFERED DATA INPUTS
● 24-LEAD SSOP PACKAGE
Low power and small size makes the DAC7613 ideal
for data acquisition systems and closed-loop servo-
control. The DAC7613 is available in a plastic
SSOP-24 package, and offers guaranteed specifica-
tions over the –40°C to +85°C temperature range.
APPLICATIONS
● PROCESS CONTROL
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
VREFL VREFH
VDD
VSS
12
Data I/O
CS
Input
Register
DAC
Register
VOUT
DAC
I/O
Buffer
TS
R/W
DAC7613
RESET
RESETSEL LOADDAC
GND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
Printed in U.S.A. January, 2000
PDS-1500B
SPECIFICATION
At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted.
DAC7613E
DAC7613EB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error(1)
Differential Linearity Error
Monotonicity
VSS = 0V or –5V
VSS = 0V or –5V
TMIN to TMAX
±2
±1
±1
±1
LSB(2)
LSB
12
✻
Bits
Zero-Scale Error
Zero-Scale Drift
Full-Scale Error
Zero-Scale Error
Zero-Scale Drift
Full-Scale Error
Power Supply Rejection
Code = 000H
±4
5
✻
✻
✻
✻
✻
✻
LSB
2
✻
ppm/°C
LS
Code = FFFH
Code = 00AH, VSS = 0V
VSS = 0V
±4
±8
10
±8
LSB
5
✻
✻
ppm/°C
LSB
Code = FFFH, VSS = 0V
30
ppm/V
ANALOG OUTPUT
Voltage Output(3)
VREFL = 0V, VSS = 0V
VSS = –5V
0
VREFH
VREFH
+1.25
✻
✻
✻
✻
✻
✻
V
V
VREFL
–1.25
Output Current
mA
pF
mA
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
No Oscillation
100
✻
✻
✻
+5, –15
Indefinite
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
VREFL Input Range
VSS = 0V or –5V
VSS = 0V
VREFL + 1.25
+2.5
✻
✻
✻
✻
✻
✻
V
V
V
0
VREFH – 1.25
VREFH – 1.25
VSS = –5V
–2.5
DYNAMIC PERFORMANCE
Settling Time(4)
To ±0.012%
5
10
✻
✻
✻
µs
Output Noise Voltage
0Hz to 1MHz
40
nV/√Hz
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
CMOS
✻
IIH ≤ ±10µA
IIL ≤ ±10µA
IOH = –0.8mA
IOL = 1.6mA
0.7 VDD
–0.3
3.6
VDD + 0.3
0.3 VDD
VDD
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
VIL
VOH
VOL
0.0
0.4
Data Format
Straight Binary
✻
POWER SUPPLY REQUIREMENTS
VDD
4.75
5.25
✻
✻
✻
V
VSS
IDD
If VSS ≠ 0V
–5.25
–4.75
0.5
✻
✻
V
mA
0.35
–0.45
4
✻
✻
✻
✻
ISS
–0.65
✻
mA
mW
mW
Power Dissipation
VSS = –5V
VSS = 0V
5.75
2.5
✻
✻
1.8
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
✻
°C
NOTES: (1) If VSS = 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, when VREFH equals +2.5V and VREFL equals –2.5V,
then one LSB equals 1.22mV. (3) Ideal output voltage, does not take into account zero or full-scale error. (4) If VSS = –5V, full-scale 5V step. If VSS = 0V, full-scale
positive 2.5V step and negative step from code FFFH to 00AH.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC7613
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VDD to VSS ............................................................................. –0.3V to 11V
VDD to GND.......................................................................... –0.3V to 5.5V
VREFL to VSS .............................................................. –0.3V to (VDD – VSS
VDD to VREFH ............................................................. –0.3V to (VDD – VSS
VREFH to VREFL .......................................................... –0.3V to (VDD – VSS
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
)
)
)
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
LINEARITY
ERROR
MAXIMUM
DIFFERENTIAL
LINEARITY ERROR
(LSB)
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
(LSB)
PACKAGE
DAC7613E
±2
±1
SSOP-24
338
–40°C to +85°C
DAC7613E
Rails
"
"
"
"
"
"
DAC7613E/1K
Tape and Reel
DAC7613EB
±1
±1
SSOP-24
338
–40°C to +85°C
DAC7613EB
Rails
"
"
"
"
"
"
DAC7613EB/1K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7613E/1K” will get a single 1000-piece Tape and Reel.
®
3
DAC7613
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
Top View
SSOP
1
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VREFL
Data Bit 11, MSB
Data Bit 10
Data Bit 9
2
DB11 (MSB)
DB10
DB9
1
2
3
4
5
6
7
8
9
24 R/W
3
23 CS
4
Data Bit 8
22 RESETSEL
21 RESET
20 LOADDAC
19 VOUT
18 VDD
5
Data Bit 7
6
Data Bit 6
DB8
7
Data Bit 5
DB7
8
Data Bit 4
DB6
9
Data Bit 3
DAC7613E
DB5
10
11
12
13
Data Bit 2
Data Bit 1
DB4
17 GND
16 VSS
Data Bit 0, LSB
DB3
Reference Input Voltage Low. Sets minimum out-
put voltage for the DAC.
DB2 10
DB1 11
15 VREFH
14 NIC
14
15
NIC
Not Internally Connected
VREFH
Reference Input Voltage High. Sets maximum
output voltage for the DAC.
DB0 (LSB) 12
13 VREFL
16
VSS
Negative Analog Supply Voltage, 0V or –5V
nominal.
17
18
19
20
GND
VDD
Ground
Positive Power Supply
DAC Voltage Output
VOUT
LOADDAC
The selected DAC register becomes transparent
when LOADDAC is LOW. It is in the latched state
when LOADDAC is HIGH.
21
22
RESET
Asynchronous Reset Input. Sets the DAC register
to either zero-scale (000H) or mid-scale (800H)
when LOW. RESETSEL determines which code is
active.
RESETSEL
When LOW, a LOW on RESET will cause the DAC
register to be set to code 000H. When RESETSEL
is HIGH, a LOW on RESET will set the registers to
code 800H.
23
24
CS
Chip Select. Active LOW.
R/W
Enabled by CS. Controls data read and write from
the input register.
®
4
DAC7613
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR vs CODE
LINEARITY ERROR and
(–40°C and +85°C)
DIFFERENTIAL LINEARITY ERROR vs CODE
0.50
0.25
0.50
0.25
0.00
0.00
–0.25
–0.50
0.50
–0.25
–0.50
0.50
+85°C
0.25
0.25
0.00
0.00
–0.25
–0.50
–0.25
–0.50
–40°C
000H 200H 400H 600H 800H A00H C00H E00H FFFH
000H 200H 400H 600H 800H A00H C00H E00H FFFH
Digital Input Code
Digital Input Code
DIFFERENTIAL LINEARITY ERROR vs CODE
ZERO-SCALE ERROR vs TEMPERATURE
(Code 010H)
(–40°C and +85°C)
6
0.50
0.25
5
4
0.00
–0.25
–0.50
0.50
3
+85°C
2
1
0.25
0
0.00
–1
–2
–0.25
–0.50
–40°C
–40
–20
0
20
40
60
80
100
000H 200H 400H 600H 800H A00H C00H E00H FFFH
Temperature (°C)
Digital Input Code
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
6
5
4
3
2
1
0
–1
–2
–40
–20
0
20
40
60
80
100
Temperature (°C)
®
5
DAC7613
TYPICAL PERFORMANCE CURVES: VSS = – 5V
At TA = +25°C, VDD = +5V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR and
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR vs CODE
0.50
0.25
0.50
0.25
0.00
0.00
–0.25
–0.50
0.50
–0.25
–0.50
0.50
0.25
0.25
0.00
0.00
–0.25
–0.50
–0.25
–0.50
000H 200H 400H 600H 800H A00H C00H E00H FFFH
000H 200H 400H 600H 800H A00H C00H E00H FFFH
Digital Input Code
Digital Input Code
ZERO-SCALE ERROR vs TEMPERATURE
(Code 000H)
DIFFERENTIAL LINEARITY ERROR vs CODE
0.50
3.0
0.25
0.00
2.5
2.0
–0.25
–0.50
0.50
1.5
1.0
0.5
0.25
0.0
0.00
–0.5
–1.0
–0.25
–0.50
000H 200H 400H 600H 800H A00H C00H E00H FFFH
–40
–20
0
20
40
60
80
100
Digital Input Code
Temperature (°C)
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–40
–20
0
20
40
60
80
100
Temperature (°C)
®
6
DAC7613
register offers a readback capability. The converter can be
powered from a single +5V supply or a dual ±5V supply.
The device offers a reset function which immediately sets
the DAC output voltage and DAC register to mid-scale
(code 800H) or to zero-scale (code 000H), depending on the
status of the reset selection. See Figures 1 and 2 for the basic
operation of the DAC7613.
THEORY OF OPERATION
The DAC7613 is a 12-bit, voltage output Digital-to-Analog
Converter (DAC). The architecture is a classic R-2R ladder
configuration followed by an operational amplifier that serves
as a buffer. The minimum voltage output (“zero-scale”) and
maximum voltage output (“full-scale”) are set by the exter-
nal voltage references (VREFL and VREFH, respectively). The
digital input is a 12-bit parallel word and the DAC input
DAC7613E
1
2
3
4
5
6
7
8
9
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
R/W 24
CS 23
Read/Write
Chip Select
RESETSEL 22
RESET 21
LOADDAC 20
VOUT 19
Reset Select
Reset DAC
Load DAC Register
0V to +2.5V
Data Bus
VDD 18
+5V
+
0.1µF
1µF
GND 17
VSS 16
+2.5V
10 DB2
11 DB1
12 DB0
VREFH 15
NIC 14
0.1µF
VREFL 13
FIGURE 1. Basic Single-Supply Operation of the DAC7613.
DAC7613E
1
2
3
4
5
6
7
8
9
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
R/W 24
CS 23
Read/Write
Chip Select
Reset Select
Reset DAC
RESETSEL 22
RESET 21
LOADDAC 20
VOUT 19
Load DAC Register
–2.5V to +2.5V
Data Bus
VDD 18
+5V
+
0.1µF
1µF
1µF
GND 17
–5V
VSS 16
+
0.1µF
0.1µF
0.1µF
10 DB2
11 DB1
12 DB0
VREFH 15
NIC 14
+2.5V
–2.5V
VREFL 13
FIGURE 2. Basic Dual-Supply Operation of the DAC7613.
®
7
DAC7613
ANALOG OUTPUTS
The current into the VREFH input depends on the DAC output
voltages and can vary from a few microamps to approxi-
mately 0.1 milliamp. The VREFH source will not be required
to sink current, only source it. Bypassing the reference
voltage or voltages with at least a 0.1µF capacitor placed as
close to the DAC7613 package is strongly recommended.
When VSS = –5V (dual supply operation), the output ampli-
fier can swing to within 2.25V of the supply rails, guaran-
teed over the –40°C to +85°C temperature range. With
VSS = 0V (single-supply operation), the output can swing to
ground. Note that the settling time of the output op amp will
be longer with voltages very near ground. Additionally, care
must be taken when measuring the zero-scale error when
VSS = 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (000H, 001H, 002H, etc.) if the output
amplifier has a negative offset.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7613. Note
that the internal register is level triggered and not edge
triggered. When the appropriate signal is LOW, the register
becomes transparent. When this signal is returned HIGH, the
digital word currently in the register is latched. The first
register (the input register) is triggered via the R/W, and CS
inputs. The second register (the DAC register) is transparent
when LOADDAC input is pulled LOW.
The behavior of the output amplifier can be critical in some
applications. Under short-circuit conditions (DAC output
shorted to ground), the output amplifier can sink a great deal
more current than it can source. See the Specifications table
for more details concerning short-circuit current.
The double-buffered architecture is mainly designed so that
the DAC input register can be written at any time and then
the DAC voltage updated by pulling LOADDAC LOW.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 2.25V and VDD – 2.25V provided that VREFH
is at least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
connected to ground or must be in the range of –4.75V to
–5.25V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
INPUT
REGISTER
DAC
REGISTER
R/W
CS
RST LOADDAC
MODE
L
L
L
L
H
H
H
H
H
L
L
H
H
L
Write
Write
Read
Hold
Hold
Hold
Write
Hold
Write
Write Input
Read Input
Update
H
X
X
X
L
Hold
H
H
H
Update
Hold
H
X
Hold
Reset
Reset
X = Don’t Care.
TABLE I. DAC7613 Control Logic Truth Table.
®
8
DAC7613
DIGITAL TIMING
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
Figure 3 and Table II provide detailed timing for the digital
interface of the DAC7613.
tRCS
tRDS
tRDH
tDZ
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
200
10
0
ns
ns
ns
ns
CS HIGH to Data Bus in
High Impedance
100
100
DIGITAL INPUT CODING
The DAC7613 input data is in Straight Binary format. The
output voltage is given by the following equation:
tCSD
tWCS
tWS
CS LOW to Data Bus Valid
CS LOW for Write
160
ns
ns
ns
ns
ns
ns
ns
ns
50
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDAC LOW
(1)
V
– VREFL • N
(
+
)
tWH
5
REFH
VOUT = VREFL
tDS
0
4096
tDH
5
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
tLWD
tRESET
50
50
RESET LOW
TABLE II. Timing Specifications (TA = –40°C to +85°C).
tWCS
CS
tWS
tWH
R/W
tRCS
tLWD
CS
tRDH
tRDS
LOADDAC
Data In
tDH
tDS
R/W
tDZ
Data Valid
Data Out
tRESET
tCSD
RESET
Data Output Timing
Digital Input Timing
FIGURE 3. Digital Input and Output Timing.
®
9
DAC7613
相关型号：
DAC7613E/1K
D/A Converter, 1 Func, Parallel, Word Input Loading, 5us Settling Time, PDSO24, SSOP-24
BB
DAC7613EB/1K
D/A Converter, 1 Func, Parallel, Word Input Loading, 5us Settling Time, PDSO24, SSOP-24
BB
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