DAC7654YBR_技术文档

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SBAS263 − NOVEMBER 2003

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FEATURES

DESCRIPTION

D

Low Glitch: 1nV-s (typ)

The DAC7654 is

a

16-bit, quad voltage output,

digital-to-analog converter (DAC) with 16-bit monotonic

performance over the specified temperature range. It

accepts 24-bit serial input data, has double-buffered DAC

input logic (allowing simultaneous update of all DACs),

and provides a serial data output for daisy-chaining

multiple DACs. Programmable asynchronous reset clears

all registers to a mid-scale code of 8000h or to a zero-scale

of 0000h. The DAC7654 can operate from a single +5V

supply or from +5V and –5V supplies.

Low Power: 18mW

Unipolar or Bipolar Operation

Settling Time: 12µs to 0.003%

16-Bit Linearity and Monotonicity:

–40°C to +85°C

Programmable Reset to Mid-Scale or

Zero-Scale

D

Double-Buffered Data Inputs

Internal Bandgap Voltage Reference

Power-On Reset

Low power and small size per DAC make the DAC7654

ideal for automatic test equipment, DAC-per-pin

programmers, data acquisition systems, and closed-loop

servo-control. The DAC7654 is available in an LQFP

package and is specified for operation over the –40°C to

+85°C temperature range.

3V to 5V Logic Interface

APPLICATIONS

IO V _DD

V _DD

V _SS

V _CC

D

Process Control

DAC7654

Closed-Loop Servo-Control

Motor Control

V

H A and B

REF

V

L

Bandgap

Voltage Reference

REF

V

L A and B

REF

H

Data Acquisition Systems

DAC-per-Pin Programmers

REF

V

A Sense 2

A Sense 1

A

OUT

SDI

Input

DAC

Register A

DAC A

DAC B

DAC C

DAC D

Shift

Register

Register A

OFSR1A

OFSR2A

SDO

V

B Sense 2

OUT

Input

DAC

Register B

B Sense 1

B

Register B

OFSR1B

OFSR2B

V

C Sense 2

C Sense 1

C

OUT

Input

DAC

Register C

CS

Register C

CLOCK

RST

OFSR1C

OFSR2C

Control

Logic

RSTSEL

LDAC

V

D Sense 2

OUT

Input

DAC

Register D

D Sense 1

D

Register D

LOAD

OFSR1D

OFSR2D

V

L C and D

REF

V

H C and D

REF

A GND

D GND

This device has ESD-CDM sensitivity and special handling precautions must be taken.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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ꢜꢘ ꢌ ꢊꢈꢥ ꢅ ꢄꢌ ꢔ ꢑꢘ ꢌ ꢥ ꢏ ꢤ ꢤ ꢄꢔ ꢎ ꢊꢌ ꢏ ꢤ ꢔꢌꢅ ꢔꢏ ꢥꢏ ꢤꢤ ꢉꢘ ꢄꢍ ꢫ ꢄꢔꢥ ꢍꢈꢊ ꢏ ꢅꢏ ꢤꢅꢄ ꢔꢎ ꢌꢢ ꢉꢍ ꢍ ꢑꢉ ꢘ ꢉꢣ ꢏꢅꢏ ꢘ ꢤꢧ

Copyright  2003, Texas Instruments Incorporated

www.ti.com

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SBAS263 − NOVEMBER 2003

(1)

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE−LEAD

DAC7654YT

DAC7654YR

DAC7654YBT

DAC7654YBR

DAC7654YCT

DAC7654YCR

Tape and Reel, 250

Tape and Reel, 1500

Tape and Reel, 250

Tape and Reel, 1500

Tape and Reel, 250

Tape and Reel, 1500

DAC7654Y

DAC7654YB

DAC7654YC

LQFP−64

PM

−40°C to +85°C

DAC7654Y

DAC7654YB

DAC7654YC

(1)

For the most current specification and package information, see the Package Ordering Addendum at the end of this data sheet.

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handledwith appropriate precautions. Failure to observe

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

proper handling and installation procedures can cause damage.

DAC7654

−0.3 to 11

−0.3 to 5.5

UNIT

IOV , V

DD CC

and V

to V

SS

V

DD

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

IOV , V

DD CC

to GND

DD

Digital Input Voltage to GND

Digital Output Voltage to GND

ESD-CDM

−0.3 to V

+ 0.3

DD

−0.3 to V

+ 0.3

DD

200

+150

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

Lead Temperature (soldering, 10s)

°C

−40 to +85

−65 to +125

+300

(1)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum conditions for extended periods may degrade

device reliability. These are stress ratings only, and functional

operationof the device at these or any other conditions beyond

those specified is not implied.

2

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SBAS263 − NOVEMBER 2003

ELECTRICAL CHARACTERISTICS: V

= 0V

SS

All specifications at T = T

A

to T

, IOV

DD

= V

DD

= V

CC

= +5V, and V

= 0V, unless otherwise noted.

MIN

MAX

SS

DAC7654Y

TYP

DAC7654YB

DAC7654YC

PARAMETER

Accuracy

TEST CONDITIONS

MIN

MAX

MIN

TYP MAX

MIN TYP MAX

UNIT

Linearity error

3

4

2

4

3

2

1

3

2

[

LSB

Linearity match

Differential linearity error

−1

16

+2

LSB

Monotonicity, T

to T

MAX

14

15

Bit

MIN

Unipolar zero error

1

5

10

20

15

7

[

mV

Unipolar zero error drift

Full-scale error

[

12.5

[

ppm/°C

mV

6

4

Full-scale error drift

Unipolar zero matching

Full-Scale matching

7

[

ppm/°C

mV

Channel-to-channel matching

3

2

5

4

10

100

2

8

mV

Power-supply rejection ratio (PSRR) At full-scale

10

[

ppm/V

Analog Output

Voltage output

R

= 10kΩ

0

2.5

[

V

L

Output current

−1.25

+1.25

mA

pF

Maximum load capacitance

Short-circuit current

Short-circuit duration

Dynamic Performance

Settling time

No oscillation

500

20

[

mA

GND or V

CC

Indefinite

To 0.003%, 2.5V output step

12

0.5

2

15

[

µs

LSB

Channel-to-channel crosstalk

Digital feedthrough

Output noise voltage

nV-s

f = 10kHz

130

nV/√Hz

7FFFh to 8000h or

8000h to 7FFFh

DAC glitch

1

5

[

nV-s

Digital Input

V

[

V

0.7 × IOV

IH

DD

V

[

0.3 × IOV

DD

IL

I

10

µA

IH

10

IL

Digital Output

V

I

= −0.8mA, IOV

= 5V

3.6

2.4

4.5

[

V

OH

OL

OH

OL

OH

OL

OH

OL

DD

= 1.6mA, IOV

= 5V

0.3

2.6

0.3

0.4

[

DD

= −0.4mA, IOV

= 0.8mA, IOV

= 3V

DD

= 3V

DD

Power Supply

V

+4.75

+2.7

+4.75

0

+5.0

0

+5.25

0

[

V

DD

IOV

DD

CC

V

SS

CC

DD

I

3.5

50

5

mA

µA

mW

I(IOV

)

50

DD

Power

18

25

[

Temperature Range

Specified performance

−40

+85

[

°C

[ specifications same as the grade to the left

3

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SBAS263 − NOVEMBER 2003

ELECTRICAL CHARACTERISTICS: V

= −5V

SS

All specifications at T = T

A

to T

, IOV

DD

= V

DD

= V

CC

= +5V, and V = −5V, unless otherwise noted.

SS

MIN

MAX

DAC7654Y

TYP

DAC7654YB

DAC7654YC

PARAMETER

Accuracy

TEST CONDITIONS

MIN

MAX

MIN

TYP MAX MIN TYP MAX

UNIT

Linearity error

3

4

2

4

3

2

1

3

2

[

LSB

Linearity match

Differential linearity error

−1

16

+2

LSB

Monotonicity, T

to T

MAX

14

15

Bit

MIN

Bipolar zero error

1

5

10

20

15

7

[

mV

Bipolar zero error drift

Full-scale error

[

12.5

[

ppm/°C

mV

6

4

Full-scale error drift

Bipolar zero matching

Full-Scale matching

7

[

ppm/°C

mV

Channel-to-channel matching

3

2

5

4

10

100

2

8

mV

Power-supply rejection ratio (PSRR) At full-scale

10

[

ppm/V

Analog Output

Voltage output

R

= 10kΩ

−2.5

+2.5

[

V

L

Output current

−1.25

+1.25

mA

pF

Maximum load capacitance

Short-circuit current

Short-circuit duration

Dynamic Performance

Settling time

No oscillation

500

[

−15, +30

Indefinite

mA

GND or V

CC

or V

SS

To 0.003%, 5V output step

12

0.5

2

15

[

µs

LSB

Channel-to-channel crosstalk

Digital feedthrough

Output noise voltage

nV-s

f = 10kHz

200

nV/√Hz

7FFFh to 8000h or

8000h to 7FFFh

DAC glitch

2

7

[

nV-s

Digital Input

V

[

V

0.7 × IOV

IH

DD

V

[

0.3 × IOV

DD

IL

I

10

µA

IH

10

IL

Digital Output

V

I

= −0.8mA, IOV

= 5V

3.6

2.4

4.5

[

V

OH

OL

OH

OL

OH

OL

OH

OL

DD

= 1.6mA, IOV

= 5V

0.3

2.6

0.3

0.4

[

DD

= −0.4mA, IOV

= 0.8mA, IOV

= 3V

DD

= 3V

DD

Power Supply

V

+4.75

+2.7

+5.0

−5.0

4

+5.25

−4.75

5.5

[

V

DD

IOV

DD

CC

V

+4.75

−5.25

V

SS

CC

DD

I

mA

µA

mA

mW

50

I(IOV

)

50

DD

I

−3.5

−40

−2.0

30

[

SS

Power

45

[

Temperature Range

Specified performance

+85

[

°C

[ specifications same as the grade to the left

4

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PIN ASSIGNMENTS

LQFP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

32

31

Offset D Range 1

Offset D Range 2

NC

Offset C Range 2 51

30 NC

52

53

54

55

56

57

58

59

60

29

28

27

Offset C Range 1

V_DD

V

_OUTC Sense 2

_OUTC Sense 1

DGND

RSTSEL

V

V_OUTC

26 RST

25 LDAC

24 LOAD

Reference GND

DAC7654

23

22

21

V

_OUTB

_OUTB Sense 1

V_OUTB Sense 2

SDI

CLK

CS

V

Offset B Range 1 61

20 SDO

62

63

64

19

18

17

Offset B Range 2

Offset A Range 2

Offset A Range 1

IOV_DD

V_DD

DGND

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

5

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Terminal Functions

NAME

DESCRIPTION

NAME

DESCRIPTION

1

2

3

4

5

6

NC

No Connection

36

37

38

39

40

41

42

43

44

NC

No connection

V

Analog –5V power supply or 0V single supply

Analog +5V power supply

SS

CC

V

A

DAC A output voltage

OUT

A

Connect to V

A for unipolar mode

OUT

Sense 1

OUT

7

V

A

Connect to V

A for bipolar mode

OUT

Sense 2

AGND

NC

V

D

Connect to V

D for bipolar mode

D for unipolar mode

OUT

Sense 2

OUT

8

Analog ground

No connection

Digital ground

9

45

V

D

Connect to V

OUT

Sense 1

OUT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

NC

46

47

48

49

V

D

DAC D output

No connection

OUT

NC

Offset D

Range 1

Connect to Offset D Range 2 for unipolar

mode

NC

50

51

52

53

54

Offset D

Range 2

Connect to Offset D Range 1 for unipolar

mode

NC

DGND

Offset C

Range 2

Connect to Offset C Range 1 for unipolar

mode

V

DD

Digital +5V power supply

Interface power supply

IOV

DD

SDO

Offset C

Range 1

Connect to Offset C Range 2 for unipolar

mode

Serial data output

CS

CLK

Chip select, active low

V

C

Connect to V

C for bipolar mode

OUT

Sense 2

OUT

Data clock input

SDI

Serial data input

V

C

Connect to V

C for unipolar mode

OUT

Sense 1

OUT

LOAD

LDAC

RST

DAC input register load control, active low

DAC register load control, rising edge triggered

55

56

57

58

59

V

C

DAC C output

OUT

Reset, rising edge triggered. Depending on

the state of RSTSEL, the DAC registers are

set to either mid-scale or zero.

REF GND Reference ground

V

B

DAC B output

OUT

27

RSTSEL Reset select. Determines the action of RST.

If high, an RST command sets the DAC

registers to mid-scale (8000h). If low, an RST

command sets the DAC registers to zero

(0000h).

Connect to V

B for unipolar mode

B for bipolar mode

OUT

Sense 1

OUT

60

61

62

63

64

V

B

Connect to V

OUT

Sense 2

OUT

Offset B

Range 1

Connect to Offset B Range 2 for unipolar

mode

28

29

30

31

32

33

34

35

DGND

Digital ground

V

DD

Digital +5V power supply

No connection

Offset B

Range 2

Connect to Offset B Range 1 for unipolar

mode

NC

Offset A

Range 2

Connect to Offset A Range 1 for unipolar

mode

Offset A

Range 1

Connect to Offset A Range 2 for unipolar

mode

6

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TYPICAL CHARACTERISTICS: V

= 0V

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V = 0V, representative unit, unless otherwise noted.

SS

A

+255C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC A, +25 C)

_

(DAC B, +25 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

−

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

−

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 1

Figure 2

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC C, +25 C)

_

(DAC D, +25 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

−

0.5

1.0

1.5

2.0

−

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

−

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 3

Figure 4

7

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TYPICAL CHARACTERISTICS: V

= 0V (continued)

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V

SS

= 0V, representative unit, unless otherwise noted.

A

+855C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC A, +85 C)

(DAC B, +85 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

−

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

−

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 5

Figure 6

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC C, +85 C)

(DAC D, +85 C)

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 7

Figure 8

8

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= 0V (continued)

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V = 0V, representative unit, unless otherwise noted.

SS

A

−405C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

−

_

−

_

(DAC A, 40 C)

(DAC B, 40 C)

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 9

Figure 10

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

−

_

(DAC C, 40 C)

−

_

(DAC D, 40 C)

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

−

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

−

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 11

Figure 12

9

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TYPICAL CHARACTERISTICS: V

= 0V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V = 0V, representative unit, unless otherwise noted.

A

SS

SUPPLY CURRENT vs TEMPERATURE

SUPPLY CURRENT vs DIGITAL INPUT CODE

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

All DACs at Midscale

No Load

All DACs

No Load

I_CC

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

−

15

40

10

35

60

85

Digital Input Code

_

Temperature ( C)

Figure 13

Figure 14

ZERO−SCALE ERROR vs TEMPERATURE

(Code 0000h)

POSITIVE FULL−SCALE ERROR vs TEMPERATURE

10

8

10

(Code FFFFh)

8

6

4

2

0

2

4

6

8

6

DAC D

4

DAC B

DAC C

DAC B

DAC C

DAC A

2

0

−

2

4

6

8

DAC D

DAC A

−

10

−

15

40

15

10

35

60

85

40

10

35

60

85

_

Temperature ( C)

_

Temperature ( C)

Figure 15

Figure 16

BROADBAND NOISE

(Code = 8000h, BW = 10kHz)

OUTPUT NOISE VOLTAGE vs FREQUENCY

1000

100

10

Time (10ms/div)

10

100

1k

10k

100k

1M

Frequency (Hz)

Figure 17

Figure 18

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TYPICAL CHARACTERISTICS: V

= 0V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V

SS

= 0V, representative unit, unless otherwise noted.

A

SETTLING TIME

(0V to +2.5V)

SETTLING TIME

(+2.5V to 39mV)

Large Signal: 1.0V/div

µ

Small Signal: 100 V/div

Large Signal: 1.0V/div

µ

Small Signal: 100 V/div

µ

Time (5 s/div)

Figure 19

Figure 20

MIDSCALE GLITCH PERFORMANCE

CODE 7FFFh to 8000h

MIDSCALE GLITCH PERFORMANCE

CODE 8000h to 7FFFh

Unfiltered DAC Output

DAC Output after

DAC Output After

2K, 470pF Low−Pass Filter

µ

Time (0.5 s/div)

Figure 21

Figure 22

OVERSHOOT FOR TRANSITION OF 100 CODES

CODE 32750 to 32850

OVERSHOOT FOR TRANSITION OF 100 CODES

CODE 32850 to 32750

Unfiltered DAC Output

DAC Output After

2K, 470pF Low−Pass Filter

DAC Output After

2K, 470pF Low−Pass Filter

100

Codes

Unfiltered DAC Output

µ

Time (1.0 s/div)

Figure 23

Figure 24

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= 0V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V

SS

= 0V, representative unit, unless otherwise noted.

A

IOVDD SUPPLY CURRENT

vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS

V_OUTvs R_LOAD

0.8

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Typical of One

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Digital Input

IOVDD = 5V

Source

Sink

10

0

1

2

3

4

5

0.01

0.1

1

100

Logic Input Level for Digital Inputs (V)

Ω

R_LOAD(k )

Figure 26

Figure 25

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= −5V

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V = −5V, representative unit, unless otherwise noted.

SS

A

+255C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC A, +25 C)

(DAC B, +25 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 27

Figure 28

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC D, +25 C)

(DAC C, +25 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 29

Figure 30

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= −5V (continued)

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V

SS

= −5V, representative unit, unless otherwise noted.

A

+855C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC A, +85 C)

(DAC B, +85 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 31

Figure 32

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

_

(DAC C, +85 C)

(DAC D, +85 C)

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

−

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 33

Figure 34

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= −5V (continued)

SS

All specifications at T = 25°C, IOV

= V

DD DD

= V

CC

= +5V, V = −5V, representative unit, unless otherwise noted.

SS

A

−405C

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

−

_

−

_

(DAC A, 40 C)

(DAC B, 40 C)

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 35

Figure 36

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

−

_

−

_

(DAC C, 40 C)

(DAC D, 40 C)

2.0

1.5

1.0

0.5

0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

−

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

−

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

−

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

Digital Input Code

Figure 37

Figure 38

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TYPICAL CHARACTERISTICS: V

= −5V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V = −5V, representative unit, unless otherwise noted.

A

SS

SUPPLY CURRENT vs TEMPERATURE

I_CC

SUPPLY CURRENT vs DIGITAL INPUT CODE

I_CC

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

−

1

2

3

4

5

−

I_SS

−

All DACs

No Load

All DACs at Midscale

No Load

0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

−

15

40

10

35

60

85

Digital Input Code

_

Temperature ( C)

Figure 39

Figure 40

BIPLOAR ZERO ERROR vs TEMPERATURE

(Code 8000h)

POSITIVE FULL−SCALE ERROR vs TEMPERATURE

10

8

10

8

(Code FFFFh)

6

DAC C

DAC B

4

DAC C

DAC D

DAC B

2

0

−

2

4

6

8

2

4

6

8

DAC A

−

10

−

15

40

15

10

35

60

85

40

10

35

60

85

_

Temperature ( C)

Figure 41

Figure 42

NEGATIVE FULL−SCALE ERROR vs TEMPERATURE

(Code 0000h)

10

8

6

DAC B

4

2

DAC A

0

−

2

4

6

8

DAC C

DAC D

−

10

−

15

40

10

35

60

85

_

Temperature ( C)

Figure 43

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TYPICAL CHARACTERISTICS: V

= −5V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V = −5V, representative unit, unless otherwise noted.

A

SS

BROADBAND NOISE

(Code = 8000h, BW = 10kHz)

OUTPUT NOISE VOLTAGE vs FREQUENCY

1000

100

10

100

1k

10k

100k

1M

Time (10ms/div)

Figure 44

SETTLING TIME

Frequency (Hz)

Figure 45

SETTLING TIME

−

(+2.5V to 2.5V)

( 2.5V to +2.5V)

Large Signal: 1.0V/div

µ

Small Signal: 100 V/div

µ

Small Signal: 100 V/div

Large Signal: 1.0V/div

µ

Time (5 s/div)

Figure 46

Figure 47

MIDSCALE GLITCH PERFORMANCE

CODE 7FFFh to 8000h

MIDSCALE GLITCH PERFORMANCE

CODE 8000h to 7FFFh

Unfiltered DAC Output

DAC Output after

DAC Output After

2K, 470pF Low−Pass Filter

µ

Time (0.5 s/div)

Figure 48

Figure 49

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SBAS263 − NOVEMBER 2003

TYPICAL CHARACTERISTICS: V

= −5V (continued)

SS

All specifications at T = 25°C, IOV

DD

= V

DD

= V

CC

= +5V, V = −5V, representative unit, unless otherwise noted.

SS

A

OVERSHOOT FOR TRANSITION OF 100 CODES

CODE 32750 to 32850

OVERSHOOT FOR TRANSITION OF 100 CODES

CODE 32850 to 32750

Unfiltered DAC Output

DAC Output After

2K, 470pF Low−Pass Filter

DAC Output After

2K, 470pF Low−Pass Filter

100

Codes

Unfiltered DAC Output

µ

Time (1.0 s/div)

Figure 50

Figure 51

V_OUTvs R_LOAD

5

4

3

2

1

0

Source

−

1

2

3

4

5

Sink

−

0.01

0.1

1

10

100

Ω

R_LOAD(k )

Figure 52

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THEORY OF OPERATION

The DAC7654 is a quad voltage output, 16-bit DAC. The

architecture is an R−2R ladder configuration with the three

most significant bits (MSBs) segmented, followed by an

operational amplifier that serves as a buffer. Each DAC

has its own R−2R ladder network, segmented MSBs, and

output op amp, as shown in Figure 53. The minimum

voltage output (zero-scale) and maximum voltage output

(full-scale) are set by the internal voltage references and

the resistors associated with the output operational

amplifier.

The digital input is a 24-bit serial word that contains a 2-bit

address code for selecting one of four DACs, a quick load

bit, five unused bits, and the 16-bit DAC code (MSB first).

The converters can be powered from either a single +5V

supply or a dual 5V supply. The device offers a reset

function that immediately sets all DAC output voltages and

DAC registers to mid-scale (code 8000h) or to zero-scale

(code 0000h). See Figure 54 and Figure 55 for basic

single- and dual-supply operation of the DAC7654.

V_OUTS1

Ω

13K

Ω

13K

V_OUTS2

Ω

100

R

V_OUT

2R

OFSR2

Ω

13K

11K

12K

OFSR1

Ω

V_REF

H

L

V_REF

Figure 53. DAC7654 Architecture

19

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0V to +2.5V

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49 Offset D Range 1

NC 32 NC

NC 31 NC

NC 30 NC

V_DD29

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Offset D Range 2

Offset C Range 2

Offset C Range 1

V_OUTC Sense 2

V_OUTC Sense 1

NC

28

27

26

25

24

23

22

21

20

19

18

17

DGND

RSTSEL

RST

0V to +2.5V

V_OUT

C

Reset DAC Register

Load DAC Registers

Load

DAC7654

Reference GND

LDAC

LOAD

SDI

Single Supply

NC = No Connection

V_OUT

B

Serial Data In

Clock

0V to +2.5V

V_OUTB Sense 1

V_OUTB Sense 2

Offset B Range 1

Offset B Range 2

Offset A Range 2

Offset A Range 1

CLK

NC

CS

Chip Select

SDO

Serial Data Out

+3V to +5V

IOV_DD

V_DD

+

µ

F

0.1

F

1

DGND

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

NC NC

NC

NC NC NC NC NC NC NC NC

0V to +2.5V

+5V

+

µ

F

1

F

0.1

Figure 54. Basic Single-Supply Operation of the DAC7654

20

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−

2.5V to +2.5V

NC NC

NC

NC NC NC NC NC NC NC NC NC NC NC

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

32

31

NC

Offset D Range 1

Offset D Range 2

NC

NC 51 Offset C Range 2

NC 30 NC

52

53

54

29

28

27

NC

Offset C Range 1

V_{OU T}C Sense 2

V_{OU T}C Sense 1

V_DD

DGND

RSTSEL

−

55 V_{OU T}

C

RST 26

LDAC 25

LOAD 24

SDI 23

2.5V to +2.5V

Reset DAC Register

Load DAC Registers

Load

DAC7654

Dual Supply

NC = No Connection

56

57

Reference GND

58 V_{OU T}

B

Serial Data In

Clock

2.5V to +2.5V

NC 59 V_{OU T}B Sense 1

CLK 22

60

61

62

21

20

19

V_{OU T}B Sense 2

Offset B Range 1

Offset B Range 2

CS

SDO

Chip Select

NC

Serial Data Out

+3V to +5V

+

IOV_DD

NC 63 Offset A Range 2

NC 64 Offset A Range 1

V_DD18

µ

F

0.1

F

1

DGND 17

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

NC NC

NC

NC NC NC NC NC NC NC NC

−

5V

µ

1

F

0.1

F

+

−

2.5V to +2.5V

+5V

+

µ

F

1

F

0.1

Figure 55. Basic Dual-Supply Operation of the DAC7654

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The DAC7654 offers

a

force and sense output

ANALOG OUTPUTS

configuration for the high open-loop gain output amplifier.

This feature allows the loop around the output amplifier to

be closed at the load (as shown in Figure 56), thus

ensuring an accurate output voltage.

When V_SS= –5V (dual-supply operation), the output

amplifier can swing to within 2.25V of the supply rails over

a range of –40°C to +85°C. When V_SS= 0V (single-supply

operation), and with R_LOADalso connected to ground, the

output can swing to within 5mV of ground. Care must be

taken when measuring the zero-scale error when

V_SS= 0V. Since the output voltage cannot swing below

ground, the output voltage may not change for the first few

digital input codes (0000h, 0001h, 0002h, etc.) if the output

amplifier has a negative offset.

DIGITAL INTERFACE

Table 1 shows the basic control logic for the DAC7654.

The interface consists of a signal data clock (CLK) input,

serial data in (SDI), DAC input register load control signal

(LOAD), and DAC register load control signal (LDAC). In

addition, a chip select (CS) input is available to enable

serial communication when there are multiple serial

devices. An asynchronous reset (RST) input, by the rising

edge, is provided to simplify startup conditions, periodic

resets, or emergency resets to a known state, depending

on the status of the reset select (RSTSEL) signal.

Due to the high accuracy of these DACs, system design

problems such as grounding and contact resistance are

very important. A 16-bit converter with a 2.5V full-scale

range has a 1LSB value of 38µV. With a load current of

1mA, series wiring and connector resistance of only 40mΩ

(R_W2) will cause a voltage drop of 40µV, as shown in

Figure 56. To understand what this means in terms of

system layout, the resistivity of a typical 1-ounce

copper-clad printed circuit board is 1/2 mΩ per square. For

a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6

inches long will result in a voltage drop of 30µV.

R_W1

V_OUTA Sense1

6

5

8

R_W2

V

_OUTA

V_OUT

DAC7654

AGND

R_W1

V_OUTB Sense1 59

58

R_W2

V_OUT

V

_OUTB

Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7654). R represents wiring resistances.

W

Table 1. DAC7654 Logic Truth Table

A1

L

A0

L

CS

L

RST

H

RSTSEL LDAC

LOAD INPUT REGISTER DAC REGISTER

MODE

Write input

Update

DAC

A

X

L

X

↑

L

Write

Hold

L

H

L

H

B

H

X

L

H

L

Write

Hold

C

H

X

L

H

L

Write

Hold

D

H

X

H

X

Hold

Write

All

X

H

X

Hold

X

↑

Reset to zero

X

↑

H

Reset to mid-scale Reset to mid-scale Reset to mid-scale

22

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The DAC code, quick load control, and address are provided

via a 24-bit serial interface (see Table 3; also see Figure 58,

page 25). The first two bits select the input register that will

be updated when LOAD goes low. The third bit is a Quick

Load bit; if high, the code in the shift register is loaded into

all of the DAC input registers when the LOAD signal goes

low. If the Quick Load bit is low, the content of shift register

is loaded only to the DAC input register that is addressed.

The Quick Load bit is followed by five unused bits. The last

16 bits (MSB first) are the DAC code.

CS and CLK are used, CS should rise only when CLK is high.

If not, then either CS or CLK can be used to operate the shift

register. Table 2 shows more information.

Table 2. Serial Shift Register Truth Table

(1)

CS

(1)

CLK

LOAD

RST

H

SERIAL SHIFT REGISTER

No change

(2)

H

(2)

X

H

(2)

L

H

No change

(2)

↑

L

H

Advanced one bit

No change

The internal DAC register is edge triggered and not level

triggered. When the LDAC signal is transitioned from low

to high, the digital word currently in the DAC input register

is latched. The first set of registers (the DAC input

registers) are level triggered via the LOAD signal. This

double-buffered architecture has been designed so that

new data can be entered for each DAC without disturbing

the analog outputs. When the new data has been entered

into the device, all of the DAC outputs can be updated

simultaneously by the rising edge of LDAC. Additionally, it

allows writing to the DAC input registers at any point,

which permits the DAC output voltages to be

synchronously changed via a trigger signal (LDAC).

↑

L

H

(3)

(4)

L

H

X

H

(3)

(5)

↑

H

No change

(1)

(2)

CS and CLK are interchangeable.

H = logic high. X = don’t care. L = logic low. ↑ = positive logic

transition.

(3)

(4)

A high value is suggested in order to avoid a false clock from

advancing and changing the shift register.

If data are clocked into the serial register while LOAD is low, the

selected DAC register will change as the shift register bits flow

throughA1 and A0. This will corrupt the data in each DAC register

that has been erroneously selected.

(5)

Rising edge of RST causes no change in the contents of the serial

shift register.

3V TO 5V LOGIC INTERFACE

GLITCH SUPPRESSION CIRCUIT

All of the digital input and output pins are compatible with

any logic supply voltage between 3V and 5V. Connect the

interface logic supply voltage to the IOV_DDpin. Note that

the internal digital logic operates from 5V, so the VDD pin

must connect to a 5V supply.

Figure 21, Figure 22, Figure 48, and Figure 49 show the

typical DAC output when switching between codes 7FFFh

and 8000h. For R-2R ladder DACs, this is potentially the

worst-case glitch condition, since every switch in the DAC

changes state. To minimize the glitch energy at this and

other code pairs with possible high-glitch outputs, an

internal track-and-hold circuit is used to maintain the DAC

ouput voltage at a nearly constant level during the internal

switching interval. This track-and-hold circuit is activated

only when the transition is at, or close to, one of the code

pairs with the high-glitch possibility.

CS AND CLK INPUTS

Note that CS and CLK are combined with an OR gate, which

controls the serial-to-parallel shift register. These two inputs

are completely interchangeable. However, care must be

taken with the state of CLK when CS rises at the end of a

serial transfer. If CLK is low when CS rises, the OR gate will

provide a rising edge to the shift register, shifting the internal

data by one additional bit. The result will be incorrect data and

the possible selection of the wrong input register(s). If both

It is advisable to avoid digital transitions within 1µs of the

rising edge of the LDAC signal. These signals can affect

the charge on the track-and-hold capacitor, thus

increasing the glitch energy.

Table 3. 24-Bit Data and Command Word

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A1

A0 Quick

Load

X

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

23

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SBAS263 − NOVEMBER 2003

SERIAL DATA OUTPUT

DIGITAL INPUT CODING

The serial-data output (SDO) is the internal shift register

output. For the DAC7654, the SDO is a driven output and

does not require an external pull-up. Any number of

DAC7654s can be daisy-chained by connecting the SDO

pin of one device to the SDI pin of the following device in

the chain, as shown in Figure 57.

The DAC7654 input data is in straight binary format. The

output voltage for single-supply operation is given by

Equation 1:

2.5 N

V_OUT

+

65, 536

(1)

where N is the digital input code.

This equation does not include the effects of offset

(zero-scale) or gain (full-scale) errors.

DIGITAL TIMING

Figure 58 and Table 4 provide detailed timing for the digital

interface of the DAC7654.

The output for the dual supply operation is given by

Equation 2:

5 N

V_OUT

+

* 2.5

65, 536

(2)

DAC7654

CLK

DAC7654

CLK

SCK

DIN

CS

CLK

SDI

CS

SDO

SDI

CS

SDI

CS

To

Other

Serial

Devices

Figure 57. Daisy-Chaining the DAC7654

24

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SBAS263 − NOVEMBER 2003

(LSB)

D0

(MSB)

A1

QUICK

LOAD

SDI

A0

X

D15

D1

CLK

t_CSH

t

css

CS

t_LDDD

t_LD2

t_LD1

LOAD

t_LDRW

LDAC

t_DS

t_DH

SDI

t_CL

t_CH

CLK

t_LDDL

t_LDDH

LDAC

V_OUT

t_S

1 LSB

ERROR BAND

1 LSB

ERROR BAND

t_RSTL

t_RSTH

RST

t_RSSH

t_RSSS

RSTSEL

Figure 58. Digital Input and Output Timing

Table 4. Timing Specifications for Figure 58

SYMBOL

DESCRIPTION

Data valid to CLK rising

Data held valid after CLK rises

CLK high

MIN

10

20

25

15

0

UNITS

t

ns

µs

DS

DH

CH

t

CLK low

CL

t

CS low to CLK rising

CLK high to CS rising

LOAD high to CLK rising

CLK rising to LOAD low

LOAD low time

CSS

CSH

t

10

30

100

150

0

LD1

LD2

t

LDRW

t

LDAC low time

LDDL

LDDH

RSSS

RSSH

t

LDAC high time

t

RSTSEL valid to RST high

RST high to RSTSEL not valid

RST low time

t

100

10

t

RSTL

RSTH

t

RST high time

t

S

Settling time

25

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LQFP

Drawing

DAC7654YBR

DAC7654YBT

DAC7654YCR

DAC7654YCT

DAC7654YR

DAC7654YT

ACTIVE

PM

64

1500

250

TBD

CU SNPB

Level-3-240C-168 HR

PM

1500

250

PM

1500

250

PM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.

1

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型号：	DAC7654YBR
厂家：	BURR-BROWN CORPORATION
描述：	16-Bit, Dual Voltage Output DIGITAL-TO-ANALOG CONVERTER 16位，双电压输出数位类比转换器转换器
文件：	总28页 (文件大小：468K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC7654YBR [BB]

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