DAC7742 [BB]
16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface; 16位单通道数位类比转换器内置电压基准及并行接口型号: | DAC7742 |
厂家: | BURR-BROWN CORPORATION |
描述: | 16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface |
文件: | 总19页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC7742
D
A
C
7
7
4
2
SBAS256 – DECEMBER 2002
16-Bit, Single Channel
DIGITAL-TO-ANALOG CONVERTER
With Internal Reference and Parallel Interface
DESCRIPTION
FEATURES
ꢀ LOW POWER: 150mW Maximum
The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC)
that provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V,
low-drift internal reference. Designed for automatic test equip-
ment and industrial process control applications, the DAC7742
output swing can be configured in a ±10V, ±5V, or +10V
range. The flexibility of the output configuration allows the
DAC7742 to provide both unipolar and bipolar operation by
pin strapping. The DAC7742 includes a high-speed output
amplifier with a maximum settling time of 5µs to ±0.003%
FSR for a 20V full-scale change and only consumes 100mW
(typical) of power.
ꢀ +10V INTERNAL REFERENCE
ꢀ UNIPOLAR OR BIPOLAR OPERATION
ꢀ SETTLING TIME: 5µs to ±0.003% FSR
ꢀ 16-BIT MONOTINICITY, –40°C TO +85°C
ꢀ ±10V, ±5V OR +10V CONFIGURABLE VOLTAGE
OUTPUT
ꢀ RESET TO MIN-SCALE OR MID-SCALE
ꢀ DOUBLE-BUFFERED DATA INPUT
ꢀ INPUT REGISTER DATA READBACK
ꢀ SMALL LQFP-48 PACKAGE
The DAC7742 features a standard 16-bit parallel interface with
double buffering to allow asynchronous updates of the analog
output, and data read-back to support data integrity verification
prior to an update. A user-programmable reset control allows
the DAC output to reset to min-scale (FFFFH) or mid-scale
(7FFFH) overriding the DAC register values. The DAC7742 is
available in an LQFP-48 package and three performance
grades specified to operate from –40°C to +85°C.
ꢀ SUPPORTS TRANSPARENT DATA INPUT
OPERATION
APPLICATIONS
ꢀ PROCESS CONTROL
ꢀ ATE PIN ELECTRONICS
ꢀ CLOSED-LOOP SERVO CONTROL
ꢀꢀMOTOR CONTROL
ꢀꢀDATA ACQUISITION SYSTEMS
REFOUT REFIN
VDD VSS VCC
REFADJ
VREF
ROFFSET
Buffer
RFB2
REFEN
CS
+10V
Reference
R/W
Control
Logic
RFB1
RST
RSTSEL
SJ
Input
Register
DAC
Register
I/O
Buffer
Data I/O
DAC
16
VOUT
AGND
DGND
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
VCC to VSS ........................................................................... –0.3V to +32V
V
V
CC to AGND ...................................................................... –0.3V to +16V
SS to AGND ...................................................................... –16V to +0.3V
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AGND to DGND ................................................................. –0.3V to +0.3V
REFIN to AGND ..................................................................... –9V to +11V
V
DD to DGND ................................................................. 0V to VCC – 1.4V
Digital Input Voltage to DGND ................................. –0.3V to VDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to VDD + 0.3V
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature .................................................................... +150°C
ESD damage can range from subtle performance degradation
tocompletedevicefailure. Precisionintegratedcircuitsmaybe
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
LINEARITY DIFFERENTIAL
SPECIFIED
ERROR
(LSB)
NONLINEARITY
(LSB)
PACKAGE
PACKAGE-LEAD DESIGNATOR(1)
TEMPERATURE
RANGE
ORDERING
NUMBER
PACKAGE
MARKING
TRANSPORT
MEDIA, QUANTITY
PRODUCT
DAC7742
±6
"
±4
"
LQFP-48
PT
"
–40°C to +85°C
DAC7742Y/250
DAC7742Y/2K
DAC7742Y
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
DAC7742
±4
"
±2
"
LQFP-48
PT
"
–40°C to +85°C
DAC7742YB/250
DAC7742YB/2K
DAC7742YB
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
DAC7742
±3
"
±1
"
LQFP-48
PT
"
–40°C to +85°C
DAC7742YC/250
DAC7742YC/2K
DAC7742YC
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
NOTE: (1) For the most current specifications and package information refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.
DAC7742Y
TYP
DAC7742YB
TYP
DAC7742YC
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ACCURACY
Linearity Error (INL)
±6
±5
±4
±4
±3
±2
±3
±2
±1
LSB
LSB
LSB
TA = 25°C
Differential Linearity Error (DNL)
Monotonicity
14
15
16
Bits
Offset Error
Offset Error Drift
Gain Error
±0.1
ꢀ
ꢀ
% of FSR
ppm/°C
% of FSR
% of FSR
ppm/°C
ppm/V
±2
ꢀ
ꢀ
With Internal REF
With External REF
With Internal REF
At Full-Scale
±0.4
±0.25
±0.25
±0.1
±0.2
ꢀ
Gain Error Drift
PSRR (VCC or VSS
±15
50
±10
ꢀ
±7
ꢀ
)
200
ꢀ
ꢀ
ANALOG OUTPUT(1)
Voltage Output(2)
+11.4/–4.75
+11.4/–11.4
+11.4/–6.4
0 to 10
±10
±5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Output Current
Output Impedance
Maximum Load Capacitance
Short-Circuit Current
Short-Circuit Duration
±5
ꢀ
ꢀ
ꢀ
mA
Ω
pF
mA
0.1
200
±15
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
AGND
Indefinite
REFERENCE
Reference Output
9.96
10
400
±15
10.04
9.975
ꢀ
ꢀ
±10
10.025
ꢀ
ꢀ
±7
ꢀ
V
Ω
REFOUT Impedance
REFOUT Voltage Drift
REFOUT Voltage Adjustment(3)
REFIN Input Range(4)
REFIN Input Current
REFADJ Input Range
ppm/°C
mV
V
nA
V
±25
4.75
ꢀ
ꢀ
ꢀ
ꢀ
VCC – 1.4
ꢀ
ꢀ
ꢀ
ꢀ
10
ꢀ
ꢀ
Absolute Max Value that
can be applied is VCC
0
10
ꢀ
ꢀ
ꢀ
ꢀ
REFADJ Input Impedance
50
1
ꢀ
ꢀ
ꢀ
ꢀ
kΩ
mA
Ω
V
V
REF Output Current
REF Impedance
–2
+2
ꢀ
ꢀ
DAC7742
2
SBAS256
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.
DAC7742Y
TYP
DAC7742YB
TYP
DAC7742YC
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
DYNAMIC PERFORMANCE
Settling Time to ±0.003%
20V Output Step
RL = 5kΩ, CL = 200pF,
with external REFOUT
to REFIN filter(5)
3
4
ꢀ
ꢀ
ꢀ
ꢀ
µs
Digital Feedthrough
Output Noise Voltage
2
100
ꢀ
ꢀ
ꢀ
ꢀ
nV-s
nV/√Hz
at 10kHz
DIGITAL INPUT
VIH
VIL
|IH| < 10µA
|IL| < 10µA
0.7 • VDD
ꢀ
ꢀ
ꢀ
ꢀ
V
V
0.3 • VDD
ꢀ
ꢀ
ꢀ
ꢀ
Input Coding
See Table III
ꢀ
ꢀ
ꢀ
ꢀ
DIGITAL OUTPUT
VOH
VOL
IOH = –0.8mA
IOL = 1.6mA
3.6
V
V
0.4
POWER SUPPLY
VDD
VCC
VSS
+4.75
+11.4
–15.75
–15.75
+5.0
+5.25
+15.75
–11.4
–4.75
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Bipolar Operation
Unipolar Operation
V
IDD
ICC
ISS
Power
100
4
–2.5
85
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µA
mA
mA
mW
mW
Unloaded
Unloaded
No Load, Ext. Reference
No Load, Int. Reference
6
ꢀ
ꢀ
–4
ꢀ
ꢀ
ꢀ
ꢀ
100
150
+85
ꢀ
ꢀ
ꢀ
ꢀ
TEMPERATURE RANGE
Specified Performance
–40
°C
ꢀ Specifications same as DAC7742Y.
NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output
voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REFIN must be equal
to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10).
DAC7742
3
SBAS256
www.ti.com
PIN CONFIGURATION
Top View
LQFP
48 47 46 45 44 43 42 41 40 39 38 37
NC
VSS
1
2
3
4
5
6
7
8
9
36 NC
35 DB15
34 DB14
33 DB13
32 DB12
31 DB11
30 DB10
29 DB9
28 DB8
27 DB7
26 TEST
25 NC
VCC
VREF
ROFFSET
AGND
AGND
RFB2
RFB1
DAC7742
SJ 10
VOUT 11
NC 12
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
28
29
30
31
32
33
34
35
36
37
38
39
DB8
DB9
Data Bit 8
1
2
3
4
NC
VSS
No Connection
Data Bit 9
Negative Analog Power Supply
Positive Analog Power Supply
DB10
DB11
DB12
DB13
DB14
DB15
NC
Data Bit 10
VCC
VREF
Data Bit 11
Buffered Output from REFIN; can be used to
drive external devices. Internally, this pin
directly drives the DAC's circuitry.
Data Bit 12
Data Bit 13
5
6
7
8
ROFFSET
AGND
AGND
RFB2
Offsetting Resistor
Data Bit 14
Analog Ground (Must be tied to analog ground.)
Analog Ground (Must be tied to analog ground.)
Data Bit 15 (MSB)
No Connection
Digital Ground
Digital Power Supply
Feedback Resistor 2, used to configure DAC
output range.
DGND
VDD
9
RFB1
Feedback Resistor 1, used to configure DAC
output range.
RST
VOUT reset; active LOW, depending on the state of
RSTSEL, the DAC register is either reset to mid-
scale or min-scale.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SJ
VOUT
NC
Summing Junction of the Output Amplifier
DAC Voltage Output
No Connection
No Connection
No Connection
No Connection
Data Bit 0 (LSB)
Data Bit 1
40
LDAC
DAC register load control, active LOW. Data is
loaded from the input register to the DAC register.
41
42
CS
Chip Select, Active LOW
NC
R/W
Enabled by CS, controls data read (HIGH) and
write (LOW) from or to the input register.
NC
NC
43
RSTSEL
REFEN
Reset Select; determines the action of RST. If
HIGH, RST will reset the DAC register to mid-
scale. If LOW, RST will reset the DAC register to
min-scale.
DB0
DB1
DB2
DB3
DB4
DB5
DB6
NC
Data Bit 2
Data Bit 3
44
Enables internal +10V reference (REFOUT), active
LOW.
Data Bit 4
45
46
REFOUT
Internal Reference Output
Data Bit 5
REFADJ
Internal Reference Trim. (Acts as a gain
adjustment input when the internal reference is
used.)
Data Bit 6
No Connection
No Connection
No Connection
Reserved, Connect to DGND
Data Bit 7
NC
47
48
REFIN
NC
Reference Input
No Connection
NC
TEST
DB7
DAC7742
4
SBAS256
www.ti.com
TIMING DIAGRAMS
DATA WRITE CYCLE
tWCS
CS
tLH
tWS
tWH
tLS
R/W
tDS
tDH
tDS
tDH
Data In
Data Valid
Data Valid
DB15-DB0
LDAC
VOUT
tLWD
tS
READ CYCLE
RESET TIMING
tSS
RSTSEL
tSH
tRCS
CS
tRDS
tRSS
RST
+FS
tRDH
R/W
tS
(RSTSEL = LOW)
tDZ
VOUT
Min-Scale
Data Valid
Data Out
DB15-DB0
–FS
tCSD
+FS
Mid-Scale
(RSTSEL = HIGH)
VOUT
–FS
TIMING CHARACTERISTICS
DAC7742Y
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
READ
tRCS
tRDS
tRDH
tDZ
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH After CS HIGH
CS HIGH to Data Bus High Impedance
CS LOW to Data Bus Valid
90
10
10
10
ns
ns
ns
ns
ns
70
100
tCSD
70
WRITE
tWS
R/W LOW to CS LOW
R/W LOW After CS HIGH
CS LOW for Write
10
10
25
20
30
0
ns
ns
ns
ns
ns
ns
ns
ns
tWH
tWCS
tLWD
tLS
tLH
tDS
LDAC LOW for Write
CS LOW to LDAC HIGH for Direct Update
CS LOW After LDAC HIGH
Data Valid to CS LOW
0
20
tDH
Data Valid After CS HIGH
RESET
tRSS
tSS
RST LOW
RSTSEL Valid Before RST LOW
RSTSEL Valid After RST HIGH
30
0
10
ns
ns
ns
tSH
ANALOG
tS
Voltage Output Settling Time
5
µs
DAC7742
5
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS
TA = +25°C (unless otherwise noted).
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
6
4
2
0
6
4
2
0
–2
–2
–4
–6
Bipolar Configuration: VOUT = –10V to +10V
–4
Bipolar Configuration: VOUT = –10V to +10V
TA = 25°C, Internal Reference Enabled
T
A = 85°C, Internal Reference Enabled
–6
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Digital Input Code
Digital Input Code
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
OFFSET ERROR vs TEMPERATURE
5
6
4
2
0
–2
–4
–6
4
3
2
Bipolar Configuration: VOUT = –10V to +10V
A = –40°C, Internal Reference Enabled
T
1
VOUT = –10V to +10V
0
VOUT = 0V to +10V
2.0
1.5
–1
1.0
–2
–3
–4
–5
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–40
–15
10
35
60
85
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Temperature (°C)
Digital Input Code
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
GAIN ERROR vs TEMPERATURE
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
0.15
Bipolar Configuration: VOUT = –10V to +10V
Internal Reference Enabled, TA = 25°C
Ext. Ref, Bipolar Mode:
OUT = –10V to +10V
V
0.10
0.05
0
Int. Ref, Bipolar Mode:
VOUT = –10V to +10V
Ext. Ref, Unipolar Mode:
Int. Ref, Unipolar Mode:
OUT = 0V to +10V
VOUT = 0V to +10V
V
–0.05
–40
–15
10
35
60
85
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Temperature (°C)
Digital Input Code
DAC7742
6
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
V
SS SUPPLY CURRENT vs DIGITAL INPUT CODE
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE
–1.50
–1.75
–2.00
–2.25
–2.50
–2.75
3.4
Bipolar Configuration: VOUT = –10V to +10V
External Reference, REFEN = 5V, TA = 25°C
3.3
3.2
3.1
3.0
2.9
2.8
Bipolar Configuration: VOUT = –10V to +10V
A = 25°C
T
2.7
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Digital Input Code
Digital Input Code
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
6
1000
TA = 25°C, Transition
Shown for One Data
Input (CS = 5V, R/W = 0)
5
4
800
600
400
200
0
3
ICC
2
Load Current Excluded, VCC = +15V, VSS = –15V
1
0
Bipolar VOUT Configuration: –10V to +10V
–1
–2
–3
–4
ISS
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
–40
–15
10
35
60
85
VLOGIC (V)
Temperature (°C)
HISTOGRAM OF VSS CURRENT CONSUMPTION
HISTOGRAM OF VCC CURRENT CONSUMPTION
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Bipolar Output Configuration
Internal Reference Enabled
Code = AAAAH
Bipolar Output Configuration
Internal Reference Enabled
Code = AAAAH
3.000
3.500
4.000
ICC (mA)
4.500
5.000
–3.50
–3.00
–2.50
–2.00
–1.50
I
SS (mA)
DAC7742
7
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at VOUT
(Measured at VOUT
)
)
10
0
10
0
Bipolar Configuration: ±10V VOUT
Code 7FFFH
Bipolar Configuration: ±10V VOUT, Code 0000H
–VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
–VSS, VCC = 15V + 1Vp-p
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
V
DD = 5V + 0.5Vp-p
VSS
VCC
VSS
VCC
VDD
VDD
0.1k
1k
10k
100k
1M
10M
0.01k
0.1k
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
INTERNAL REFERENCE START-UP
10.015
10.010
10.005
10.000
9.995
15V
0V
10V
0V
9.990
9.985
–40
–15
10
35
60
85
Time (2ms/div)
Temperature (°C)
OUTPUT VOLTAGE vs RLOAD
Source
REFOUT VOLTAGE vs LOAD
12
8
11.0
10.5
10.0
9.5
Loaded to VCC
VCC = +15V
4
0
–4
–8
–12
Sink
9.0
Loaded to AGND
10
8.5
0.0
0.1
1.0
10.0
100.0
1
100
1k
RLOAD (kΩ)
REFOUT LOAD (kΩ)
DAC7742
8
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY
OUTPUT NOISE vs FREQUENCY
(Measured at REFOUT
)
900
800
700
600
500
400
300
200
100
0
10
0
Unipolar Configuration, Internal Reference Enabled
Internal Reference Enabled
–VSS, VCC = 15V + 1Vp-p,
VDD = 5V + 0.5Vp-p
–10
–20
–30
–40
–50
–60
–70
–80
VCC
Code 0000H
VDD
VSS
Code FFFFH
0.01k
0.1k
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
OUTPUT NOISE vs FREQUENCY
BROADBAND NOISE
800
700
600
500
400
300
200
100
0
Bipolar Configuration: ±10V, Internal Reference Enabled
Code FFFFH
Code 0000H
Internal Reference Enabled
Filtered with 1.6Hz Low-Pass
Code 0000H, Bipolar ±10V Configuration
10kHz Measurement BW
Code 7FFFH
0.01k
0.1k
1k
10k
100k
1M
10M
Time (100µs/div)
Frequency (Hz)
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Time (2µs/div)
Time (2µs/div)
DAC7742
9
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).
BIPOLAR FULL-SCALE SETTLING TIME
UNIPOLAR FULL-SCALE SETTLING TIME
Time (2µs/div)
Time (2µs/div)
MID-SCALE GLITCH
MID-SCALE GLITCH
Time (1µs/div)
Time (1µs/div)
DIGITAL FEEDTHROUGH
Time (200ns/div)
DAC7742
10
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The digital input is a parallel word made up of the 16-bit DAC
code and is loaded into the DAC register using the LDAC
input pin. The converter can be powered from ±12V to ±15V
dual analog supplies and a +5V logic supply. The device
offers a reset function, which immediately sets the DAC
output voltage and DAC register to min-scale (code FFFFH)
or mid-scale (code 7FFFH). The data I/O and reset functions
are discussed in more detail in the following sections.
THEORY OF OPERATION
The DAC7742 is a voltage output, 16-bit DAC with a +10V built-
in internal reference. The architecture is an R-2R ladder con-
figuration with the three MSBs segmented, followed by an
operational amplifier that serves as a buffer, as shown in Figure
1. The output buffer is designed to allow user-configurable
output adjustments giving the DAC7742 output voltage ranges
of 0V to +10V, –5V to +5V, or –10V to +10V. Please refer to
Figures 2, 3, and 4 for pin configuration information.
ROFFSET
RFB2
REFIN
VREF
REFADJ
REFOUT
R/4
R/4
Buffer
RFB1
+10V Internal
Reference
R/2
R/2
R/4
SJ
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
AGND
FIGURE 1. DAC7742 Architecture.
Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7742
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(0V to +10V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 2. Basic Operation: VOUT = 0V to +10V.
DAC7742
11
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Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7742
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(–5V to +5V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 3. Basic Operation: VOUT = –5V to +5V.
Data Bus
VDD
0.1µF
1µF
DGND
VDD
NC
NC
RST
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
LDAC
CS
Control Bus
R/W
Data Bus
DAC7742
RSTSEL
REFEN
REFOUT
REFADJ
REFIN
NC
NC
NC
VSS
(–10V to +10V)
0.1µF
1µF
VCC
0.1µF
1µF
FIGURE 4. Basic Operation: VOUT = –10V to +10V.
DAC7742
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ANALOG OUTPUTS
at the VREF pin. In this configuration, VREF is used to setup the
DAC7742 output amplifier into one of three voltage output
modes as discussed earlier. VREF can also be used to drive
other system components requiring an external reference.
The output amplifier can swing to within 1.4V of the supply
rails, specified over the –40°C to +85°C temperature range.
This allows for a ±10V DAC voltage output operation from
±12V supplies with a typical 5% tolerance.
The internal reference of the DAC7742 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REFIN, can be any
voltage between 4.75V (or VSS + 14V, whichever is greater)
and VCC – 1.4V.
When the DAC7742 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
“Electrical Characteristics” table for more information.
The minimum and maximum voltage output values are de-
pendent upon the output configuration implemented and
reference voltage applied to the DAC7742. Please note that
VSS (the negative power supply) must be in the range of
–4.75V to –15.75V for unipolar operation. The voltage on VSS
sets several bias points within the converter and is required
in all modes of operation. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not ensured.
DIGITAL INTERFACE
Table III shows the data format for the DAC7742 and
Table II illustrates the basic control logic of the device. The
interface consists of a chip select input (CS), read/write
control input (R/W), data inputs (DB0-DB15), and a load DAC
input (LDAC). An asynchronous reset input (RST) which is
active LOW, is provided to simplify start-up conditions, peri-
odic resets, or emergency resets to a known state, depend-
ing on the status of the reset select (RSTSEL) signal. The
DAC code is provided via a 16-bit parallel interface, as
shown in Table II. The input word makes up the DAC code
to be loaded into the data input register of the device. The
data is latched into the input register on rising CS and is
loaded into the DAC register upon reception of a LOW level
on the LDAC input. This action updates the analog output,
Supply sequence is important in establishing correct startup
of the DAC.
The digital supply (VDD) needs to establish correct bias
conditions before the analog supplies (VCC, VSS) are brought
up. If the digital supply cannot be brought up first, it must
come up before either analog supply (VCC or VSS), with the
preferred sequence of: VSS (device substrate), VDD, and then
VOUT, to the desired value. LDAC inputs of multiple DAC7742s
VCC
.
can be connected when a synchronized update of numerous
DAC outputs is desired. Please refer to the timing section for
more detailed data I/O information.
REFERENCE INPUTS
The DAC7742 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7742 (as shown in Table I) and
the REFOUT pin must be connected to REFIN. This is the input
to the on-chip reference buffer. The buffer’s output is provided
ANALOG OUTPUT
DIGITAL INPUT
Unipolar Configuration
Bipolar Configuration
Complementary Straight Binary Complementary Offset Binary
0xFFFF
0xFFFE
:
Zero (0V)
–Full-Scale (–VREF or –VREF/2)
Zero + 1LSB
–Full-Scale + 1LSB
:
1/2 Full-Scale
1/2 Full-Scale + 1LSB
:
:
Bipolar Zero
Bipolar Zero + 1LSB
:
0x7FFF
0x7FFE
:
REFEN
ACTION
1
Internal Reference disabled;
REFOUT = High Impedance
0x0000
Full-Scale (VREF – 1LSB) +Full-Scale (+VREF – 1LSB
or +VREF/2 – 1LSB)
0
Internal Reference enabled;
REFOUT = +10V
TABLE III. DAC7742 Data Format.
TABLE I. REFEN Action.
CONTROL STATUS
COMMAND
R/W
CS
RST
RSTSEL
LDAC
Input Register
DAC Register
Mode
Write Data to Input Register
L
L
H
H
X
X
H
L
Write
Hold
Hold
X
H
Write
Update DAC Register with Data from Input
Register
L
H
X
X
L
L
H
H
H
L
X
X
X
L
L
H, L
H
Transparent
Read
Write
Hold
Write DAC Register Directly from Data Bus
Read Data in Input Register
No Change
H
X
Hold
Hold
X
Reset to Min-Scale
Reset to Min-Scale
Reset to Input and DAC Register (FFFFH)
Min-Scale
X
X
L
H
X
Reset to Mid-Scale
Reset to Mid-Scale
Reset to Input and DAC Register (7FFFH)
Mid-Scale
TABLE II. DAC7742 Logic Truth Table.
DAC7742
13
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DAC RESET
(+VREF
)
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a LOW signal
on RST. Once RST is LOW, the DAC output will begin settling
to the mid-scale or min-scale code depending on the state of
the RSTSEL input. A HIGH value on RSTSEL will cause VOUT
to reset to the mid-scale code (7FFFH) and a LOW value will
reset VOUT to min-scale (FFFFH). A change in the state of the
RSTSEL input while RST is LOW will cause a corresponding
change in the reset command selected internally and conse-
quently change the output value of VOUT of the DAC. Note that
a valid reset signal also resets the input register of the DAC to
the value specified by the state of RSTSEL.
+ Full-Scale
Gain Adjust
Rotates
the Line
1LSB
Input =
FFFFH
Input =
0000 H
Zero Scale
(AGND)
Digital Input
Offset Adjust Translates the Line
FIGURE 5. Relationship of Offset and Gain Adjustments for
GAIN AND OFFSET CALIBRATION
VOUT = 0V to +10V Output Configuration.
The architecture of the DAC7742 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7742
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 5 and 6 illustrate the
relationship of offset and gain adjustments for the DAC7742
in a unipolar configuration and in a bipolar configuration,
(+VREF or +VREF/2)
+ Full-
Scale
1LSB
Input =
FFFFH
Gain
Adjust
Rotates
the Line
respectively.
Offset
Adjust
Translates
the Line
When calibrating the DAC’s output, offset should be adjusted
first to avoid 1st-order interaction of adjustments. In unipolar
mode, the DAC7742’s offset is adjusted from code FFFFH
and for either bipolar mode, offset adjustments are made at
code 7FFFH. Gain adjustment can then be made at code
0000H for each configuration, where the output of the DAC
should be at +10V for the 0V to +10V – 1LSB or ±10V output
range and +5V – 1LSB for the ±5V output range. Figure 7
shows the generalized external offset and gain adjustment
Input =
0000 H
Input = 7FFFH
– Full-Scale
(–VREF OR –VREF/2)
Digital Input
FIGURE 6. Relationship of Offset and Gain Adjustments for
OUT =–10Vto+10VOutputConfiguration.(Same
V
circuitry using potentiometers.
Theory Applies for VOUT = –5V to +5V.)
15 REFOUT
16 REFADJ
Optional Gain
17 REFIN
Adjust
18 NC
RPOT1
ISJ
R1
(Other Connections Omitted
for Clarity)
RS
RPOT2
+
VOADJ
–
Optional Offset
Adjust
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
DAC7742
14
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REFADJ can be driven by a low impedance voltage source
such as a unipolar, 0V to +10V DAC or a potentiometer (less
than 100kΩ), see Figure 7. Since the input impedance of
REFADJ is typically 50kΩ, the smaller the resistance of the
potentiometer, the more linear the adjustment will be. A 10kΩ
potentiometer is suggested if linearity of the reference adjust-
ment is of concern.
OFFSET ADJUSTMENT
Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7742. The
voltage at SJ, or VSJ, is dependent on the output configura-
tion of the DAC7742. Table IV shows the required pin
strapping for a given configuration and the nominal values of
VSJ for each output range.
(1)
REFERENCE
OUTPUT
PIN STRAPPING
VSJ
OFFSET ADJUST RANGE
50
CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2
–10V to +10V VOUT
typ
Internal
Reference
0V to +10V
–10V to +10V
–5V to +5V
to VREF to VOUT to VOUT
NC NC
+5V
Configuration
to VOUT +3.333V
to AGND to VOUT to VOUT +2.5V
min (75% of typ)
25
External
0V to VREF
to VREF to VOUT to VOUT VREF/2
Reference
–VREF to VREF
NC
NC
to VOUT VREF/3
typ
–VREF/2 to VREF/2 to AGND to VOUT to VOUT VREF/4
0
NOTE: (1) Voltage measured at VSJ for a given configuration.
min (75% of typ)
0V to 10V and –5V to +5V
TABLE IV. Nominal VSJ vs VOUT and Reference Configuration.
–25
–50
VOUT Configuration
The current level required to adjust the DAC7742’s offset can
be created by using a potentiometer divider, see Figure 7.
Another alternative is to use a unipolar DAC in order to apply
a voltage, VOADJ, to the resistor RS. A ±1.2µA current range
applied to SJ will ensure offset adjustment coverage of the
±0.1% maximum offset specification of the DAC7742.
–2
–1
0
1
2
ISJ (µA)
FIGURE 8. Offset Adjustment Transfer Characteristic.
When in a unipolar configuration (VSJ = 5V), only a single
resistor, RS, is needed for symmetrical offset adjustment with
a 0V to 10V VOADJ range. When in one of the two bipolar
configurations, VSJ is either +3.333v (±10V range) or +2.5V
(±5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer
When the DAC7742’s internal reference is not used, gain
adjustments can be made via trimming the external refer-
ence applied to the DAC at REFIN. This can be accomplished
through using a potentiometer, unipolar DAC, or other means
of precision voltage adjustment to control the voltage pre-
sented to the DAC7742 by the external reference. Figure 9
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.
to Figure 7 for component configuration.
OUTPUT
CONFIGURATION
RPOT2
R1
RS
ISJ
RANGE
NOMINAL
OFFSET
ADJUSTMENT
REFOUT ADJUST RANGE
40
0V to +10V
–10V to +10V
–5V to +5V
10k
10k
10k
0
5k
10k
2.5M
1.5M
1.5M
±2µA
±2.2µA
±1.7µA
±25mV
±55mV
±21mV
Typical REFOUT
30
Adjustment Range
TABLE V. Recommended External Component Values for
Symmetrical Offset Adjustment (VREF = 10V).
20
10
Minimum REFOUT
0
Adjustment Range
Figure 8 illustrates the typical and minimum offset adjustment
ranges provided by forcing a current at SJ for a given output
voltage configuration.
–10
–20
–30
–40
GAIN ADJUSTMENT
0
2
4
6
8
10
When using the internal reference of the DAC7742, gain
adjustment is performed by adjusting the device’s internal
reference voltage via the reference adjust pin, REFADJ.
The effect of a reference voltage change on the gain of the
DAC output can be seen in the generic equation (for
unipolar configuration):
REFADJ (V)
FIGURE 9. Internal Reference Adjustment Transfer Charac-
teristic.
VOLTAGE AT REFADJ
REFOUT VOLTAGE
65535 – N
(
•
)
REFADJ = 0V
REFADJ = 5V or NC(1)
REFADJ = 10V
10V + 25mV (min)
10V
10V – 25mV (max)
VOUT = VREFIN
65536
Where N is represented in decimal format and ranges from
0 to 65535.
NOTE: "NC" is "Not Connected".
TABLE VI. Minimum Internal Reference Adjustment Range.
DAC7742
15
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NOISE PERFORMANCE
LAYOUT
Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the
DAC7742. Figure 10 shows a typical internal reference filter
schematic. A low-pass filter applied between the REFOUT and
REFIN pins can increase noise immunity at the DAC and
output amplifier. The REFOUT pin can source a maximum of
50µA so care should be taken in order to avoid overloading
A precision analog component requires careful layout, adequate
bypassing, and clean, well-regulated power supplies. The
DAC7742 offers separate digital and analog supplies, as it will
often be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital
logic present in the design and the higher the switching speed,
the more important it will become to separate the analog and
digital ground and supply planes at the device.
the internal reference output.
Since the DAC7742 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
they were connected at the power entry point of the system.
43 RSTSEL
44 REFEN
The voltages applied to VCC and VSS should be well regulated
and low noise. Switching power supplies and DC/DC con-
verters will often have high-frequency glitches or spikes
riding on the output voltage. In addition, digital components
can create similar high-frequency spikes as their internal
logic switches states. This noise can easily couple into the
DAC output voltage through various paths between the
power connections and analog output.
100kΩ
45 REFOUT
1µF
46 REFADJ
47 REFIN
48 NC
(Other Connections
Omitted for Clarity)
In addition, a 1µF to 10µF bypass capacitor in parallel with a
0.1µF bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may
be required, such as a 100µF electrolytic capacitor or even
a "Pi" filter made up of inductors and capacitors–all designed
to essentially low-pass filter the analog supplies, removing
any high frequency noise components.
FIGURE 10. Internal Reference Filter.
DAC7742
16
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PACKAGE DRAWING
PT (S-PQFP-G48)
MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
05–75
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
DAC7742
17
SBAS256
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
Drawing
DAC7742Y/250
DAC7742Y/2K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PT
48
48
48
48
48
48
250
2000
250
None
None
None
None
None
None
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
PT
DAC7742YB/250
DAC7742YB/2K
DAC7742YC/250
DAC7742YC/2K
PT
PT
2000
250
PT
PT
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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16-Bit, Single Channel, Parallel Interface with Internal Reference 48-LQFP -40 to 85
TI
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