DAC8043 [BB]
CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER; CMOS 12位串行输入乘法数位类比转换器
| 型号： | DAC8043 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总7页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC8043
DAC8043
CMOS 12-Bit Serial Input Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 12-BIT ACCURACY IN 8-PIN SOIC
● FAST 3-WIRE SERIAL INTERFACE
● LOW INL AND DNL: ±1/2 LSB max
● GAIN ACCURACY TO ±1LSB max
● LOW GAIN TEMPCO: 5ppm/°C max
● OPERATES WITH +5V SUPPLY
● TTL/CMOS COMPATIBLE
● AUTOMATIC CALIBRATION
● MOTION CONTROL
● MICROPROCESSOR CONTROL SYSTEMS
● PROGRAMMABLE AMPLIFIER/
ATTENUATORS
● DIGITALLY CONTROLLED FILTERS
● ESD PROTECTED
DESCRIPTION
The DAC8043 is a 12-bit current output multiplying
digital-to-analog converter (DAC) that is packaged in a
space-saving, surface-mount 8-pin SOIC. Its 3-wire se-
rial interface saves additional circuit board space which
results in low power dissipation. When used with micro-
processors having a serial port, the DAC8043 minimizes
the digital noise feedthrough from its input to output.
The serial port can be used as a dedicated analog bus and
kept inactive while the DAC8043 is in use. Serial inter-
facing reduces the complexity of opto or transformer
isolation applications.
RFB
2
RFB
12-Bit
D/A
Converter
1
5
3
VREF
IOUT
12
12-Bit
DAC Register
LD
The DAC8043 contains a 12-bit serial-in, parallel-out
shift register, a 12-bit DAC register, a 12-bit CMOS
DAC, and control logic. Serial input (SRI) data is clocked
into the input register on the rising edge of the clock
(CLK) pulse. When the new data word had been clocked
in, it is loaded into the DAC register by taking the LD
input low. Data in the DAC register is converted to an
output current by the D/A converter.
8
4
VDD
12
GND
7
6
CLK
SRI
12-Bit Input
Shift Register
The DAC8043 operates from a single +5V power supply
which makes the DAC8043 an ideal low power, small
size, high performance solution for several applications.
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1993 Burr-Brown Corporation
PDS-1197B
Printed in U.S.A. March, 1998
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
DAC8043U
TYP
DAC8043UC
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
12
Bits
LSB
LSB
LSB
LSB
ppm/°C
%/%
nA
Nonlinearity(1)
INL
DNL
FSE
±1
±1
±2
±2
±5
±1/2
±1/2
±1
±2
±5
Differential Nonlinearity(2)
Gain Error(3)
TA = +25°C
TA = Full Temp Range
Gain Tempco(5)
Power Supply Rejection Ratio
Output Leakage Current(4)
TCFSE
PSRR
ILKG
∆VDD = ±5%
TA = +25°C
±0.0006
±0.002
±5
±0.0006
±0.002
±5
TA = Full Temp Range
TA = +25°C
TA = Full Temp Range
±100
0.03
0.60
15
±25
0.03
0.15
15
nA
Zero Scale Error(7, 12)
Input Resistance(8)
IZSE
RIN
LSB
LSB
kΩ
7
11
7
11
AC PERFORMANCE
Output Current Settling Time(5, 6)
Digital-to-Analog Glitch
Energy(5, 10)
tS
TA = +25°C
0.25
2
1
20
0.25
2
1
20
µs
nVs
V
REF = 0V
Q
IOUT = Load = 100Ω
CEXT = 13pF
DAC Register Loaded Alternately with all 0s and all 1s
Feedthrough Error(5, 11)
FT
VREF = 20Vp-p at f = 10kHz
0.7
1
0.7
1
mVp-p
(VREF to IOUT
)
Digital Input = 0000 0000 0000
T
A = +25°C
Total Harmonic Distortion(5)
THD
eN
VREF = 6VRMS at 1kHz
DAC Register Loaded with all 1s
10Hz to 100kHz
–85
–85
dB
Output Noise Voltage Density(5, 13)
17
17
nV/√Hz
Between RFB and IOUT
DIGITAL INPUTS
Digital Input High
Digital Input Low
Input Leakage Current(9)
Input Capacitance(5, 11)
VIH
VIL
IIL
2.4
2.4
V
V
µA
pF
0.8
±1
8
0.8
±1
8
VIN = 0V to +5V
VIN = 0V
CIN
ANALOG OUTPUTS
Output Capacitance(5)
COUT
Digital Inputs = VIH
Digital Inputs = VIL
110
80
110
80
pF
pF
TIMING CHARACTERISTICS(5, 14)
Data Setup Time
Data Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Load Pulse Width
tDS
tDH
tCH
tCL
tLD
TA = Full Temperature Range
TA = Full Temperature Range
TA = Full Temperature Range
TA = Full Temperature Range
TA = Full Temperature Range
40
80
90
120
120
40
80
90
120
120
ns
ns
ns
ns
ns
LSB Clock into Input Register
to Load DAC Register Time
tASB
TA = Full Temperature Range
0
0
ns
POWER SUPPLY
Supply Voltage
Supply Current
VDD
IDD
4.75
5
5.25
500
100
4.75
5
5.25
500
100
V
µA
µA
Digital Inputs = VIH or VIL
Digital Inputs = 0V or VDD
NOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to IOUT; All
digital inputs = 0V. (5) Guaranteed by design and not tested. (6) IOUT Load = 100Ω, CEXT = 13pF, digital input = 0V to VDD or VDD to 0V. Extrapolated to 1/2 LSB:
t
S = propagation delay (tPD) + 9τ where τ = measured time constant of the final RC decay. (7) VREF = +10V, all digital inputs = 0V. (8) Absolute temperature coefficient
is less than ±50ppm/°C. (9) Digital inputs are CMOS gates: IIN is typically 1nA at +25°C. (10) VREF = 0V, all digital inputs = 0V to VDD or VDD to 0V. (11) All digital
inputs = 0V. (12) Calculated from worst case RREF: IZSE (in LSBs) = (RREF X ILKG X 4096)/VREF. (13) Calculations from en = √4K TRB where: K = Boltzmann constant,
J/°K, R = resistance, Ω. T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at VIN = 0V or VDD
.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC8043
WAFER TEST LIMITS
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = +25°C.
DAC8043
UNITS
PARAMETER
SYMBOL
CONDITIONS
LIMIT
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Gain Error
N
INL
DNL
GFSE
PSRR
ILKG
12
±1
±1
±2
±0.002
±5
Bits min
LSB max
LSB max
LSB max
%/% max
nA max
Using Internal Feedback Resistor
∆VDD = ±5%
Power Supply Rejection Ratio
Output Leakage Current (IOUT
)
Digital Inputs = VIL
REFERENCE INPUT
Input Resistance
RIN
7/15
kΩ min/max
DIGITAL INPUTS
Digital Input HIGH
Digital Input LOW
Input Leakage Current
VIH
VIL
IIL
2.4
0.8
±1
V min
V max
µA max
VIN = 0V to VDD
POWER SUPPLY
Supply Current
IDD
Digital Inputs = VIH or VIL
Digital Inputs = 0V to VDD
500
100
µA max
µA max
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
VDD to GND .................................................................................. 0V, +7V
VREF to GND ...................................................................................... ±25V
VRFB to GND ...................................................................................... ±25V
Digital Input Voltage Range ................................................. –0.3V to VDD
Output Voltage (Pin 3)......................................................... –0.3 V to VDD
Operating Temperature Range
AD ........................................................................................0°C to +70°C
U, UC ............................................................................... –40°C to +85°C
Junction Temperature .................................................................... +150°C
Storage Temperature.................................................... –65°C to + 150°C
Lead Temperature (soldering, 10s) .............................................. +300° C
Top View
8-Pin SOIC
VREF
1
2
3
4
8
7
6
5
VDD
RFB
IOUT
CLK
SRI
LD
GND
θJA
.......................................................................................................................... +100°C/W
θJC ........................................................................................... +42°C/W
CAUTION: 1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF (Pin 1) and RFB (Pin 2). 2. The digital
control inputs are ESD protected: however, permanent damage may occur on
unprotected units from high-energy electrostatic fields. Keep units in conduc-
tive foam at all times until ready to use. 3. Use proper anti-static handling
procedures. 4. Absolute Maximum Ratings apply to both packaged devices.
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
TEMPERATURE
RANGE
PRODUCT
INL
PACKAGE
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
DAC8043U
DAC8043UC 1/2LSB
1LSB
–40°C to +85°C
–40°C to +85°C
8-pin SOIC
8-pin SOIC
182
182
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Digital Inputs: All digital inputs of the DAC8043 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500Ω)
applied to each digital input.
Analog Pins: Each analog pin has been tested to Burr-
Brown’s analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500Ω) ap-
plied to each pin. VREF and RFB show some sensitivity.
®
3
DAC8043
WRITE CYCLE TIMING DIAGRAM
Bit 1
Bit 12
LSB
SRI
Bit 2
Bit 11
11
MSB(1)
tDH
tDS
1
tCL
tCH
2
CLK INPUT
tASB
Load Serial Data
Into Input Register
tLD
LD
Load Input Register's
Data Into DAC Register
NOTE: (1) Data loaded MSB first.
®
4
DAC8043
TYPICAL PERFORMANCE CURVES
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
LINEARITY ERROR vs REFERENCE VOLTAGE
GAIN vs FREQUENCY
0
–20
0.5
0.25
0
Digital Input
= 1111 1111 1111
–40
–60
Digital Input
= 0000 0000 0000
–80
–0.25
–0.5
VDD = +5V
VREF = 100mV
TA = +25°C
–100
–120
1k
10k
100k
Frequency (Hz)
1M
10M
2
4
6
8
10
VREF (V)
TOTAL HARMONIC DISTORTION vs FREQUENCY
(Multiplying Mode)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
VDD = +5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–20
VDD = +5V
VIN = 6Vrms
TA = +25°C
–40
–60
–80
–100
–120
10
100
1000
Frequency (Hz)
10000
0
1
2
3
4
VIN (V)
LINEARITY ERROR vs DIGITAL CODE
DNL ERROR vs REFERENCE VOLTAGE
1
0.75
0.5
0.5
0.25
0
TA = +25°C
REF = +10V
V
0.25
0
–0.25
–0.5
–0.75
–1
–0.25
–0.5
2
4
6
8
10
0
1024
2048
3072
4096
Digital Input Code (Decimal)
VREF (V)
®
5
DAC8043
tains a constant current in each leg of the ladder regardless of
the input code. The input resistance at VREF is therefore
constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to ±20V.
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB, compensates for the temperature drift of the ON resis-
tance of the ladder switches.
Figure 2 shows an equivalent circuit for the DAC. COUT is the
output capacitance due to the N-channel switches and varies
from about 80pF to 110pF with digital input code. The current
source ILKG is the combination of surface and junction leak-
ages to the substrate. ILKG approximately doubles every 10°C.
RO is the equivalent output resistance of the D/A and it varies
with input code.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
GAIN ERROR
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC8043 is –(4095/4096)VREF. Gain error may be
adjusted to zero using external trims as shown in Figure 4.
R
RFB
VREF
IOUT
ILKG
DIN VREF
COUT
RO
x
R
4096
R
OUTPUT LEAKAGE CURRENT
GND
The current which appears at IOUT with the DAC loaded with
all zeros.
FIGURE 2. Equivalent Circuit for the DAC.
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT to GND.
INSTALLATION
ESD PROTECTION
FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from VREF to
IOUT with the DAC loaded with all zeros.
All digital inputs of the DAC8043 incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
+0.01% of final value for a full scale step.
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
POWER SUPPLY CONNECTIONS
The DAC8043 is designed to operate on VDD = +5V ±5%.
For optimum performance and noise rejection, power supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recom-
mended) should be located close to the D/A. Output op amp
analog common (+ input) should be connected as near to the
GND pins of the DAC8043 as possible.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of a DAC8043. The
current from the VREF pin is switched between IOUT and GND
by 12 single-pole double-throw CMOS switches. This main-
VREF
R
R
R
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the VREF lines and the IOUT lines. Coupling from any
of the digital control or data lines might degrade the glitch
performance. Solder the DAC8043 directly into the PC board
without a socket. Sockets add parasitic capacitance (which
can degrade AC performance).
RFB
R
2R
2R
2R
2R
2R
IOUT
GND
Bit 1
(MSB)
Bit 2
Bit 3
Bit 12
(LSB)
FIGURE 1. Simplified Circuit Diagram for the DAC.
®
6
DAC8043
AMPLIFIER OFFSET VOLTAGE
versus digital input code are listed in Table I. The operational
amplifiers used in this circuit can be single amplifiers such as
the OPA602, or a dual amplifier such as the OPA2107. C1
provides phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
The output amplifier used with the DAC8043 should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multi-
plied by the “noise gain” of the circuit. This “noise gain” is
equal to (RF/RO + 1) where RO is the output impedance of the
D/A IOUT terminal and RF is the feedback network imped-
ance. The nonlinearity occurs due to the output impedance
varying with code. If the 0 code case is excluded (where
RO = infinity), the RO will vary from R to 3R providing a
“noise gain” variation between 4/3 and 2. In addition, the
variation of RO is nonlinear with code, and the largest steps
in RO occur at major code transitions where the worst
differential nonlinearity is also likely to be experienced. The
nonlinearity seen at the amplifier output is
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistor R2 induces
a positive gain error greater than worst-case initial negative
gain error. Trim resistor R1 provides a variable negative gain
error and have sufficient trim range to correct for the worst-
case initial positive gain error plus the error produced by R2.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC8043 in a typical bipolar (four-
quadrant) multiplying configuration. The analog output val-
ues versus digital input code are listed in Table II.
2VOS – 4VOS/3 = 2VOS/3.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602 or a dual amplifier such as
the OPA2107. C1 provides phase compensation to minimize
settling time and overshoot when using a high speed opera-
tional amplifier. The bipolar offset resistors R1–R2 should
be ratio-matched to 0.01% to ensure the specified gain error
performance.
Thus, to maintain good nonlinearity the op amp offset should
be much less than 1/2LSB.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC8043 in a typical unipolar (two-quad-
rant) multiplying configuration. The analog output values
DATA INPUT
↓ LSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
ANALOG OUTPUT
DATA INPUT
↓ LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
ANALOG OUTPUT
MSB ↓
MSB ↓
+VREF (2047/2048)
+VREF (1/2048)
0 Volts
–VREF (1/2048)
–VREF (2048/2048)
–VREF (4095/4096)
–VREF (2048/4096) = –1/2VREF
–VREF (1/4096)
0 Volts
TABLE I. Unipolar Output Code.
TABLE II. Bipolar Output Code.
VDD
+5V
VIN
VDDVREF
+5V
R1
100Ω
VREF
+
CD
1µF
+
CD
1µF
RFB
R2
RFB
C1
C1 10pF
–
A1
+
IOUT
10pF
47Ω
–
A1
+
IOUT
DAC
GND
VOUT
DAC
GND
VOUT
DAC8043
DAC8043
A1 OPA602 or 1/2 OPA2107.
A1 OPA602 or 1/2 OPA2107.
FIGURE 3. Unipolar Configuration.
FIGURE 4. Unipolar Configuration with Gain Trim.
+5V
R1
VDD
20kΩ
VREF
R2
20kΩ
–
+
CD
1µF
VOUT
A2
R3
+
10kΩ
RFB
IOUT
C1
10pF
–
+
A1
DAC
GND
A1–A2, OPA602 or 1/2 OPA2107.
DAC8043
FIGURE 5. Bipolar Configuration.
®
7
DAC8043
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