DAC904U [BB]
14-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER; 14位， 165MSPS数位类比转换器
| 型号： | DAC904U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 14-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总16页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC904
DAC904
For most current data sheet and other product
information, visit www.burr-brown.com
TM
14-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
FEATURES
● COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
● SINGLE +5V OR +3V OPERATION
●
HIGH SFDR: 20MHz Output at 100MSPS: 64dBc
● LOW GLITCH: 3pV-s
Cable Modems
● LOW POWER: 170mW at +5V
● WAVEFORM GENERATION
● INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
● MEDICAL/ULTRASOUND
● HIGH-SPEED INSTRUMENTATION AND
CONTROL
● VIDEO, DIGITAL TV
For noncontinuous operation of the DAC904, a power-down
mode results in only 45mW of standby power.
DESCRIPTION
The DAC904 is a high-speed, digital-to-analog converter (DAC)
offering a 14-bit resolution option within the SpeedPlus family
of high-performance converters. Featuring pin compatibility
among family members, the DAC908, DAC900, and DAC902
provide a component selection option to an 8-, 10-, and 12-bit
resolution, respectively. All models within this family of D/A
converters support update rates in excess of 165MSPS with
excellent dynamic performance, and are especially suited to
fulfill the demands of a variety of applications.
The DAC904 comes with an integrated 1.24V bandgap refer-
ence and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families
can be interfaced to the DAC904.
The reference structure of the DAC904 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2mA to 20mA, with one external resistor, while
maintaining the specified dynamic performance.
The advanced segmentation architecture of the DAC904 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communica-
tion systems.
The DAC904 is available in SO-28 and TSSOP-28 packages.
+VA
BW
+VD
DAC904
The DAC904 has a high impedance (200kΩ) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential, or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
IOUT
IOUT
BYP
LSB
Switches
FSA
Current
Sources
REFIN
Segmented
Switches
INT/EXT
Utilizing a small geometry CMOS process, the monolithic
DAC904 can be operated on a wide, single-supply range of
+2.7V to +5.5V. Its low power consumption allows for use in
portable and battery operated systems. Further optimization can
be realized by lowering the output current with the adjustable
full-scale option.
Latches
PD
+1.24V Ref.
14-Bit Data Input
D13...D0
AGND
CLK
DGND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
©1999 Burr-Brown Corporation
Printed in U.S.A. May, 2000
PDS-1448B
SPECIFICATIONS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
Output Update Rate (fCLOCK
Output Update Rate
14
200
165
Bits
MSPS
MSPS
°C
)
4.5V to 5.5V
2.7V to 3.3V
Ambient, TA
165
125
–40
Full Specified Temperature Range, Operating
+85
STATIC ACCURACY(1)
TA = +25°C
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
fCLOCK = 25MSPS, fOUT = 1.0MHz
±2.5
±3.0
LSB
LSB
DYNAMIC PERFORMANCE
TA = +25°C
Spurious Free Dynamic Range (SFDR)
fOUT = 1.0MHz, fCLOCK = 25MSPS
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 25.3MHz, fCLOCK = 125MSPS
fOUT = 41.5MHz, fCLOCK = 125MSPS
fOUT = 27.4MHz, fCLOCK = 165MSPS
fOUT = 54.8MHz, fCLOCK = 165MSPS
Spurious Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 2.1MHz, fCLOCK = 125MSPS
Two Tone
To Nyquist
72
79
76
68
68
64
60
55
60
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
2MHz Span
4MHz Span
82
82
dBc
dBc
–75
–74
dBc
dBc
fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS
Output Settling Time(2)
63
30
2
dBc
ns
ns
to 0.1%
10% to 90%
10% to 90%
Output Rise Time(2)
Output Fall Time(2)
2
ns
Glitch Impulse
3
pV-s
DC-ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error
Gain Error
Gain Drift
All Bits High, IOUT
2.0
–1.0
–10
–10
20.0
+1.25
+10
mA
V
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
±1
±2
±120
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/√Hz
kΩ
+10
Offset Error
Offset Drift
–0.025
+0.025
±0.1
Power Supply Rejection, +VA
Power Supply Rejection, +VD
Output Noise
Output Resistance
Output Capacitance
–0.2
–0.025
+0.2
+0.025
IOUT = 20mA, RLOAD = 50Ω
50
200
12
IOUT, IOUT to Ground
pF
REFERENCE
Reference Voltage
Reference Tolerance
+1.24
±10
±50
10
V
%
Reference Voltage Drift
Reference Output Current
Reference Input Resistance
Reference Input Compliance Range
Reference Small Signal Bandwidth(4)
ppmFSR/°C
µA
MΩ
V
1
0.1
1.25
1.3
MHz
DIGITAL INPUTS
Logic Coding
Straight Binary
Latch Command
Rising Edge of Clock
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Voltage, VIH
Logic Low Voltage, VIL
+VD = +5V
+VD = +5V
+VD = +3V
+VD = +3V
+VD = +5V
+VD = +5V
3.5
2
5
0
3
V
V
V
1.2
0.8
0
V
(5)
Logic High Current, IIH
±20
±20
5
µA
µA
pF
Logic Low Current, IIL
Input Capacitance
Theinformationprovidedhereinisbelievedtobereliable;however,BURR-BROWNassumesnoresponsibilityforinaccuraciesoromissions.BURR-BROWNassumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
withoutnotice. Nopatentrightsorlicensestoanyofthecircuitsdescribedhereinareimpliedorgrantedtoanythirdparty. BURR-BROWNdoesnotauthorizeorwarrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
DAC904
SPECIFICATIONS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltages
+VA
+VD
+2.7
+2.7
+5
+5
+5.5
+5.5
V
V
Supply Current(6)
IVA
24
1.1
8
170
50
45
30
2
15
230
mA
mA
mA
mW
mW
mW
IVA, Power-Down Mode
IVD
Power Dissipation
+5V, IOUT = 20mA
+3V, IOUT = 2mA
Power Dissipation, Power-Down Mode
Thermal Resistance, θJA
SO-28
75
50
°C/W
°C/W
TSSOP-28
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
+VA to AGND ........................................................................ –0.3V to +6V
DISCHARGE SENSITIVITY
+VDto DGND ........................................................................ –0.3V to +6V
AGNDto DGND ................................................................. –0.3V to +0.3V
This integrated circuit can be damaged by ESD. Burr-Brown
+VA to +VD .............................................................................. –6V to +6V
recommends that all integrated circuits be handled with
CLK, PD to DGND ...................................................... –0.3V to VD + 0.3V
D0-D13 to DGND ........................................................ –0.3V to VD + 0.3V
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
IOUT, IOUT to AGND............................................................ –1V to VA + 0.3V
BW, BYP to AGND....................................................... –0.3V to VA + 0.3V
ESD damage can range from subtle performance degradation
REFIN, FSA to AGND .................................................. –0.3V to VA + 0.3V
INT/EXT to AGND ........................................................ –0.3V to VA + 0.3V
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
changes could cause the device not to meet its published
Storage Temperature ..................................................................... +125°C
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC904U
SO-28
217
"
360
"
–40°C to +85°C
DAC904U
DAC904U
DAC904U/1K
DAC904E
Rails
Tape and Reel
Rails
"
DAC904E
"
"
"
"
TSSOP-28
–40°C to +85°C
DAC904E
"
"
"
DAC904E/2K5
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC904E/2K5” will get a single 2500-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
DEMO BOARD
PRODUCT
ORDERING NUMBER
COMMENT
DAC904U
DAC904E
DEM-DAC90xU
DEM-DAC904E
Populated evaluation board without D/A converter. Order sample of desired DAC90x model separately.
Populated evaluation board including the DAC904E.
®
3
DAC904
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR
DESCRIPTION
Top View
SO/TSSOP
1
2
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
PD
Data Bit 1 (D13), MSB
Data Bit 2 (D12)
Data Bit 3 (D11)
Data Bit 4 (D10)
Data Bit 5 (D9)
3
4
5
6
Data Bit 6 (D8)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
1
2
3
4
5
6
7
8
9
28 CLK
27 +VD
26 DGND
25 NC
7
Data Bit 7 (D7)
8
Data Bit 8 (D6)
9
Data Bit 9 (D5)
10
11
12
13
14
15
Data Bit 10 (D4)
Data Bit 11 (D3)
Data Bit 12 (D2)
Data Bit 13 (D1)
Data Bit 14 (D0), LSB
24 +VA
23 BYP
22 IOUT
21 IOUT
20 AGND
19 BW
Power Down, Control Input; Active
High. Contains internal pull-down circuit;
may be left unconnected if not used.
DAC904
16
17
INT/EXT
REFIN
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
Reference Input/Ouput. See Applications
section for further details.
Bit 10 10
Bit 11 11
Bit 12 12
Bit 13 13
Bit 14 14
18
19
FSA
BW
Full-Scale Output Adjust
18 FSA
17 REFIN
16 INT/EXT
15 PD
Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VA for Optimum
Performance.
20
21
22
23
24
25
26
27
28
AGND
IOUT
Analog Ground
Complementary DAC Current Output
DAC Current Output
IOUT
BYP
+VA
Bypass Node: Use 0.1µF to AGND
Analog Supply Voltage, 2.7V to 5.5V
No Connection
NC
DGND
+VD
Digital Ground
Digital Supply Voltage, 2.7V to 5.5V
Clock Input
CLK
TYPICAL CONNECTION CIRCUIT
+5V
+5V
0.1µF
+VA
+VD
BW
DAC904
IOUT
IOUT
1:1
LSB
FSA
Switches
BYP
Current
Sources
REFIN
Segmented
MSB
50Ω
0.1µF
20pF
50Ω
20pF
RSET
Switches
0.1µF
INT/EXT
PD
Latches
+1.24V Ref.
14-Bit Data Input
D13.......D0
AGND
CLK
DGND
®
4
DAC904
TIMING DIAGRAM
t1
t2
CLK
tS
tH
D13- D0
tSET
tPD
IOUT
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
tS
tH
tPD
tSET
Clock Pulse High Time
Clock Pulse Low Time
Data Setup Time
Data Hold Time
Propagation Delay Time
6.25
6.25
2
2
(t1+t2)+1
25
ns
ns
ns
ns
ns
ns
Output Settling Time to 0.1%
®
5
DAC904
TYPICAL PERFORMANCE CURVES, VD = VA = +5V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
TYPICAL INL
TYPICAL DNL
10
8
10
8
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
DAC Code
DAC Code
SFDR vs fOUT AT 25MSPS
SFDR vs fOUT AT 50MSPS
90
85
80
75
70
65
60
85
80
75
70
65
60
55
–6dBFS
–6dBFS
0dBFS
0dBFS
0
2.0
4.0
6.0
8.0
10.0
12.0
0
5.0
10.0
15.0
20.0
25.0
Frequency (MHz)
Frequency (MHz)
SFDR vs fOUT AT 100MSPS
SFDR vs fOUT AT 125MSPS
85
80
75
70
65
60
55
50
45
85
80
75
70
65
60
55
50
45
–6dBFS
–6dBFS
0dBFS
0dBFS
0
10.0
20.0
30.0
40.0
50.0
60.0
0
10.0
20.0
30.0
40.0
50.0
Frequency (MHz)
Frequency (MHz)
®
6
DAC904
TYPICAL PERFORMANCE CURVES, VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 165MSPS
SFDR vs fOUT AT 200MSPS
80
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
–6dBFS
0dBFS
–6dBFS
0dBFS
0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0
Frequency (MHz)
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS
85
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
40
2.1MHz
X
Diff (–6dBFS)
*
X
5.04MHz
*
*
*
10.1MHz
X
20.2MHz
IOUT (–6dBFS)
X
X
X
40.4MHz
Diff (0dBFS)
X
X
X
X
X
IOUT (0dBFS)
0
10.0
20.0
30.0
40.0
50.0
2
5
10
20
Frequency (MHz)
I
OUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
2.1MHz
THD vs fCLOCK AT fOUT = 2.1MHz
85
80
75
70
65
60
55
50
45
–70
–75
–80
–85
–90
–95
–100
2HD
4HD
10.1MHz
40.4MHz
X
X
X
X
3HD
X
X
X
X
X
X
X
–40
–20
0
25
50
70
85
0
25
50
100
125
150
Temperature (°C)
f
CLOCK (MSPS)
®
7
DAC904
TYPICAL PERFORMANCE CURVES, VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DUAL-TONE OUTPUT SPECTRUM
FOUR-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15 20
25
30
35
40
45 50
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
®
8
DAC904
TYPICAL PERFORMANCE CURVES, VD = VA = +3V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 25MSPS (3V)
SFDR vs fOUT AT 50MSPS (3V)
85
80
75
70
65
60
55
85
80
75
70
65
60
55
–6dBFS
–6dBFS
0dBFS
0dBFS
0
0
0
2.0
4.0
6.0
8.0
10.0
12.0
0
0
0
5.0
10.0
15.0
20.0
25.0
60.0
50.0
Frequency (MHz)
Frequency (MHz)
SFDR vs fOUT AT 100MSPS (3V)
SFDR vs fOUT AT 125MSPS (3V)
85
80
75
70
65
60
55
50
45
85
80
75
70
65
60
55
50
45
–6dBFS
–6dBFS
0dBFS
0dBFS
10.0
20.0
30.0
40.0
50.0
10.0
20.0
30.0
40.0
50.0
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS (3V)
SFDR vs fOUT AT 165MSPS (3V)
85
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
40
Diff (–6dBFS)
–6dBFS
IOUT (–6dBFS)
Diff (0dBFS)
0dBFS
IOUT (0dBFS)
10.0
20.0
30.0
40.0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
Frequency (MHz)
®
9
DAC904
TYPICAL PERFORMANCE CURVES, VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs IOUTFS and fOUT AT 100MSPS (3V)
2.1MHz
THD vs fCLOCK AT fOUT = 2.1MHz (3V)
2HD
80
75
70
65
60
55
50
45
40
–70
–75
–80
–85
–90
–95
–100
5.04MHz
40.4MHz
X
X
X
X
10.1MHz
4HD
3HD
20.2MHz
*
*
*
*
2
5
10
20
0
25
50
100
125
150
IOUTFS (mA)
f
CLOCK (MSPS)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS (3V)
2.1MHz
DUAL-TONE OUTPUT SPECTRUM (3V)
80
75
70
65
60
55
50
45
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10.1MHz
40.4MHz
X
X
X
X
X
X
X
–40
–20
0
25
50
70
85
0
5
10
15 20
25
30
35
40
45 50
Temperature (°C)
Frequency (MHz)
FOUR-TONE OUTPUT SPECTRUM (3V)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
Frequency (MHz)
®
10
DAC904
DAC TRANSFER FUNCTION
APPLICATION INFORMATION
THEORY OF OPERATION
The total output current, IOUTFS, of the DAC904 is the
summation of the two complementary output currents:
The architecture of the DAC904 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic D/A converter is an
array of segmented current sources, which are designed to
deliver a full-scale output current of up to 20mA (see
Figure 1). An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/16384)
(2)
(3)
currents to either output summing node, IOUT or IOUT
.
The complementary outputs deliver a differential output
signal, which improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by
a factor of two, compared to single-ended operation.
IOUT = IOUTFS • (16383 - Code/16384)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the refer-
ence current IREF, which is determined by the reference
The segmented architecture results in a significant reduc-
tion of the glitch energy, and improves the dynamic perfor-
mance (SFDR) and DNL. The current outputs maintain a
very high output impedance of greater than 200kΩ.
voltage and the external setting resistor, RSET
.
IOUTFS = 32 • IREF = 32 • VREF/RSET
(4)
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, RSET. The resulting IREF is internally multiplied by
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
of RSET
.
VOUT = IOUT • RLOAD
VOUT = IOUT • RLOAD
(5)
(6)
The DAC904 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches and the
reference circuitry.
+3V to +5V
Digital
+3V to +5V
Analog
0.1µF
Bandwidth
Control
BW
+VA
+VD
DAC904
Full-Scale
Adjust
Resistor
IOUT
IOUT
1:1
VOUT
LSB
Switches
FSA
PMOS
Current
Source
Array
Ref
Control
Amp
Ref
Input REFIN
Segmented
MSB
Switches
50Ω
400pF
RSET
2kΩ
20pF
50Ω
20pF
0.1µF
0.1µF
BYP
INT/EXT
Ref
Buffer
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
+1.24V Ref
14-Bit Data Input
D13...D0
AGND
Analog
CLK
DGND
Clock
Input
Digital
Ground
Ground
NOTE: Supply bypassing not shown.
FIGURE 1. Functional Block Diagram of the DAC904.
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11
DAC904
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer will be
instrumental for achieving excellent distortion performance.
Common-mode errors, such as even-order harmonics or
noise, can be substantially reduced. This is particularly the
case with high output frequencies and/or output amplitudes
below full-scale.
The value of the load resistance is limited by the output
compliance specification of the DAC904. To maintain speci-
fied linearity performance, the voltage for IOUT and IOUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
(2 • Code – 16383)
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
VOUTDIFF = VOUT – VOUT
=
• IOUTFS • RLOAD
(7)
16384
ANALOG OUTPUTS
The DAC904 provides two complementary current outputs,
IOUT and IOUT. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ || 12pF for IOUT
and IOUT results from the parallel combination of the differ-
ential switches, along with the current sources and associ-
ated parasitic capacitances.
INPUT CODE (D13 - D0)
IOUT
IOUT
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0000
20mA
10mA
0mA
0mA
10mA
20mA
Table I. Input Coding vs Analog Output Current.
OUTPUT CONFIGURATIONS
The current output of the DAC904 allows for a variety of
configurations, some of which are illustrated below. As
mentioned previously, utilizing the converter’s differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
(see Figure 3) or a differential amplifier configuration (see
Figure 4). The transformer configuration is ideal for most
applications with ac coupling, while op amps will be suitable
for a dc-coupled configuration.
+VA
DAC904
The single-ended configuration (see Figure 6) may be con-
sidered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to
ground will convert the output current into a ground-refer-
enced voltage signal. To improve on the dc linearity an I to
V converter can be used instead. This will result in a
negative signal excursion and, therefore, requires a dual
supply amplifier.
IOUT
RL
IOUT
RL
FIGURE 2. Equivalent Analog Output.
DIFFERENTIAL WITH TRANSFORMER
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC904, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of IOUTFS = 2mA.
Care should be taken that the configuration of DAC904 does
not exceed the compliance range to avoid degradation of the
distortion performance and integral linearity.
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance (see
Figure 3). The appropriate transformer should be carefully
selected based on the output frequency spectrum and imped-
ance requirements. The differential transformer configura-
tion has the benefit of significantly reducing common-mode
signals, thus improving the dynamic performance over a
wide range of frequencies. Furthermore, by selecting a
suitable impedance ratio (winding ratio), the transformer can
be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown, ADT1-1WT (by Mini-Circuits), has a 1:1
ratio and may be used to interface the DAC904 to a 50Ω
load. This results in a 25Ω load for each of the outputs, IOUT
and IOUT. The output signals are ac coupled and inherently
isolated because of the transformer's magnetic coupling .
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC904 by selecting a suitable
transformer while maintaining optimum voltage levels at
®
12
DAC904
As shown in Figure 3, the transformer’s center tap is con-
nected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RS,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • IOUTFS/2. However, in
this case, the two resistors, RS, must be used to enable the
necessary dc-current flow for both outputs.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC904 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate off of a dual power supply (±5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R4.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer solu-
tion because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capa-
bilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The ac performance of this circuit may
be improved by adding a small capacitor, CDIFF, between the
ADT1-1WT
outputs IOUT and IOUT, as shown in Figure 4. This will intro-
(Mini-Circuits)
1:1
duce a real pole to create a low-pass filter in order to slew-
limit the DACs fast output signal steps, which otherwise
could drive the amplifier into slew-limitations or into an
overload condition; both would cause excessive distortion.
The difference amplifier can easily be modified to add a
level shift for applications requiring the single-ended output
voltage to be unipolar, i.e., swing between 0V and +2V.
IOUT
RS
50Ω
Optional
RDIFF
DAC904
RL
IOUT
RS
50Ω
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the
OPA2680, which is set up as a transimpedance stage, or
‘I to V converter’. With this circuit, the DAC’s output will
be kept at a virtual ground, minimizing the effects of output
impedance variations, and resulting in the best dc linearity
(INL). However, as mentioned previously, the amplifier
may be driven into slew-rate limitations, and produce un-
wanted distortion. This may occur, especially, at high DAC
update rates.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a dc-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor
values shown were selected to result in a symmetric 25Ω
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resis-
tors RL, and should be considered.
+5V
50Ω
1/2
OPA2680
–VOUT = IOUT • RF
RF1
CF1
DAC904
R2
402Ω
IOUT
CD1
R1
200Ω
RF2
CF2
IOUT
VOUT
DAC904
IOUT
OPA680
CD2
IOUT
R3
CDIFF
200Ω
–5V +5V
1/2
OPA2680
RL
28.7Ω
R4
402Ω
RL
26.1Ω
–VOUT = IOUT • RF
50Ω
–5V
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and AC-Coupling.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
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13
DAC904
INTERNAL REFERENCE OPERATION
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
The DAC904 has an on-chip reference circuit which com-
prises a 1.24V bandgap reference and a control amplifier.
Grounding of pin 16, INT/EXT, enables the internal refer-
ence operation. The full-scale output current, IOUTFS, of the
DAC904 is determined by the reference voltage, VREF, and
the value of resistor RSET. IOUTFS can be calculated by:
IOUTFS = 32 • IREF = 32 • VREF / RSET
(10)
1
GBP
=
(8)
2πRFCF 4πRFCD
As shown in Figure 7, the external resistor RSET connects to
the FSA pin (Full-Scale Adjust). The reference control
amplifier operates as a V to I converter producing a refer-
ence current, IREF, which is determined by the ratio of VREF
and RSET (see Equation 10). The full-scale output current,
IOUTFS, results from multiplying IREF by a fixed factor of 32.
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f-3dB of approximately:
GBP
f−3dB
=
(9)
2πRFCD
+5V
CCOMPEXT
0.1µF
The full-scale output voltage is defined by the product of
IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
BW
+VA
DAC904
VREF
RSET
IREF
=
FSA
Ref
Control
Amp
Current
Sources
REFIN
RSET
2kΩ
SINGLE-ENDED CONFIGURATION
CCOMP
400pF
0.1µF
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0 to 0.5V into the 25Ω load.
INT/EXT
+1.24V Ref.
FIGURE 7. Internal Reference Configuration.
Using the internal reference, a 2kΩ resistor value results in
a 20mA full-scale output. Resistors with a tolerance of 1%
or better should be considered. Selecting higher values, the
converter output can be adjusted from 20mA down to 2mA.
Operating the DAC904 at lower than 20mA output currents
may be desirable for reasons of reducing the total power
consumption, improving the distortion performance, or ob-
serving the output compliance voltage limitations for a given
load condition.
IOUTFS = 20mA
VOUT = 0V to +0.5V
IOUT
DAC904
IOUT
50Ω
50Ω
25Ω
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. To improve the ac performance, an additional capaci-
tor (CCOMPEXT) should be applied between the BW pin and the
analog supply, +VA, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps
shunting feedthrough signals more effectively, and improving
the noise performance of the DAC904.
FIGURE6. DrivingaDoublyTerminated50ΩCableDirectly.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.
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DAC904
EXTERNAL REFERENCE OPERATION
POWER-DOWN MODE
The DAC904 features a power-down function which can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic
High to the PD pin will initiate the power-down mode, while
a logic Low enables normal operation. When left uncon-
nected, an internal active pull-down circuit will enable the
normal operation of the converter.
The internal reference can be disabled by applying a logic
High (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
DIGITAL INPUTS
The DAC904 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1uF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. There-
fore they should be located as close as physically possible to
those device leads. Whenever possible, the capacitors should
be located immediately under each pair of supply/ground
pins on the reverse side of the pc board. This layout ap-
proach will minimize the parasitic inductance of component
leads and pcb runs.
The digital inputs, D0 (LSB) through D13 (MSB) of the
DAC904 accept standard positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following rising clock edge (refer to the specification
table and timing diagram for details). The best performance
will be achieved with a 50% clock duty cycle, however, the
duty cycle may vary as long as the timing specifications are
met. Additionally, the setup and hold times may be chosen
within their specified limits.
All digital inputs are CMOS compatible. The logic thresh-
olds depend on the applied digital supply voltage such that
they are set to approximately half the supply voltage;
Vth = +VD/2 (±20% tolerance). The DAC904 is designed to
operate over a supply range of 2.7V to 5.5V.
+5V
CCOMPEXT
0.1µF
BW
+VA
DAC904
VREF
RSET
IREF
=
FSA
Ref
Control
Amp
Current
Sources
REFIN
External
Reference
CCOMP
400pF
INT/EXT
RSET
+5V
+1.24V Ref.
FIGURE 8. External Reference Configuration.
®
15
DAC904
Further supply decoupling with surface mount tantalum
capacitors (1uF to 4.7uF) may be added as needed in
proximity of the converter.
The power to the DAC904 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low noise analog supply voltage, which can then
be connected to the +VA supply pin of the DAC904.
Low noise is required for all supply and ground connections
to the DAC904. It is recommended to use a multilayer pc-
board utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of
the different supply currents and signal traces. Generally,
analog supply and ground planes should only extend into
analog signal areas, such as the DAC output signal and the
reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the D/A converter.
This can be realized with a short track of approximately
1/8inch (3mm).
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
®
16
DAC904
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