DIR1703 [BB]
DIGITAL AUDIO INTERFACE RECEIVER; 数字音频接口接收器
| 型号： | DIR1703 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 文件： | 总19页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES007– JULY 2001
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FEATURES
DESCRIPTION
D
Standard Digital Audio Interface Receiver
(EIAJ1201)
The DIR1703 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1703 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits. It also includes extensive
errors reporting.
D
D
D
D
Sampling Rate: 32 / 44.1 / 48 / 88.2 / 96 kHz
Recover 128 / 256 / 384 / 512 f System Clock
s
Very Low Jitter System Clock Output (75 ps
Typically)
On-Chip Master Clock Oscillator, Only an
External Crystal Is Required:
24.576 / 22.5792 / 18.432 / 16.9344 / 16.384 /
12.288 / 11.2896 / 8.192 / 6.144 / 5.6448 /
4.096 MHz Crystals Are Available
The significant advantages of the DIR1703 are
96-kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
Controlled Tracking (SpAct ) system. The input
signal is reclocked with the patented Sampling
period Adaptive controlled tracking system for
maximum quality. These features are required for
recent consumer and professional audio
instruments, in which the DIR has an interface to
any kind of delta-sigma type ADC/DAC with a
96-kHz sampling rate.
D
D
D
Selectable Output PCM Audio Data Format
Selectable Crystal Clock and PPL Clock
Operation Mode
Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
D
Single 3.3-V Power Supply
Package: 28 SSOP
D
APPLICATIONS
D
D
D
AV Receiver
MD Player
DAC Unit
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
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Copyright 2001, Texas Instruments Incorporated
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ꢚ ꢞ ꢛ ꢚꢓ ꢔꢨ ꢖꢕ ꢙ ꢡꢡ ꢟꢙ ꢗ ꢙ ꢘ ꢞ ꢚ ꢞ ꢗ ꢛ ꢣ
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1
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SLES007– JULY 2001
DIR1703
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADFLG
BRATE0
BRATE1
SCKO
CKSEL
UNLOCK
FMT1
2
3
4
FMT0
5
V
V
DD
CC
6
DGND
XTO
AGND
FILT
RST
7
8
XTI
9
CKTRNS
LRCKO
BCKO
DOUT
SCF0
DIN
10
11
12
13
14
BRSEL
BFRAME
EMFLG
URBIT
CSBIT
SCF1
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
}
DIR1703E
Rails
†
324
DIR1703E
SSOP–28
–25°C to +85°C
DIR1703E
DIR1703E/2K
Tape and Reel
†
‡
TI equivalent no. 4040065.
Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of DIR1703E/2K will get a single 2000-piece tape and reel.
block diagram
V
DD
V
CC
BRSEL SCF
CKSEL
FMT
XTI
OSC
SCKO
XTO
BCKO
OSC
LRCKO
DOUT
PLL1
Selector
Audio Clock
And Data
Generator
BFRAME
URBIT
CSBIT
100 MHZ
DIN
PLL2
SpAct
FIFO
EMFLG
ADFLG
wrclk
S/PDIF
Decoder
rdclk
BRATE
2
DGND AGND
FILT
RST
UNLOCK CKTRNS
2
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SLES007– JULY 2001
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
PIN
1
ADFLG
BRATE0
BRATE1
SCKO
O
O
O
O
–
–
O
I
Audio data or digital data flag
2
f
f
rate flag 0 (32 k, 44.1 k, 48 k, and 88 k / 96 k)
rate flag 1 (32 k, 44.1 k, 48 k, and 88 k / 96 k)
s
3
s
4
System clock output
V
5
Digital power supply, +3.3 V
Digital ground
DD
DGND
XTO
6
7
Crystal oscillator output
XTI
8
Crystal oscillator input, external clock input
Clock transition status output
CKTRNS
LRCKO
BCKO
DOUT
SCF0
SCF1
CSBIT
URBIT
EMFLG
BFRAME
BRSEL
DIN
9
O
O
O
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Audio latch enable (LRCK, f ) output
s
Audio bit clock output
Audio serial data output
System clock frequency select (128/256/384/512 f ) (see Note 1)
s
I
System clock frequency select (128/256/384/512 f ) (see Note 1)
s
O
O
O
O
I
Channel status bit output (see Note 2)
User bit output (see Note 2)
Emphasis flag
Block start clock (B-frame)
Default bit rate select (32 / 44.1 / 48 / 88.2 / 96 kHz) (see Note 1)
S/PDIF data digital input (see Note 4)
Reset input, active LOW (see Note 3)
External filter
I
RST
I
FILT
–
–
–
I
AGND
Analog ground
V
Analog power supply, 3.3V
CC
FMT0
Audio data format select (see Note 1)
Audio data format select (see Note 1)
PLL unlock or parity error flag
FMT1
I
UNLOCK
CKSEL
O
I
System clock operation mode selected. Low: PLL, High: Crystal (see Note 1)
NOTES: 1. Schmitt trigger input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
2. Serial outputs are utilized for both consumer and professional application.
3. Schmitt trigger input with internal pullup (TYP 51 kΩ), 5 V tolerant.
4. CMOS level input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
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†
absolute maximum ratings
Supply voltage, V , V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
CC DD
Supply voltage differences, V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
CC DD
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage: Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V)
XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V + 0.3 V)
DD
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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electrical characteristics, all specifications at T = 25°C, V = V = 3.3 V (unless otherwise noted)
DD
A
CC
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(5)
(5)
V
V
V
V
V
V
V
V
V
V
2
5.5
0.8
IH
IL
(6)
(6)
(7)
(7)
(8)
(8)
(9)
(9)
70%V
IH2
IL2
IH3
IL3
OH
OL
OH
OL
DD
Input logic level
VDC
30%V
DD
5.5
70%V
DD
30%V
DD
I
I
I
I
= 1 mA
V
DD
–0.4
–0.4
O
O
O
O
= –2 mA
= 2 mA
0.5
Output logic level
Input leakage current
VDC
V
DD
= –4 mA
0.5
(10)
I
I
I
I
I
I
f
V
V
V
V
V
V
= V
DD
= 0 V
65
100
10
IH
IN
IN
IN
IN
IN
IN
(10)
–10
–10
IL
(11)
= V
10
IH
DD
= 0 V
= V
µA
(11)
–100
–10
–10
32
–65
IL
(6)
10
10
96
IH
DD
(6)
IL
(12)
= 0 V
Input sampling frequency
System clock frequency
kHz
MHz
s
128/256/
384/512 f
SCKO
4.096
49.152
s
t
j
SCKO clock jitter
SCKO duty cycle
75
ps RMS
50%
See
Table 3
XTI clock accuracy
–500
500
ppm
S/PDIF INPUT
Duty cycle
V
IN
V
IN
= 1.5 V,
= 1.5 V
f
s
= 96 kHz
15%
85%
Jitter
±10
ns p-p
POWER SUPPLY REQUIREMENTS
V
, V
Voltage range
3
3.3
3.4
26
3.6
4.7
36
VDC
mA
DD CC
I (V
CC CC
)
)
Supply current (see Note 13)
Power dissipation
I (V
DD DD
P
D
100
mW
TEMPERATURE RANGE
Operation temperature
Thermal resistance
–25
85
°C
θ
28-pin SSOP
100
°C/W
JA
NOTES: 5. TTL compatible, except pins 8, 20: XTI, DIN.
6. Pin 8: XTI (CMOS logic level).
7. Pin 20: DIN (CMOS logic level).
8. Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK.
9. Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT.
10. Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL.
11. Pin 21: RST
12. f is defined as the incoming audio sampling frequency per channel.
s
13. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock
frequency.
5
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basic operation theory
The DIR1703 is operated as either a PLL clock operation mode or a crystal clock operation mode. These basic
operation modes are user selectable.
Sampling period adaptive controlled tracking system (SpAct) is a newly developed clock recover architecture,
giving very low jitter clock from S/PDIF data input.
The DIR1703 has two PLLs, PLL1 and PLL2. SpAct is supplied with a 100 MHz executing clock from PLL1.
The DIR1703 requires system clock input for operation of SpAct at both the PLL clock operation mode and the
crystal clock operation mode. This system clock can be obtained by connecting a crystal resonator at the
XTI/XTO pins or applying an external clock input at the XTI pin as shown in Figure 1.
PLL2 generates the system clock SCKO by using the output signal of the SpAct. The source of SCKO, either
OSC (crystal) or PLL2, is selected by the CKSEL pin (called PLL clock operation mode and crystal clock
operation mode).
In the PLL clock operation mode, when the S/PDIF signal goes to noninput, SCKO may hold the latest tracked
frequency.
Also, the DIR1703 indicates the unlocked state by a high level output at the UNLOCK pin. When the S/PDIF
signal restarts, the analog PLL will lock to the incoming S/PDIF signal with very low jitter. The PLL lock-in time
is around 1 ms using the SpAct.
Then, the DIR1703 indicates the locked status by a low output at the UNLOCK pin. In this status, the BRATE
pins simultaneously indicate the bit rate of the incoming S/PDIF signal.
After RST (pin 21) is removed, SCKO is set to the default frequency, which can be selected by the BRSEL and
SCF pins. The sampling rate (f ), 32 k, 44.1 k, 48 k, 88.2 k, or 96 k is selected by the BRSEL pin. The system
S
clock frequency, 128, 256, 384, or 512 f is also selected by the SCF pins.
S
In the crystal clock operation mode, the crystal oscillator generates three audio clocks SCKO, BCKO, and
LRCKO. In this mode, DOUT is always set to mute (zero). BRATE and UNLOCK can be indicated according
to the incoming S/PDIF signal.
If CKSEL (pin 28) is connected to UNLOCK (pin 27), which indicates the S/PDIF decoding status and the PLL2
lock-state, the system clock source can be selected automatically when the S/PDIF signal is active and the bit
rate is detected.
External Clock
C
Crystal
1
XTI
XTI
XTAL
OSC
CIR
XTAL
OSC
CIR
R
1
Open
XTO
XTO
C
R
2
1
= 1 MΩ,
C , C = 10 TO 33 pF
DIR1703
DIR1703
1
2
Crystal Resonator Connection
External Clock Input
Figure 1. System Clock Connections
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system clock output
The primary function of the DIR1703 is to recover audio data and a low jitter clock from a digital audio
transmission line. The system clock (SCKO) can be selected in two clocks that are generated by the crystal
oscillator clock (crystal mode) or the PLL clock (PLL mode) by the SpAct.
The two operation modes are selected by the CKSEL pin. In the PLL clock operation mode, the clock that can
be generated is SCKO (128 / 256 / 384 / 512 f , shown in Table 1), BCKO (64 f ), and LRCKO (1 f ). SCKO
S
S
S
is the output of the voltage controlled oscillator (VCO) in an analog PLL. The PLL function consists of a VCO,
phase and frequency detector, and a external second-order loop filter. The closed-loop transfer function, which
specifies the PLL jitter attenuation characteristics, is shown in Figure 2. In the crystal clock operation mode,
SCKO can be generated from several crystal oscillators shown in Table 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME, EMFLG, URBIT, or CSBIT as shown in Table 3. A 12.288 MHz crystal resonator can be used for
96-kHz – 128 f (CSBIT), 48-kHz – 256 f (OPEN) and 32-kHz – 384 f (BFRAME). If BRSEL is not connected
S
S
S
to any pins, the 48-kHz sampling rate is selected. The system clock frequency of both modes can be selected
by control data at SCF0 and SCF1 pins shown in Table 4.
Table 5 shows the state of the system and the condition of audio clocks and flags in both the PLL and crystal
operation modes. In the crystal clock operation mode, SpAct also detects the bit rate of the incoming S/PDIF
signal and indicates the state at the UNLOCK pin. Therefore, by connecting CKSEL pin 28) to UNLOCK (pin
27), the system clock source can be selected automatically when the S/PDIF signal arrives and the bit rate is
detected. The required accuracy for clock frequency of the crystal resonator or external clock input is ±500 ppm.
Table 1. Generated System Clock (SCKO) PLL Clock Operation Mode
SAMPLING
128 f
256 f
384 f
512 f
S
S
S
S
RATE
32 kHz
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
44.1 kHz
48 kHz
88.2 kHz
96 kHz
0
–20
–40
–60
–80
–100
100
1 M
f – Frequency – kHz
10 M
100 M
1 k
10 k
100 k
Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter
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system clock output (continued)
Table 2. Generated System Clock (SCKO) Crystal Clock Operation Mode
SAMPLING
RATE
128 f
256 f
384 f
512 f
S
S
S
S
32 kHz
44.1 kHz
48 kHz
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
88.2 kHz
96 kHz
See Note 14
See Note 14
NOTE 14: External clock only
Table 3. Selectable Crystal Oscillator
SAMPLING
RATE
BRSEL
CONNECTED TO
128 f
256 f
384 f
512 f
S
S
S
S
32 kHz
44.1 kHz
48 kHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
12.288 MHz
16.9344 MHz
18.432 MHz
33.8688 MHz
(see Note 14) (see Note 14)
36.864 MHz 49.152 MHz
(see Note 14) (see Note 14)
16.384 MHz
22.5792 MHz
24.576 MHz
45.1584 MHz
BFRAME
EMFLG
open
88.2kHz
96 kHz
11.2896 MHz
12.288 MHz
22.5792 MHz
24.576 MHz
URBIT
CSBIT
Table 4. System Clock Selection
SCF1
SCF0
LOW
HIGH
LOW
HIGH
SYSTEM CLOCK
LOW
LOW
HIGH
HIGH
128 f
256 f
384 f
512 f
S
S
S
S
8
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system clock output (continued)
Table 5. System Clock Operation Mode
CONDITIONS
S/PDIF
CLOCK AND DATA OUTPUTS
MODE
CS. UR
BIT
AD.
EMFLG
CKSEL
SCKO
BCKO
LRCKO
DOUT
BRATE
UNLOCK
DATA
†
Default PLL
Default
PLL
Default
PLL
After
RESET
†
†
(128, 256, 384, 512
MUTE
LOW
HIGH
LOW
LOW
f )
S
(64 f )
(1 f )
S
S
PLL
PLL
PLL
(1 f )
S
YES
NO
(128, 256, 384, 512
DATA
MUTE
MUTE
MUTE
MUTE
DETECT
LOW
HIGH
HIGH
LOW
HIGH
DATA
DATA
PLL
LOW
(64 f )
S
f )
S
‡
HOLD
‡
‡
HOLD
(1 f )
S
HOLD
‡
Unknown
‡
(128, 256, 384, 512
HOLD
HOLD
(64 f )
S
f )
S
Crystal
Crystal
Crystal
After
RESET
(128, 256, 384, 512
LOW
LOW
LOW
(64 f )
S
(1 f )
S
f )
S
Crystal
Crystal
Crystal
Unknown
YES
NO
(128, 256, 384, 512
DETECT
Unknown
LOW
LOW
CRYSTAL
HIGH
(64 f )
S
(1 f )
S
f )
S
Crystal
Crystal
Crystal
Unknown
(128, 256, 384, 512
(64 f )
(1 f )
S
S
f )
S
†
‡
In the PLL mode, the DIR1703 will be the same frequencies as the crystal mode after RESET; however, the frequency error is below 1%.
Holds the latest tracked frequency.
SCKO timing
t
SCKH
H
L
2 V
SCKO
0.8 V
t
SCKL
System Clock Pulse
†
Cycle Time
SCKO Clock Pulse Width High
SCKO Clock Pulse Width Low
t
t
7 ns (min)
7 ns (min)
SCKH
SCKL
†
1/128 f , 1/256 f , 1/384 f or 1/512 f .
S
S
S
S
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SLES007– JULY 2001
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1703 automatically detects
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 6 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 6. Incoming Sample Frequency Bits
SAMPLING RATE
32 kHz
BRATE1
HIGH
LOW
BRATE0
HIGH
LOW
44.1 kHz
48 kHz
LOW
HIGH
LOW
88.2 kHz
96 kHz
HIGH
HIGH
LOW
timing specification for PLL operation
lock-up time
Unlock
PLL
Lock
Condition
DIN Start
PLL Status
Indicator Pin
Site UNLOCK
H
L
t
< 1 ms
INT
Figure 3. PLL Lock Up Timing
relation between audio-data-output timing and PLL condition indicator timing
In the PLL clock operation mode, when the S/PDIF signal is not detected after reset removal, audio clocks
(SCKO, BCKO, LRCKO) which are not related to S/PDIF signal are generated by SpAct. The bit rate can be
selected by setting pin BRSEL. If BRSEL is OPEN or connected to DGND, the default bit rate frequency is set
to 48 kHz. If BRSEL is connected to one of the output pins BFRAME, EMFLG, URBIT, or CSBIT, the frequency
is set to 32, 44.1, 88.2, or 96 kHz, respectively. Therefore, the initial frequency is the same as the crystal
resonator, however, its error frequency is below 1% after reset.
When the analog PLL is still unlocked after at least ten rising-edges of the S/PDIF, a S/PDIF decoder can detect
the incoming S/PDIF signal. Thus, DOUT becomes low (MUTE) until the analog PLL locks. This MUTE period
is less than 1 ms (analog PLL’s lock-up time is less than 0.5 ms). When the decoder does not detect an incoming
S/PDIF signal, UNLOCK will output high level status at the LRCKO clock transition. SCKO keeps its frequency
at the latest tracked bit rate.
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SLES007– JULY 2001
relation between audio-data-output timing and PLL condition indicator timing (continued)
Unlock
Lock
PLL
Condition
H
L
UNLOCK
LRCKO
BCKO
DOUT
Mute
Mute
31
32
1
2
Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing
unlock flag minimum pulse width time
CASE-A when PLL is unlocked
In the PLL clock operation mode, when PLL goes to unlock by a disconnected S/PDIF signal, the UNLOCK flag
pin indicates high and the audio data output DOUT becomes low (MUTE). The MUTE period, t , is a
(UNL)
minimum of 200 ms. In this period, SCKO, BCKO, and LRCKO frequencies hold the latest tracked frequency.
If the S/PDIF signal is connected again in this unlock period, the bit rate is changed to the incoming signal
frequency, after at least 1 ms (before the UNLOCK flag becomes low). CKTRNS indicates the validity of SCKO.
When CKTRNS is high, the frequency of SCKO, BCKO, and LRCKO is in transition.
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SLES007– JULY 2001
t
>200 ms
(UNL)
UNLOCK
LRCKO
H
L
CKTRANS
S/PDIF Signal Bit Rate
S/PDIF Signal Starts Again
New Bit Rate
BCKO
DOUT
t
< 1 ms
(TRNS)
1
2
Mute
Figure 5. UNLOCK Flag Minimum Pulse Width Time for PLL Unlocked
CASE-B when parity error occurs
When a parity error occurs in one subframe interval, UNLOCK becomes high during this subframe, then returns
low at the next arriving subframe.
During this subframe with parity error, the data output will hold the previous data of each channel.
CASE-B When Parity Error Occurs
H
L
UNLOCK
LRCKO
BCKO
DOUT
24
1
24
1
2
Same as The Previous Data
Figure 6. UNLOCK Timing for Parity Error
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SLES007– JULY 2001
PCM audio interface
The DIR1703 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format.
The PCM audio interface format of the DIR1703 is selected using the format pins FMT1, FMT0. Table 7 shows
the FMT pin configuration.
Table 7. Audio Output Data Format Select
FMT1
LOW
LOW
HIGH
HIGH
FMT0
LOW
HIGH
LOW
HIGH
AUDIO DATA FORMAT
16 bit MSB first, Right justified
24 bit MSB first, Right justified
24 bit MSB first, Left justified
24 bit IIS
Standard Data Format; L–Channel = HIGH, R–Channel = LOW
1/f
S
LRCKO
R–Channel
L–Channel
BCKO
Right Justified
Audio Data Word = 16–Bit
1
2
1 2
14 15 16
15 16
LSB
DOUT
15 16
LSB
MSB
MSB
Right Justified
Audio Data Word = 24–Bit
DOUT
22 23 24
1
2
23 24
LSB
1
2
23 24
LSB
MSB
MSB
Left Justified
Audio Data Word = 24–Bit
DOUT
1
2
23 24
LSB
1
2
23 24
LSB
MSB
MSB
IIS Data Format; L–Channel = LOW, R–Channel = HIGH
1/f
S
LRCKO
BCKO
L–Channel
R–Channel
Audio Data Word = 24–Bit
DOUT
1
2
23 24
LSB
1
2
23 24
LSB
1
MSB
MSB
Figure 7. Audio Data Output Format
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SLES007– JULY 2001
PCM audio interface (continued)
50% of V
50% of V
SCKO
DD
t
t
(LS)
(SL)
LRCKO
DD
t
t
t
(LB)
(BCH)
(BCL)
50% of V
50% of V
BCKO
DOUT
DD
t
t
(BCY)
(BL)
DD
t
t
(DH)
(DS)
PARAMETERS
MIN
11
MAX UNITS
t
t
t
t
t
t
t
t
t
SCKO rising edge to LRCKO edge
LRCKO edge to SCKO rising edge
BCKO pulse cycle time
ns
ns
(SL)
5
(LS)
64 f
(BCY)
(BCL)
(BCH)
(BL)
S
BCKO pulse width low
78
78
78
78
78
78
ns
ns
ns
ns
ns
ns
BCKO pulse width high
BCKO rising edge to LRCKO edge
LRCKO edge to BCKO rising edge
DOUT setup time
(LB)
(DS)
(DH)
DOUT hold time
Figure 8. Audio Data Output Timing
dedicated output pins for both professional and consumer applications
The DIR1703 has parallel output pins for both professional and consumer applications. In the professional mode
de-emphasis flag EMFLG indicates a 50/15-µs time constant pre-emphasis. Professional mode is set when Bit
0 of CSBIT Byte 0 is high. When Bits 2 to 4 of CSBIT Byte 0 is 110, the EMFLG becomes high. In other cases,
EMFLG is low. Audio/non-audio flag ADFLG indicates S/PDIF data mode, i.e., Bit 1 of CSBIT Byte 0. When
ADFLG is low, S/PDIF data includes PCM audio signal. In other cases, ADFLG is high.
In the consumer mode EMFLG indicates 2-channel audio with a 50/15-µs time constant pre-emphasis.
Consumer mode is set when Bit 0 of CSBIT Byte 0 is low. When Bits 3 to 5 of CSBIT Byte 0 is 100, EMFLG
becomes high. In other cases, EMFLG is low. The ADFLG signal indicates whether S/PDIF includes digital data,
such as AC-3 or not. When Bit 1 of CSBIT Byte 0 is high, the incoming S/PDIF includes a non-audio signal. In
other cases, ADFLG is low.
These dedicated output pins are checked for only L-ch CS information. The DIR1703 does not support CRC
check function in the professional mode. As for other flags, CS bit and user-bit for professional and consumer
applications, are directly supplied by serial mode at CSBIT (pin 15) and URBIT (pin 16). These pins indicate
L-ch and R-ch information sequentially.
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SLES007– JULY 2001
dedicated output pins for both professional and consumer applications (continued)
Audio data and clock timing are described below. The serial output data starts after 16±8 BCKO clocks from
when the corresponding subframe arrives. When B subframe arrives, the BFRAME pin becomes high during
1/f x 32 (s), then BFRAME returns to low after 32 frames.
s
1/f (S)
S
Frame 0
Frame 1
Frame 191
W
Frame 0
R191
S/PDIF
B
W
M
W
M
B
16 ± 8 BCKO Delay
64 BCKO
L1 R1
URBIT/CSBIT/UNLOCK etc.
LRCKO
L0
R0
L191
BFRAME
1/f x 32 (S)
S
1/f x 192 (S)
S
LRCKO
BCKO
DOUT
64 1
2 3
Figure 9. Timing Chart for Audio Data and Channel Status
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SLES007– JULY 2001
reset sequence
The DIR1703 requires external reset operation after power on. Figure 10 shows the reset sequence after power
on. The DIR1703 is ready for receiving S/PDIF signal when the internal reset sequence has finished and
CKTRNS goes to LOW. BFRAME, EMFLG, URBIT and CSBIT pins are used for configuration during the period
from the rising edge of RST to the falling edge of CKTRNS. S/PDIF signal is accepted after CKTRNS goes to
LOW. The minimum pulse width of RST, t
be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW.
is 100 ns. The RST delay after the power supply reaches 3 V should
RST
3 V
V , V
DD CC
XTI
Stable
Unstable
XTO
RST
DIR1703 Ready
Internal PLL ON
t
> 10 ms
STT
LOW
LOW
HIGH
HIGH
t
> 100 ns
RST
BFRAME,
EMFLG,
VRBIT,
12.5XTI Clock
Chip Status Information
LOW
Unknown
Valid
CSBIT
1160XTI Clock
CKTRNS
DIN
< 5 f
s
S/PDIF Acceptable
< 1 ms
HIGH
UNLOCK
NOTE: SCF0 and SCF1 should be settled during RST assertion. The change of SCF0 and SCF1 is not permitted during normal operation. When
the change is needed, the reset sequence must be started by asserting RST again.
Figure 10. After Power ON
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SLES007– JULY 2001
typical circuit connection
For Automatic System Clock Selection
1
2
28
27
26
25
24
23
22
21
20
19
18
ADFLG
CKSEL
UNLOCK
FMT1
BRATE0
BRATE1
SCKO
Bit Rate Indicator
3
4
Data Format Select
FMT0
5
3.3 V V
V
DD
V
CC
3.3 V V
CC
DD
+
+
C
C
C
4
C
3
7
C
2
1
6
DGND
XTO
AGND
FILT
RST
DIN
R
C
8
2
7
R
1
8
Reset (Active LOW)
Receiver Circuit
XTI
9
C
5
C
CKTRNS
LRCKO
6
10
11
12
BRSEL
BFRAME
EMFLG
URBIT
BCKO
17
16
15
DOUT
SCF0
SCF1
13
14
System Clock
Frequency Select
(128,256,348, 512 f )
CSBIT
s
BRSEL Connection Depends Upon
Crystal Resonator Frequency.
Audio Data
Processor
C
C
C
C :
C :
, C : Bypass Capacitor, 1 µF to 10 µF
2
1
3
5
7
8
, C : Bypass Capacitor, 0.01 µF to 0.1 µF
4
, C : OSC Capacitor, 10 to 33 pF
6
Loop Filter Capacitor, 0.068 µF
Loop Filter Capacitor, 0.0082 µF
OSC Resistor, 1 MΩ
R :
R :
1
2
Loop Filter Resistor, 1.2 kΩ
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SLES007– JULY 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065/D 09/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
18
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