MPC508AU/1KG4 [BB]
Single-Ended 8-Channel/Differential 4-Channel CMOS ANALOG MULTIPLEXERS; 单端8通道/差分4通道CMOS模拟多路复用器
| 型号： | MPC508AU/1KG4 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Single-Ended 8-Channel/Differential 4-Channel CMOS ANALOG MULTIPLEXERS |
| 文件： | 总16页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC508A
MPC509A
M
P
C508
M
PC509
SBFS019A – JANUARY 1988 — REVISED OCTOBER 2003
Single-Ended 8-Channel/Differential 4-Channel
CMOS ANALOG MULTIPLEXERS
FEATURES
● ANALOG OVERVOLTAGE PROTECTION: 70VPP
FUNCTIONAL DIAGRAMS
● NO CHANNEL INTERACTION DURING
1kΩ
1kΩ
1kΩ
OVERVOLTAGE
In 1
Out
● BREAK-BEFORE-MAKE SWITCHING
● ANALOG SIGNAL RANGE: ±15V
● STANDBY POWER: 7.5mW typ
● TRUE SECOND SOURCE
In 2
In 8
Decoder/
Driver
Overvoltage
Clamp and
Signal
5V
Ref
Level
Shift
DESCRIPTION
Isolation
The MPC508A is an 8-channel single-ended analog
multiplexer and the MPC509A is a 4-channel differential
multiplexer.
(1)
(1)
(1) (1)
NOTE: (1) Digital
Input Protection.
MPC508A
A0 A1 A2
EN
The MPC508A and MPC509A multiplexers have input
overvoltage protection. Analog input voltages may exceed
either power supply voltage without damaging the device or
disturbing the signal path of other channels. The protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand 70VPP signal levels and standard ESD
tests. Signal sources are protected from short circuits should
multiplexer power loss occur; each input presents a 1kΩ
resistance under this condition. Digital inputs can also sustain
continuous faults up to 4V greater than either supply voltage.
1kΩ
1kΩ
In 1A
In 4A
Out A
Out B
1kΩ
1kΩ
In 1B
In 4B
Decoder/
Driver
These features make the MPC508A and MPC509A ideal for
use in systems where the analog signals originate from
external equipment or separately powered sources.
Overvoltage
Clamp and
Signal
5V
Ref
Level
Shift
Isolation
The MPC508A and MPC509A are fabricated with Burr-
Brown’s dielectrically isolated CMOS technology. The
multiplexers are available in plastic DIP and plastic SOIC
packages. Temperature range is –40°C to +85°C.
(1) (1)
(1)
NOTE: (1) Digital
Input Protection.
MPC509A
A0 A1
EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2003, Texas Instruments Incorporated
www.ti.com
ELECTRICAL CHARACTERISTICS
Supplies = +15V, –15V; VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +0.8V, unless otherwise specified.
MPC508A/509A
TYP
PARAMETER
TEMP
MIN
MAX
UNITS
ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range
RON, On Resistance(1)
Full
+25°C
Full
–15
+15
1.5
1.8
V
1.3
1.5
0.5
kΩ
kΩ
nA
nA
nA
nA
nA
µA
nA
nA
nA
IS (OFF), Off Input Leakage Current
+25°C
Full
10
ID (OFF), Off Output Leakage Current
MPC508A
+25°C
Full
0.2
5
5
MPC509A
Full
ID (OFF) with Input Overvoltage Applied(2)
ID (ON), On Channel Leakage Current
MPC508A
+25°C
+25°C
Full
2.0
2
10
10
MPC509A
Full
IDIFF Differential Off Output Leakage Current
(MPC509A Only)
Full
10
nA
DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold Drive
VAH, Input High Threshold(3)
Full
Full
Full
0.8
1.0
V
V
4.0
25
IA, Input Leakage Current (High or Low)(4)
µA
SWITCHING CHARACTERISTICS
tA, Access Time
+25°C
Full
0.5
µs
µs
ns
ns
ns
ns
ns
µs
µs
dB
pF
pF
pF
pF
pF
0.6
tOPEN, Break-Before-Make Delay
tON (EN), Enable Delay (ON)
+25°C
+25°C
Full
80
200
500
500
tOFF (EN), Enable Delay (OFF)
+25°C
Full
250
Settling Time (0.1%)
(0.01%)
"OFF Isolation"(5)
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
25°C
1.2
3.5
68
5
50
CS (OFF), Channel Input Capacitance
CD (OFF), Channel Output Capacitance: MPC508A
MPC509A
25
12
5
CA, Digital Input Capacitance
CDS (OFF), Input to Output Capacitance
+25°C
0.1
POWER REQUIREMENTS
PD, Power Dissipation
I+, Current Pin 1(6)
Full
Full
Full
7.5
0.7
5
mW
mA
µA
1.5
20
I–, Current Pin 27(6)
NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended.
(4) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (5) VEN = 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz.
Worst-case isolation occurs on channel 4 due to proximity of the output pins. (6) VEN, VA = 0V or 4.0V.
MPC508A, MPC509A
2
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PIN CONFIGURATIONS
Top View
Top View
16 A1
16 A1
A0
En
1
2
3
4
5
6
7
8
A0
En
1
2
3
4
5
6
7
8
15 Ground
14 +VSUPPLY
13 In 1B
12 In 2B
11 In 3B
10 In 4B
15 A2
14 Ground
13 +VSUPPLY
12 In 5
–VSUPPLY
In 1A
–VSUPPLY
In 1
In 2A
In 2
11 In 6
In 3A
In 3
10 In 7
In 4A
In 4
9
Out B
9
In 8
Out A
Out
MPC508A (Plastic)
MPC509 A (Plastic)
TRUTH TABLES
MPC508A
MPC509A
"ON"
"ON"
A2
A1
A0
EN
CHANNEL
CHANNEL
PAIR
A1
A0
EN
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
L
None
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
X
L
L
H
H
X
L
H
L
L
H
H
H
H
None
1
2
3
4
H
H
ABSOLUTE MAXIMUM RATINGS(1)
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
Voltage between supply pins ............................................................... 44V
V+ to ground ........................................................................................ 22V
V– to ground ........................................................................................ 25V
Digital input overvoltage VEN, VA:
VSUPPLY (+) ................................................... +4V
VSUPPLY (–) ................................................... –4V
or 20mA, whichever occurs first.
Analog input overvoltage VS:
SUPPLY (+) ................................................ +20V
SUPPLY (–) ................................................ –20V
V
V
Continuous current, S or D ............................................................... 20mA
Peak current, S or D
(pulsed at 1ms, 10% duty cycle max) ............................................ 40mA
Power dissipation(2) .......................................................................... 1.28W
Operating temperature range ........................................... –40°C to +85°C
Storage temperature range ............................................. –65°C to +150°C
NOTE: (1) Absolute maximum ratings are limiting values, applied individu-
ally, beyond which the serviceability of the circuit may be impaired. Func-
tional operation under any of these conditions is not necessarily implied.
(2) Derate 1.28mW/°C above TA = +70°C.
MPC508A, MPC509A
3
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TYPICAL PERFORMANCE CURVES
Typical at +25°C unless otherwise noted.
SETTLING TIME vs
SOURCE RESISTANCE FOR 20V STEP CHANGE
1k
CROSSTALK vs SIGNAL FREQUENCY
1
0.1
100
To ±0.01%
R
= 100kΩ
s
R
s
= 10kΩ
10
0.01
R
s
= 1kΩ
R
= 100Ω
s
To ±0.1%
1
0.001
0.0001
0.1
0.01
0.1
1
10
100
1
10
100
1k
10k
Source Resistance (kΩ)
Signal Frequency (Hz)
COMBINED CMR vs
FREQUENCY MPC509A AND INA110
120
100
80
60
40
20
0
G = 500
G = 100
G = 10
1
10
100
1k
10k
Frequency (Hz)
MPC508A, MPC509A
4
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Differential Multiplexer Static Accuracy
DISCUSSION OF
PERFORMANCE
DC CHARACTERISTICS
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current mis-
match, load differential impedance mismatch, and common-
mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel ON
resistance (RON), the load impedance, the source impedance,
the load bias current and the multiplexer leakage current.
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
Source resistance loading error;
Multiplexer ON resistance error;
and, dc offset error caused by both load bias current and
multiplexer leakage current.
The effects of these errors can be minimized by following the
general guidelines described in this section, especially for
low-level multiplexing applications. Refer to Figure 2.
Resistive Loading Errors
Load (Output Device) Characteristics
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
•
Use devices with very low bias current. Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.
•
Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resis-
tance and multiplexer ON resistance. As a guideline, load
impedances of 108Ω, or greater, will keep resistive load-
ing errors to 0.002% or less for 1000Ω source imped-
ances. A 106Ω load impedance will increase source
loading error to 0.2% or more.
•
•
The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
•
Use sources with impedances as low as possible. 1000Ω
source resistance will present less than 0.001% loading
error and 10kΩ source resistance will increase source
loading error to 0.01% with a 108 load impedance.
Load impedances, differential and common-mode, should
be 1010Ω or higher.
IBIAS
RS1
RON
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
VM
Measured
Voltage
IL
Source and Multiplexer Resistive Loading Error
RS8
ROFF
VS1
R
S +RON
(RS +RON) =
×100%
R
S +RON +RL
ZL
VS8
where RS = source resistance
RL = load resistance
FIGURE 1. MPC508A DC Accuracy Equivalent Circuit.
RON = multiplexer ON resistance
RS1
RON1A
IBIAS A
Input Offset Voltage
Cd/2
Cd/2
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC508A, the OFFSET voltage at the output is
determined by:
Rd/2
RCM
IL
VS1
ZL
RS1B
RON1B IBIAS B
RCM1
CCM
Rd/2
RS4A
ROFF4A
VOFFSET = (IB + IL) (RON + RS)
ILB
where IB = Bias current of device multiplexer is driving
IL = Multiplexer leakage current
VS8
RS48
ROFF4B
RON = Multiplexer ON resistance
RS = source resistance
RCM4
FIGURE 2. MPC509A DC Accuracy Equivalent Circuit.
MPC508A, MPC509A
5
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Source Characteristics
RSA
•
The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain-scatter er-
rors. Use sources which do not have large impedance
unbalances if at all possible.
Node A
CdA
RdA
Load
RdB
CSA
RCMS
ZCM
MPC509A
Channel
Source
CSB
•
•
Keep source impedances as low as possible to minimize
resistive loading errors.
Node B
CCMS
CdB
RSB
Minimize ground loops. If signal lines are shielded,
ground all shields to a common point at the system
analog common.
If the MPC509A is used for multiplexing high-level signals
of ±1V to ±10V full-scale ranges, the foregoing precautions
should still be taken, but the parameters are not as critical as
for low-level signal applications.
DYNAMIC CHARACTERISTICS
Settling Time
FIGURE 4. Settling and Common-Mode-Effects—
MPC509A
The gate-to-source and gate-to-drain capacitance of the CMOS
FET switches, the RC time constants of the source and the
load determine the settling time of the multiplexer.
Switching Time
Governed by the charge transfer relation i = C (dV/dt), the
charge currents transferred to both load and source by the
analog switches are determined by the amplitude and rise
time of the signal driving the CMOS FET switches and the
gate-to-drain and gate-to-source junction capacitances as
shown in Figures 3 and 4. Using this relationship, one can see
that the amplitude of the switching transients, seen at the
source and load, decrease proportionally as the capacitance
of the load and source increase. The trade-off for reduced
switching transient amplitude is increased settling time. In
effect, the amplitude of the transients seen at the source and
load are:
This is the time required for the CMOS FET to turn ON after
a new digital code has been applied to the Channel Address
inputs. It is measured from the 50 percent point of the address
input signal to the 90 percent point of the analog signal seen
at the output for a 10V signal change between channels.
Crosstalk
Crosstalk is the amount of signal feedthrough from the three
(MPC509A) or seven (MPC508A) OFF channels appearing
at the multiplexer output. Crosstalk is caused by the voltage
divider effect of the OFF channel, OFF resistance and junc-
tion capacitances in series with the RON and RS impedances
of the ON channel. Crosstalk is measured with a 20Vp-p
1kHz sine wave applied to all OFF channels. The crosstalk
for these multiplexers is shown in the Typical Performance
Curves.
dVL = (i/C) dt
where i = C (dV/dt) of the CMOS FET switches
C = load or source capacitance
The source must then redistribute this charge, and the effect
of source resistance on settling time is shown in the Typical
Performance Curves. This graph shows the settling time for
a 20V step change on the input. The settling time for smaller
step changes on the input will be less than that shown in the
curve.
Common-Mode Rejection (MPC509A Only)
The matching properties of the load, multiplexer and source
affect the common-mode rejection (CMR) capability of a
differentially multiplexed system. CMR is the ability of the
multiplexer and input amplifier to reject signals that are
common to both inputs, and to pass on only the signal
difference to the output. For the MPC509A, protection is
provided for common-mode signals of ±20V above the
power supply voltages with no damage to the analog switches.
MPC508A Channel
Load
Source
Node A
RS
CL
RL
The CMR of the MPC509A and Burr-Brown’s INA110
instrumentation amplifier is 110dB at DC to 10Hz (G = 100)
with a 6dB/octave roll off to 70dB at 1000Hz. This measure-
ment of CMR is shown in the Typical Performance Curves
and is made with a Burr-Brown model INA110 instrumenta-
tion amplifier connected for gains of 10, 100, and 500.
CS
FIGURE 3. Settling Time Effects—MPC508A
MPC508A, MPC509A
6
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Factors which will degrade multiplexer and system DC CMR
are:
AC CMR roll off is determined by the amount of common-
mode capacitances (absolute and mismatch) from each signal
line to ground. Larger capacitances will limit CMR at higher
frequencies; thus, if good CMR is desired at higher frequen-
cies, the common-mode capacitances and unbalance of sig-
nal lines and multiplexer-to-amplifier wiring must be mini-
mized. Use twisted-shielded-pair signal lines wherever pos-
sible.
•
Amplifier bias current and differential impedance mis-
match
•
•
•
Load impedance mismatch
Multiplexer impedance and leakage current mismatch
Load and source common-mode impedance
SWITCHING WAVEFORMS
Typical at +25°C, unless otherwise noted.
BREAK-BEFORE-MAKE DELAY (tOPEN
)
VA Input
2V/Div
MPC508A(1)
In 1
+5V
4.0V
VAM
A2
Address Drive
(VA)
VA
A1 In 2 Thru In 7
A0
1 On
0V
In 8
50Ω
Output
0.5V/Div
Output
VOUT
Out
1kΩ
En
GND
50%
50%
+4.0V
12.5pF
tOPEN
100ns/Div
NOTE: (1) Similar connection for MPC509A.
ENABLE DELAY (tON (EN), tOFF (EN))
Enable Drive
Enable Drive
2V/Div
MPC508A(1)
VAM 4.0V
+10V
In 1
A2
50%
A1
A0
0V
In 2 Thru In 8
Output
90%
90%
Out
1kΩ
En
50Ω
GND
VA
12.5pF
Output
2V/Div
t
ON(EN)
tOFF(EN)
NOTE: (1) Similar connection for MPC509A.
100ns/Div
MPC508A, MPC509A
7
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
Unless otherwise specified: TA = +25, VS = ±15V, VAM = +4V, VAL = 0.8V.
ON RESISTANCE vs ANALOG INPUT SIGNAL,
SUPPLY VOLTAGE
100µA
V2
RON = V2/100µA
In
Out
VIN
NORMALIZED ON RESISTANCE
vs SUPPLY VOLTAGE
ON RESISTANCE vs
ANALOG INPUT VOLTAGE
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
±125°C > TA > –55°C
IN = +5V
TA = +125°C
V
TA = +25°C
TA = –55°C
0.6
±5
±6
±7
±8
±9 ±10 ±11 ±12 ±13 ±14 ±15
Supply Voltage (V)
–10 –8
–6
–4
–2
0
2
4
6
8
10
Analog Input (V)
SUPPLY CURRENT vs TOGGLE FREQUENCY
+15V/+10V
8
6
4
2
0
+ISUPPLY
A
MPC508A(1)
±10V/±5V
±10V/±5V
A2
En
VA
In 2 Thru In 7
In 8
A1
A0
VS = ±15V
50Ω
Out
En
GND –V
VS = ±10V
±10V/±5V
+4V
10MΩ
14pF
A
–ISUPPLY
100
1k
10k
100k
1M
10M
–15V/–10V
Toggle Frequency (Hz)
NOTE: (1) Similar connection for MPC509A.
MPC508A, MPC509A
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
LEAKAGE CURRENT vs TEMPERATURE
En
+0.8V
Out
Out
A
I
D (On)
A
En
A1
ID (Off)
A0
±
10V
±10V
±
±10V
10V
+4.0V
100nA
Off Output
Current
ID (Off)
10nA
1nA
On Leakage
Current ID (On)
Out
IS (Off)
A
±10V
En
Off Input
Leakage Current
IS (Off)
±
+0.8V
10V
100pA
10pA
25
50
75
Temperature (°C)
100
125
NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V.
(Two measurements per device for ID (Off): +10V/–10V and –10V/+10V).
ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
21
18
7
6
5
4
3
2
1
0
Positive Input Overvoltage
15
12
9
IO (Off)
IIN
Analog Input
Current (IIN
A
A
)
+VIN
6
Output Off
Leakage Current
IO (Off)
3
0
+12
+15 +18
+21
+24
+27
+30
+33
+36
Analog Input Overvoltage (V)
21
Negative Input Overvoltage
18
4
2
0
15
12
9
IO (Off)
A
IIN
Analog Input
Current (IIN
A
)
−VIN
6
Output Off
Leakage Current
IO (Off)
3
0
−12
−15 −18
−21
−24
−27
−30
−33
−36
Analog Input Overvoltage (V)
MPC508A, MPC509A
9
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
ACCESS TIME vs LOGIC LEVEL (High)
1000
+15V
+V
900
VREF
800
700
600
500
400
300
In 1
–10V
A2
In 2 Thru
In 7
VA
A1
A0
MPC
50Ω
508A(1)
In 8
Out
+10V
Probe
En
GND –V
+4V
14pF
10MΩ
–15V
3
4
5
6
7
8
9
10 11 12 13 14 15
NOTE: (1) Similar connection for MPC509A.
Logic Level High (V)
ACCESS TIME WAVEFORM
Address
Drive (VA)
VAM
4.0V
VA Input
2V/Div
50%
10V
0V
Output A
10V
90%
Output A
5V/Div
tA
200ns/Div
ON-CHANNEL CURRENT vs VOLTAGE
±14
±12
±10
±8
–55°C
+25°C
+125°C
A
±6
±VIN
±4
±2
0
0
±2
±4
±6
±8
±10
±12
±14
±16
VIN –Voltage Across Switch (V)
MPC508A, MPC509A
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INSTALLATION AND
OPERATING INSTRUCTIONS
The ENABLE input, pin 2, is included for expansion of the
number of channels on a single node as illustrated in Figure
5. With ENABLE line at a logic 1, the channel is selected by
the 2-bit (MPC509A) or 3-bit (MPC508A) Channel Select
Address (shown in the Truth Tables). If ENABLE is at logic
0, all channels are turned OFF, even if the Channel Address
Lines are active. If the ENABLE line is not to be used, simply
In 1
In 2
In 3
Out
8
2
MPC508A
En
+V
In 8
A0 A1 A2
Multiplexer
Output
In 1
MPC508A
Out
Direct
En
+V
In 8
A0 A1 A2
tie it to +VSUPPLY
.
In 1
In 2
In 3
Buffered
OPA602
1/4 OPA404
If the +15V and/or –15V supply voltage is absent or shorted
to ground, the MPC509A and MPC508A multiplexers will
not be damaged; however, some signal feedthrough to the
output will occur. Total package power dissipation must not
be exceeded.
Out
8
2
MPC508A
En
+V
In 8
A0 A1 A2
For best settling speed, the input wiring and interconnections
between multiplexer output and driven devices should be
kept as short as possible. When driving the digital inputs
from TTL, open collector output with pull-up resistors are
recommended
4LSBs 4MSBs
6-Bit Channel
Address Generator
Settling Time to
±0.01% is 20µs
with RS = 100Ω
To preserve common-mode rejection of the MPC509A, use
twisted-shielded pair wire for signal lines and inter-tier
connections and/or multiplexer output lines. This will help
common-mode capacitance balance and reduce stray signal
pickup. If shields are used, all shields should be connected as
close as possible to system analog common or to the com-
mon-mode guard driver.
FIGURE 6. Channel Expansion Up to 64 Channels Using
8 x 8 Two-Tiered Expansion.
Differential Multiplexer (MPC509A)
Single or multitiered configurations can be used to expand
multiplexer channel capacity up to 32 channels using a
32 x 1 or 16 channels using a 4 x 4 configuration.
CHANNEL EXPANSION
Single-Ended Multiplexer (MPC508A)
Single-Node Expansion
Up to 32 channels (four multiplexers) can be connected to a
single node, or up to 64 channels using nine MPC508A
multiplexers on a two-tiered structure as shown in Figures 5
and 6.
The 32 x 1 configuration is simply eight (MPC509A) units
tied to a single node. Programming is accomplished with a
5-bit counter, using the 2LSBs of the counter to control
Channel Address inputs A0 and A1 and the 3MSBs of the
counter to drive a 1-of-8 decoder. The 1-of-8 decoder then is
used to drive the ENABLE inputs (pin 2) of the MPC509A
multiplexers.
In 1
In 2
In 3
Out
MPC
508A
8
2
Group 1
Ch1-8
Group 1
Enable
Multiplexer
Output
In 8
Two-Tier Expansion
A2 A1 A0
Direct
Using a 4 x 4 two-tier structure for expansion to 16 channels,
the programming is simplified. A 4-bit counter output does
not require a 1-of-8 decoder. The 2LSBs of the counter drive
the A0 and A1 inputs of the four first-tier multiplexers and the
2MSBs of the counter are applied to the A0 and A1 inputs of
the second-tier multiplexer.
5-Bit
Binary
Counter
To
Group
2
20
21
22
Buffered
OPA602
1/4 OPA404
23
24
Single vs Multitiered Channel Expansion
A2 A1 A0
To
Group
3
In 1
In 2
In 3
In addition to reducing programming complexity, two-tier
configuration offers the added advantages over single-node
expansion of reduced OFF channel current leakage (reduced
OFFSET), better CMR, and a more reliable configuration if
a channel should fail in the ON condition (short). Should a
channel fail ON in the single-node configuration, data cannot
be taken from any channel, whereas only one channel group
is failed (4 or 8) in the multitiered configuration.
Group 4
Enable
Out
2
MPC
508A
8
In 8
Group 4
Ch25-42
Settling Time to 0.01% for RS < 100Ω
—Two MPC508A units in parallels: 10µs
—Four MPC509 A units in parallels: 12µs
FIGURE 5. 32-Channel, Single-Tier Expansion.
MPC508A, MPC509A
11
SBFS019A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
MPC508AP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
16
16
16
16
16
16
16
16
16
16
16
16
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
MPC508APG4
MPC508AU
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
DW
DW
DW
DW
N
48 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MPC508AU/1K
MPC508AU/1KG4
MPC508AUG4
MPC509AP
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
48 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
MPC509APG4
MPC509AU
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
DW
DW
DW
DW
48 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MPC509AU/1K
MPC509AU/1KG4
MPC509AUG4
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
48 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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