OPA2694 [BB]
Wideband, Low-Power, Current Feedback Operational Amplifier; 宽带，低功耗，电流反馈运算放大器
| 型号： | OPA2694 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Wideband, Low-Power, Current Feedback Operational Amplifier |
| 文件： | 总24页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA694
SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
Wideband, Low-Power, Current Feedback
Operational Amplifier
FD EATURES
DESCRIPTION
The OPA694 is an ultra-wideband, low-power, current
feedback operational amplifier featuring high slew rate and
low differential gain/phase errors. An improved output
stage provides 80mA output drive with < 1.5V output
voltage headroom. Low supply current with > 500MHz
bandwidth meets the requirements of high density video
routers. Being a current feedback design, the OPA694
holds its bandwidth to very high gains—at a gain of 10, the
OPA694 will still provide 200MHz bandwidth.
UNITY GAIN STABLE BANDWIDTH: 1.5GHz
HIGH GAIN OF 2V/V BANDWIDTH: 690MHz
LOW SUPPLY CURRENT: 5.8mA
D
D
D
D
D
HIGH SLEW RATE: 1700V/µsec
HIGH FULL-POWER BANDWIDTH: 675MHz
LOW DIFFERENTIAL GAIN/PHASE:
0.03%/0.0155
D
Pb-FREE AND GREEN SOT23-5 PACKAGE
RF applications can use the OPA694 as a low-power SAW
pre-amplifier. Extremely high 3rd-order intercept is
provided through 70MHz at much lower quiescent power
than many typical RF amplifiers.
AD PPLICATIONS
WIDEBAND VIDEO LINE DRIVER
The OPA694 is available in an industry-standard pinout in
both SO-8 and SOT23-5 packages.
D
D
D
D
MATRIX SWITCH BUFFER
DIFFERENTIAL RECEIVER
ADC DRIVER
+5V
IMPROVED REPLACEMENT FOR OPA658
VIN
Ω
75
VLOAD
RG−59
OPA694
Ω
75
RELATED PRODUCTS
Ω
75
Ω
402
SINGLES
DUALS
OPA2694
OPA2683
OPA2684
OPA2691
OPA2695
TRIPLES
QUADS
FEATURES
Dual Version
—
—
—
OPA683
OPA684
OPA691
OPA695
—
—
OPA4684
—
Low-Power, CFBplus
Low-Power, CFBplus
High Output
Ω
402
−
5V
OPA3684
OPA3691
OPA3695
—
High Intercept
Gain 2V/V Video Line Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2004, Texas Instruments Incorporated
www.ti.com
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
(1)
ABSOLUTE MAXIMUM RATINGS
handledwith appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DC
Internal Power Dissipation . . . . . . . . . See Thermal Characteristics
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Storage Temperature Range: D, DBV . . . . . . . . . −40°C to +125°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
J
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . 1000V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA694ID
OPA694IDR
Rails, 100
OPA694
SO-8
D
−40°C to +85°C
−40°C to +85°C
OPA694
BIA
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
OPA694IDBVT
OPA694IDBVR
OPA694
SOT23-5
DBV
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our website
at www.ti.com.
PIN CONFIGURATIONS
Top View
Top View
1
2
3
5
4
Output
+VS
−
VS
NC
Inverting Input
1
2
3
4
8
7
6
5
NC
Noninverting Input
Inverting Input
+VS
SOT23−5
Noninverting Input
Output
NC
−
VS
SO−8
NC = No Connection
BIA
Pin Orientation/Package Marking
2
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS: V = 5V
S
Boldface limits are tested at +25°C. At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
OPA694ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0°C to
70°C
−40°C to
+85°C
MIN/
MAX LEVEL
TEST
(3)
(2)
(2)
(1)
PARAMETER
CONDITIONS
+25°C
+25°C
UNITS
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
G = +1, V = 0.5V
PP,
R
= 430Ω
= 402Ω
= 318Ω
= 178Ω
= 430Ω
1500
690
250
200
90
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
O
F
G = +2, V = 0.5V
R
350
200
150
340
180
130
330
160
120
O
PP,
PP,
F
G = +5, V = 0.5V
R
F
R
O
G = +10, V = 0.5V
O
PP,
F
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G = +1, V = 0.5V
R
F
O
PP,
V
≤ 0.2V , R = 430Ω
PP
2
O
F
G = +2, V = 2V
675
1700
0.8
20
MHz
V/µs
ns
O
PP
G = +2, 2V Step
1300
1275
1250
Rise Time and Fall Time
Settling Time to 0.01%
to 0.1%
G = +2, V = 0.2V Step
O
G = +2, V = 2V Step
ns
O
G = +2, V = 2V Step
13
ns
O
Harmonic Distortion
2nd-Harmonic
G = +2, f = 5MHz, V = 2V
O
PP
R
= 100Ω
≥ 500Ω
= 100Ω
≥ 500Ω
−68
−92
−72
−93
2.1
−63
−87
−69
−88
2.4
24
−62
−85
−67
−86
2.8
26
−61
−83
−66
−84
3.0
28
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
max
max
max
max
max
max
max
typ
B
B
B
B
B
B
B
C
C
C
C
L
R
L
L
3rd-Harmonic
R
R
L
Input Voltage Noise Density
f > 1MHz
f > 1MHz
f > 1MHz
Inverting Input Current Noise Density
Noninverting Input Current Noise Density
NTSC Differential Gain
22
24
26
28
30
V
= 1.4V , R = 150Ω
PP
0.03
0.05
0.015
0.16
O
L
V
= 1.4V , R = 37.5Ω
%
typ
O
PP
L
NTSC Differential Phase
G = +2, V = 1.4V , R = 150Ω
°
°
typ
O
PP
L
V
= 1.4V , R = 37.5Ω
typ
O
PP
L
(4)
DC PERFORMANCE
Open-Loop Transimpedance
Input Offset Voltage
V
= 0V, R = 100Ω
145
0.5
90
65
60
kΩ
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
O
L
V
V
V
V
V
V
= 0V
= 0V
= 0V
= 0V
= 0V
= 0V
3.0
3.7
12
4.1
15
CM
CM
CM
CM
CM
CM
Average Input Offset Voltage Drift
Non-inverting Input Bias Current
Average Input Bias Current Drift
Inverting Input Bias Current
Average Input Bias Current Drift
µV/°C
µA
nA/°C
µA
5
2
20
18
26
31
100
26
150
38
150
200
nA/°C
INPUT
(5)
Common-mode Input Voltage (CMIR)
2.5
60
2.3
55
2.2
53
2.1
51
V
dB
min
min
typ
A
A
C
C
Common-Mode Rejection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance
V
= 0V
CM
280 1.2
30
kΩ pF
Ω
Open-Loop
No Load
typ
OUTPUT
Voltage Output Voltage
4
3.4
80
3.8
3.1
60
3.7
3.1
58
3.6
3.0
50
V
V
min
min
min
typ
A
A
A
C
C
R
= 100Ω
= 0V
= 0V
L
Output Current
V
V
mA
mA
Ω
O
Short-Circuit Output Current
Closed-Loop Output Impedance
200
0.02
O
G = +2, f =100kHz
typ
(1)
(2)
(3)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical
value only for information.
(4)
(5)
Current is considered positive out of node. V
is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at CMIR limits.
CM
3
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS: V = 5V (continued)
S
Boldface limits are tested at +25°C. At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
OPA694ID, IDBV
TYP
+25°C
5
MIN/MAX OVER TEMPERATURE
0°C to
70°C
−40°C to
+85°C
MIN/
MAX LEVEL
TEST
(3)
(2)
(2)
(1)
+25°C
PARAMETER
POWER SUPPLY
CONDITIONS
UNITS
Specified Operating Voltage
V
V
typ
max
max
max
min
min
C
A
B
A
A
A
Maximum Operating Voltage Range
Minimum Operating Voltage Range
Maximum Quiescent Current
6.3
3.5
6.0
5.6
54
6.3
3.5
6.2
5.3
52
6.3
3.5
6.3
5.0
50
V
V
V
=
=
5V
5V
5.8
5.8
58
mA
mA
dB
S
Minimum Quiescent Current
S
Power-Supply Rejection Ratio (−PSRR)
Input-Referred
THERMAL CHARACTERISTICS
Specification: ID, IDBV
−40 to +85
°C
typ
C
Thermal Resistance q
JA
Junction-to-Ambient
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
DBV SOT-23
(1)
(2)
(3)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical
value only for information.
(4)
(5)
Current is considered positive out of node. V
is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at CMIR limits.
CM
4
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V
S
At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
NONINVERTING SMALL−SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL
FREQUENCY RESPONSE
3
3
0
3
6
9
VO = 0.5VPP
Ω
RL = 100
G = +2V/V
0
3
6
9
Ω
RF = 402
−
−
−
−
−
−
G = +10V/V
G = +5V/V
−
−
−
12
15
18
Ω
RF = 178
Ω
RF = 318
See Figure 1
700
200
−
12
0
400
600
800
1000
0
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
INVERTING LARGE−SIGNAL
FREQUENCY RESPONSE
NONINVERTING LARGE−SIGNAL
FREQUENCY RESPONSE
9
9
6
3
0
VO = 1VPP
G = +2V/V
6
3
0
3
6
9
Ω
RF = 402
VO = 4VPP
VO = 2VPP
VO = 1VPP
VO = 2VPP
−
−
−
−
−
−
3
6
9
VO = 7VPP
−
G = 2V/V
VO = 7VPP
VO = 4VPP
Ω
RF = 402
See Figure 1
200
See Figure 2
−
12
−
12
0
200
400
600
800
1000
0
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
NONINVERTING
INVERTING
PULSE RESPONSE
PULSE RESPONSE
3
2
1
0
0.6
0.4
0.2
0
3
2
1
0
0.6
0.4
0.2
0
−
−
−
−
−
−
−
−
−
−
1
2
3
0.2
0.4
0.6
1
2
3
0.2
0.4
0.6
−
−
Time (5ns/div)
Time (5ns/div)
5
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
HARMONIC DISTORTION
vs LOAD RESISTANCE
HARMONIC DISTORTION
vs SUPPLY VOLTAGE
−
−
−
−
−
−
−
65
70
75
80
85
90
95
−
−
−
−
−
60
65
70
75
80
G = +2V/V
f = 5MHz
G = +2V/V
f = 5MHz
VO = 2VPP
Ω
RL = 100
O = 2VPP
V
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
See Figure 1
See Figure 1
3.5 4.0
−
100
100
1000
4.5
5.0
5.5
6.0
Ω
Load Resistance (
)
Supply Voltage ( VS)
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
HARMONIC DISTORTION
vs FREQUENCY
−
−
−
−
−
65
70
75
80
85
−
−
−
−
−
50
60
70
80
90
G = +2V/V
2nd Harmonic
G = +2V/V
Ω
RL = 100
Ω
RL = 100
f = 5MHz
VO = 2VPP
2nd Harmonic
3rd Harmonic
3rd Harmonic
See Figure 1
See Figure 1
−
100
0.1
1
Output Voltage Swing (VPP
10
0.1
1
10
20
)
Frequency (MHz)
HARMONIC DISTORTION
vs NONINVERTING GAIN
HARMONIC DISTORTION
vs INVERTING GAIN
−
−
−
−
−
−
−
−
60
65
70
75
60
65
70
75
Ω
Ω
RL = 100
f = 5MHz
O = 2VPP
RL = 100
f = 5MHz
O = 2VPP
V
V
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
See Figure 2
See Figure 1
1
10
1
10
Gain (V/V)
Gain (|V/V|)
6
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
INPUT VOLTAGE
2−TONE, 3rd−ORDER
AND CURRENT NOISE
INTERMODULATION INTERCEPT
1k
100
10
55
50
45
40
35
30
25
20
Ω
50
PI
OPA694
PO
50Ω
Ω
50
Ω
402
√
Noninverting Current Noise (24pA/ Hz)
Ω
402
√
Inverting Current Noise (22pA/ Hz)
√
Voltage Noise (2.1nV/ Hz)
1
10
100
1k
10k
100k
1M
10M 100M
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
Frequency (MHz)
RECOMMENDED RS
vs CAPACITIVE LOAD
FREQUENCY RESPONSE
vs CAPACITIVE LOAD
60
50
40
30
20
10
0
3
0
CL = 10pF
CL = 22pF
0dB Peaking Targeted
CL = 100pF
CL = 47pF
−
−
−
3
6
9
RS
VI
OPA694
VO
Ω
50
(1)
CL
1kΩ
Ω
402
−
−
−
12
15
18
402Ω
NOTE: (1) 1k load is optional
Ω
10
100
1M
10M
100M
1G
Capacitive Load (pF)
Frequency (Hz)
COMMON−MODE REJECTION RATIO
AND POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
OPEN−LOOP ZOL
GAIN AND PHASE
120
110
100
90
30
0
70
60
50
40
30
20
10
0
CMRR
+PSRR
−
−
−
−
−
−
−
30
60
< ZOL
80
90
−
PSRR
70
120
150
180
210
20 log |ZOL
|
60
50
40
100
1K
10K
100K
1M
10M
100M
1G
100
1K
10K
100K
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
7
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted.
F
L
VIDEO DIFFERENTIAL GAIN/DIFFERNTIAL PHASE
(No Pulldown)
TYPICAL DC DRIFT
OVER TEMPERATURE
0.08
0.06
0.04
0.02
0
0.16
0.12
0.08
0.04
0
1.0
0.5
0
10
5
dP Positive Video
dG Positive Video
Input Offset Voltage (VOS
)
Left Scale
Inverting Input Bias Current (IBI
Right Scale
)
0
−
−
Noninverting Input Bias Current (IBN
)
dG Negative Video
Right Scale
−
−
0.5
5
dP Negative Video
1.0
10
−
−
25
1
2
3
4
50
0
+25
+50
+75
+100 +125
_
Video Loads
Ambient Temperature ( C)
OUTPUT VOLTAGE
AND CURRENT LIMITATIONS
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
4
3
2
1
0
100
90
80
70
60
50
40
10
1W Internal Power Limit
Sourcing Output Current
Left Scale
9
8
7
6
5
4
Ω
RL = 100
Ω
RL = 50
Output
Current
Limit
Sinking Output Current
Left Scale
Ω
RL = 25
Output
Current
Limit
Supply Current
Right Scale
−
−
−
−
1
2
3
4
1W Internal Power Limit
100 200
−
−
−
−
25
200
100
0
50
0
+25
+50
+75
+100 +125
_
Output Current (mA)
Ambient Temperature ( C)
NONINVERTING
INVERTING
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY
4
8
4
0
4
8
4
2
0
4
Input
Right Scale
Ω
RL = 100
Ω
RL = 100
G = +2V/V
−
G = 1V/V
2
0
2
4
2
0
−
−
Input
Right Scale
Output
Left Scale
Output
Left Scale
−
−
−
−
−
−
2
4
2
4
See Figure 2
See Figure 1
Time (10ns/div)
Time (10ns/div)
8
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
At R = 402Ω, R = 100Ω, and G = 2V/V, unless otherwise noted.
F
L
D
Differential Performance Test Circuit
+5V
DIFFERENTIAL SMALL−SIGNAL
FREQUENCY RESPONSE
3
0
VO = 2VPP
Ω
RL = 400
OPA694
GD = 1
GD = 2
RF = 402
Ω
RF = 430
Ω
RG
RG
RF
RF
−
3
6
9
VI
RL
400
VO
RT
−
−
Ω
GD = 5
RF = 330
Ω
GD = 10
OPA694
Ω
RF = 250
VO
VI
RF
−
12
GD
=
=
RG
0
10
0.1
50 100 150 200 250 300 350 400 450 500
Frequency (MHz)
−
5V
DIFFERENTIAL LARGE−SIGNAL
FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION
vs LOAD RESISTANCE
−
−
−
−
−
−
−
9
6
3
0
3
6
60
65
70
75
80
85
90
VO = 4VPP
f = 5MHz
GD = 2
GD = 2
RL = 400
Ω
3rd Harmonic
VO = 12VPP
VO = 5VPP
VO = 16VPP
−
−
VO = 8VPP
2nd Harmonic
0
50 100 150 200 250 300 350 400 450 500
Frequency (MHz)
100
1000
Ω
Resistance (
)
DIFFERENTIAL DISTORTION
vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION
vs FREQUENCY
−
−
−
−
−
−
−
65
70
75
80
85
90
95
−
−
−
−
−
55
65
75
85
95
GD = 2
f = 5MHz
GD = 2
VO = 4VPP
3rd Harmonic
2nd Harmonic
Ω
RL = 400
Ω
RL = 400
3rd Harmonic
2nd Harmonic
−
105
1
10
100
1
10
20
Output Voltage Swing (VPP
)
Frequency (MHz)
9
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
Figure 2 shows the DC-coupled, gain of −2V/V, dual
power-supply circuit used as the basis of the inverting
Typical Characteristic curves. Inverting operation offers
several performance benefits. Since there is no
common-mode signal across the input stage, the slew rate
for inverting operation is higher and the distortion
performance is slightly improved. An additional input
resistor, RT, is included in Figure 2 to set the input
impedance equal to 50Ω. The parallel combination of RT
and RG sets the input impedance. Both the noninverting
and inverting applications of Figure 1 and Figure 2 will
benefit from optimizing the feedback resistor (RF) value for
bandwidth (see the discussion in Setting Resistor Values
to Optimize Bandwidth). The typical design sequence is to
select the RF value for best bandwidth, set RG for the gain,
then set RT for the desired input impedance. As the gain
increases for the inverting configuration, a point will be
reached where RG will equal 50Ω, where RT is removed
and the input match is set by RG only. With RG fixed to
achieve an input match to 50Ω, RF is simply increased, to
increase gain. This will, however, quickly reduce the
achievable bandwidth, as shown by the inverting gain of
–10 frequency response in the Typical Characteristic
curves. For gains > 10V/V (14dB at the matched load),
noninverting operation is recommended to maintain
broader bandwidth.
APPLICATION INFORMATION
WIDEBAND CURRENT FEEDBACK OPERATION
The OPA694 provides exceptional AC performance for a
wideband, low-power, current-feedback operational
amplifier. Requiring only 5.8mA quiescent current, the
OPA694 offers a 690MHz bandwidth at a gain of +2, along
with a 1700V/µs slew rate. An improved output stage
provides 80mA output drive, along with < 1.5V output
voltage headroom. This combination of low power and
high bandwidth can benefit high-resolution video
applications.
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the 5V
Electrical Characteristic tables and Typical Characteristic
curves. For test purposes, the input impedance is set to
50Ω with a resistor to ground and the output impedance is
set to 50Ω with a series output resistor. Voltage swings
reported in the Electrical Charateristics are taken directly
at the input and output pins, while load powers (dBm) are
defined at a matched 50Ω load. For the circuit of Figure 1,
the total effective load will be 100Ω || 804Ω = 89Ω. One
optional component is included in Figure 1. In addition to
the usual power-supply decoupling capacitors to ground,
a
0.1µF capacitor is included between the two
power-supply pins. In practical PC board layouts, this
optional added capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
+5V
+VS
+
µ
µ
6.8 F
0.1 F
+5V
+VS
Ω
20
µ
µ
0.1 F
6.8 F
Ω
50 Load
+
Ω
50
VO
OPA694
Ω
50 Source
Ω
50 Load
Ω
VO 50
VI
Ω
50
Optional
OPA694
µ
0.01 F
RF
RG
Ω
50 Source
Ω
402
Ω
200
µ
0.1 F
RF
VI
Ω
402
RT
66.5
RG
µ
µ
6.8 F
Ω
0.1 F
+
Ω
µ
µ
0.1 F
402
6.8 F
+
−
VS
−
5V
VS
−
5V
−
Figure 2. DC-Coupled, G = −2V/V, Bipolar-Supply
Specification and Test Circuit
Figure 1. DC-Coupled, G = +2, Bipolar-Supply
Specification and Test Circuit
10
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
gain), wideband inverting summing stages may be
implemented using the OPA694. The circuit in Figure 4
shows an example inverting summing amplifier, where the
resistor values have been adjusted to maintain both
maximum bandwidth and input impedance matching. If
each RF signal is assumed to be driven from a 50Ω source,
the NG for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The
total feedback impedance (from VO to the inverting error
current) is the sum of RF + (RI • NG). where RI is the
impedance looking into the inverting input from the
summing junction (see the Setting Resistor Values to
Optimize Performance section). Using 100Ω feedback (to
get a signal gain of –2 from each input to the output pin)
requires an additional 30Ω in series with the inverting input
to increase the feedback impedance. With this resistor
added to the typical internal RI = 30Ω, the total feedback
impedance is 100Ω + (60Ω • 6) = 460Ω, which is equal to
the required value to get a maximum bandwidth flat
frequency response for NG = 6.
ADC DRIVER
Most modern, high-performance analog-to-digital
converters (ADCs), such as Texas Instruments ADS522x
series, require a low-noise, low-distortion driver. The
OPA694 combines low-voltage noise (2.1nV/√Hz) with low
harmonic distortion. Figure 3 shows an example of a
wideband, AC-coupled, 12-bit ADC driver.
Two OPA694s are used in the circuit of Figure 3 to form a
differential driver for the ADS5220. The two OPA694s offer
> 250MHz bandwidth at a differential gain of 5V/V, with a
2VPP output swing. A 2nd-order RLC filter is used in order
to limit the noise from the amplifier and provide some
attenuation for higher-frequency harmonic distortion.
WIDEBAND INVERTING SUMMING AMPLIFIER
Since the signal bandwidth for a current-feedback op amp
can be controlled independently of the noise gain (NG,
which is normally the same as the noninverting signal
+5V
Power−supply decoupling not shown.
C1
R1
L
Ω
25
OPA694
V+
Ω
Ω
Ω
Ω
100
500
1:2
C
R2
VI
12−Bit
40MSPS
ADS5220
Ω
50
VCM
100
500
µ
0.1 F
R2
C1
Single−to−Differential
Gain of 10
R1
L
−
V
OPA694
Ω
25
−
5V
Figure 3. Wideband, AC-Coupled, Low-Power ADC Driver
+5V
DIS
Ω
50
50
50
50
50
V1
V2
V3
V4
V5
Ω
50
−
VO
=
(V1 + V2 + V3 + V4 + V5)
Ω
Ω
Ω
Ω
OPA694
RG−58
Ω
50
Ω
30
Ω
100
−
100MHz, 1dB Compression = 15dBm
−
5V
Figure 4. 200MHz RF Summing Amplifier
11
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
This circuit removes the peaking by bootstrapping out any
parasitic effects on RG. The input impedance is still set by
RM as the apparent impedance looking into RG is very
high. RM may be increased to show a higher input
impedance, but larger values will start to impact DC output
offset voltage. This circuit creates an additional input offset
voltage as the difference in the two input bias currents
times the impedance to ground at VI. Figure 7 shows a
comparison of small-signal frequency response for the
unity gain buffer of Figure 1 compared to the improved
approach shown in Figure 6. Either approach gives a
low-power unity-gain buffer with > 1.56GHz bandwidth.
SAW FILTER BUFFER
One common requirement in an IF strip is to buffer the
output of a mixer with enough gain to recover the insertion
loss of a narrowband SAW filter. Figure 5 shows one
possible configuration driving a SAW filter. The 2-Tone,
3rd-Order Intermodulation Intercept plot is shown in the
Typical Characteritics curves. Operating in the inverting
mode at a voltage gain of –8V/V, this circuit provides a 50Ω
input match using the gain set resistor, has the feedback
optimized for maximum bandwidth (250MHz in this case),
and drives through a 50Ω output resistor into the matching
network at the input of the SAW filter. If the SAW filter gives
a 12dB insertion loss, a net gain of 0dB to the 50Ω load at
the output of the SAW (which could be the input
impedance of the next IF amplifier or mixer) will be
delivered in the passband of the SAW filter. Using the
OPA694 in this application will isolate the first mixer from
the impedance of the SAW filter and provide very low
two-tone, 3rd-order spurious levels in the SAW filter
bandwidth.
+5V
DIS
RO
Ω
50
VO
OPA694
RF
RG
Ω
430
Ω
430
VI
+12V
RM
Ω
50
−
5V
Ω
Ω
5k
Ω
50
PO
50
Matching
Network
OPA694
5k
µ
1000pF
0.1
F
Figure 6. IF Amplifier Driving SAW Filter
Ω
SAW
Filter
Ω
50
Source
1000pF
Ω
50
400Ω
PO
PI
3
= 12dB − (SAW Loss)
PI
G = +1, Figure 1
0
Figure 5. IF Amplifier Driving SAW Filter
G = +1, Figure 6
−
−
−
3
6
9
WIDEBAND UNITY GAIN BUFFER WITH
IMPROVED FLATNESS
The unity gain buffer configuration of Figure 1 shows a
peaking in the frequency response exceeding 2dB. This
gives the slight amount of overshoot and ringing apparent
in the gain of +1V/V pulse response curves. A similar
circuit that holds a flatter frequency response, giving
improved pulse fidelity, is shown in Figure 6.
−
12
10M
100M
1G
3G
Frequency (MHz)
Figure 7. IF Amplifier Driving SAW Filter
12
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
DESIGN-IN TOOLS
VI
DEMONSTRATION BOARDS
α
Two PC boards are available to assist in the initial
evaluation of circuit performance using the OPA694 in its
two package styles. Both are available free, as
unpopulated PC boards delivered with descriptive
documentation. The summary information for these
boards is shown in Table 1.
VO
RI
Z(S) iERR
iERR
RF
RG
Table 1. Demo Board Listing
LITERATURE
BOARD
PART NUMBER
REQUEST
NUMBER
PRODUCT
OPA694ID
PACKAGE
SO-8
Figure 8. Recommended Feedback Resistor
Versus Noise Gain
DEM-OPA84xD
SBOU026
SBOU027
OPA694IDBV
SOT23-5
DEM-OPA84xDBV
The key elements of this current-feedback op amp model
are:
To request either of these boards, use the Texas
Instruments web site (www.ti.com).
α
→ Buffer gain from the noninverting input to the
inverting input
RI
→ Buffer output impedance
MACROMODELS AND APPLICATIONS SUPPORT
iERR → Feedback error current signal
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the OPA694 is available through the TI
web site (www.ti.com). These models do a good job of
predicting small-signal AC and transient performance
under a wide variety of operating conditions. They do not
do as well in predicting the harmonic distortion or dG/dφ
characteristics. These models do not attempt to
distinguish between package types in their small-signal
AC performance.
Z(s) → Frequency dependent open-loop transimpe-
dance gain from iERR to VO
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It will,
however, set the CMRR for a single op amp differential
amplifier configuration. For a buffer gain α < 1.0, the
CMRR = –20 × log (1– α) dB.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. RI for the OPA694 is typically
about 30Ω.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error
voltage for a voltage-feedback op amp) and passes this on
to the output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show
this open-loop transimpedance response. This is
analogous to the open-loop voltage gain curve for a
voltage-feedback op amp. Developing the transfer
function for the circuit of Figure 8 gives Equation (1):
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
A current-feedback op amp like the OPA694 can hold an
almost constant bandwidth over signal gain settings with
the proper adjustment of the external resistor values. This
is shown in the Typical Characteristic curves; the
small-signal bandwidth decreases only slightly with
increasing gain. Those curves also show that the feedback
resistor has been changed for each gain setting. The
resistor values on the inverting side of the circuit for a
current-feedback op amp can be treated as frequency
response compensation elements while their ratios set
the signal gain. Figure 8 shows the small-signal frequency
response analysis circuit for the OPA694.
RF
RG
ǒ Ǔ
a 1 )
VO
VI
aNG
+
+
RF)RI NG
RF
RG
1 )
R )R 1)
ǒ Ǔ
F
I
Z(S)
1 )
Z(S)
(1)
where:
RF
NG + ǒ1 ) Ǔ
RG
13
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
This is written in a loop-gain analysis format, where the
errors arising from a noninfinite open-loop gain are shown
in the denominator. If Z(S) were infinite over all frequencies,
the denominator of Equation (1) would reduce to 1 and the
ideal desired signal gain shown in the numerator would be
achieved. The fraction in the denominator of Equation (1)
determines the frequency response. Equation (2) shows
this as the loop-gain equation:
450
400
350
300
250
200
150
Z(S)
+ Loop Gain
RF ) RI NG
(2)
If 20 × log(RF + NG × RI) were drawn on top of the
open-loop transimpedance plot, the difference between
the two would be the loop gain at a given frequency.
Eventually, Z(S) rolls off to equal the denominator of
Equation (2), at which point the loop gain reduces to 1 (and
the curves intersect). This point of equality is where the
amplifier closed-loop frequency response given by
Equation (1) starts to roll off, and is exactly analogous to
the frequency at which the noise gain equals the open-loop
voltage gain for a voltage-feedback op amp. The
difference here is that the total impedance in the
denominator of Equation (2) may be controlled somewhat
separately from the desired signal gain (or NG).
0
5
10
15
20
Noise Gain
Figure 9. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting
a series resistor between the inverting input and the
summing junction will increase the feedback impedance
(denominator of Equation (1)), decreasing the bandwidth.
This approach to bandwidth control is used for the
inverting summing circuit on the front page. The internal
buffer output impedance for the OPA694 is slightly
influenced by the source impedance looking out of the
noninverting input terminal. High source resistors will have
the effect of increasing RI, decreasing the bandwidth.
The OPA694 is internally compensated to give a
maximally flat frequency response for RF = 402Ω at
NG = 2 on 5V supplies. Evaluating the denominator of
Equation (2) (which is the feedback transimpedance)
gives an optimal target of 462Ω. As the signal gain
changes, the contribution of the NG × RI term in the
feedback transimpedance will change, but the total can be
held constant by adjusting RF. Equation (3) gives an
approximate equation for optimum RF over signal gain:
OUTPUT CURRENT AND VOLTAGE
The OPA694 provides output voltage and current
capabilities that are not usually found in wideband
amplifiers. Under no-load conditions at 25°C, the output
voltage typically swings closer than 1.2V to either supply
rail; the +25°C swing limit is within 1.2V of either rail. Into
a 15Ω load (the minimum tested load), it is tested to deliver
more than 60mA.
RF + 462W * NG @ RI
(3)
As the desired signal gain increases, this equation will
eventually predict a negative RF. A somewhat subjective
limit to this adjustment can also be set by holding RG to a
minimum value of 20Ω. Lower values will load both the
buffer stage at the input and the output stage, if RF gets too
low, actually decreasing the bandwidth. Figure 9 shows
the recommended RF versus NG for 5V operation. The
values for RF versus gain shown here are approximately
equal to the values used to generate the Typical
Characteristics. They differ in that the optimized values
used in the Typical Characteristics are also correcting for
board parasitics not considered in the simplified analysis
leading to Equation (2). The values shown in Figure 9 give
a good starting point for design where bandwidth
optimization is desired.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage × current, or V−I
product, which is more relevant to circuit operation. Refer
to the Output Voltage and Current Limitations plot in the
Typical Characteristics. The X and Y axes of this graph
show the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The four
quadrants give a more detailed view of the OPA694 output
drive capabilities, noting that the graph is bounded by a
Safe Operating Area of 1W maximum internal power
14
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
dissipation. Superimposing resistor load lines onto the plot
shows that the OPA694 can drive 2.5V into 25Ω or 3.5V
into 50Ω without exceeding the output capabilities or the
1W dissipation limit. A 100Ω load line (the standard test
circuit load) shows the full 3.4V output swing capability,
as shown in the Electrical Charateristics.
The Typical Characteristics show the recommended RS vs
Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA694. Long
PC-board traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add
the recommended series resistor as close as possible to
the OPA694 output pin (see the Board Layout Guidelines
section).
The minimum specified output voltage and current
over-temperature are set by worst-case simulations at the
cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers
shown in the Electrical Characteristic tables. As the output
transistors deliver power, the junction temperatures will
increase, decreasing both VBE (increasing the available
output voltage swing) and increasing the current gains
(increasing the available output current). In steady-state
operation, the available output voltage and current will
always be greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum specified
operating ambient.
DISTORTION PERFORMANCE
The OPA694 provides good distortion performance into a
100Ω load on 5V supplies. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with
a negligible 3rd-harmonic component. Focusing then on
the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network—in the noninverting
configuration (see Figure 1), this is the sum of RF + RG,
while in the inverting configuration it is just RF. Also,
providing an additional supply decoupling capacitor
(0.1µF) between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to 6dB).
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including
additional external capacitance that may be
recommended to improve ADC linearity. A high-speed,
high open-loop gain amplifier like the OPA694 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier open−loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. Several external solutions to this problem
have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at a
little less than the expected 2x rate, while the 3rd-harmonic
increases at a little less than the expected 3x rate. Where
the test power doubles, the 2nd-harmonic increases by
less than the expected 6dB, while the 3rd-harmonic
increases by less than the expected 12dB. This also
shows up in the 2-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels are
extremely low at low output power levels. The output stage
continues to hold them low even as the fundamental power
reaches very high levels. As the Typical Characteristics
show, the spurious intermodulation powers do not
increase as predicted by a traditional intercept model. As
the fundamental power level increases, the dynamic range
does not decrease significantly.
15
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SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
Evaluating these two equations for the OPA694 circuit and
component values (see Figure 1) gives a total output spot
noise voltage of 11.2nV/√Hz and a total equivalent input
spot noise voltage of 5.6nV/√Hz. This total input-referred
spot noise voltage is higher than the 2.1nV/√Hz
specification for the op amp voltage noise alone. This
reflects the noise added to the output by the inverting
current noise times the feedback resistor. If the feedback
resistor is reduced in high-gain configurations (as
suggested previously), the total input-referred voltage
noise given by Equation (5) will approach just the
2.1nV/√Hz of the op amp itself. For example, going to a
gain of +10 using RF = 178Ω will give a total input-referred
noise of 2.36nV/√Hz.
NOISE PERFORMANCE
Wideband, current-feedback op amps generally have a
higher output noise than comparable voltage-feedback op
amps. The OPA694 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. The inverting current noise (24pA/√Hz) is
significantly lower than earlier solutions, while the input
voltage noise (2.1nV/√Hz) is lower than most unity-gain
stable, wideband, voltage-feedback op amps. This low
input voltage noise was achieved at the price of higher
noninverting input current noise (22pA/√Hz). As long as
the AC source impedance looking out of the noninverting
node is less than 100Ω, this current noise will not
contribute significantly to the total output noise. The op
amp input voltage noise and the two input current noise
terms combine to give low output noise under a wide
variety of operating conditions. Figure 10 shows the op
amp noise analysis model with all the noise terms
included. In this model, all noise terms are taken to be
noise voltage or current density terms in either nV/√Hz or
pA/√Hz.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA694 provides
exceptional bandwidth in high gains, giving fast pulse
settling, but only moderate DC accuracy. The Electrical
Characteristics show an input offset voltage comparable to
high-speed, voltage-feedback amplifiers. However, the
two input bias currents are somewhat higher and are
unmatched. Whereas bias current cancellation
techniques are very effective with most voltage-feedback
op amps, they do not generally reduce the output DC offset
for wideband, current-feedback op amps. Since the two
input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of
each input to reduce their error contribution to the output
is ineffective. Evaluating the configuration of Figure 1,
using worst-case +25°C input offset voltage and the two
input bias currents, gives a worst-case output offset range
equal to:
ENI
EO
OPA694
RS
IBN
ERS
RF
√
4kTRS
√
4kTRF
IBI
RG
4kT
RG
4kT = 1.6 10−20 J
at 290K
×
(NG × V
)
(I
× R /2 × NG) (I × R )
S BI F
OS
where NG = noninverting signal gain
(2 × 3mV) (20µA × 25Ω × 2) (402Ω × 18µA)
BN
Figure 10. Op Amp Noise Analysis Model
=
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation (4) shows the general form for the
output noise voltage using the terms shown in Figure 10.
= 6mV + 1mV 7.24mV = 14.24mV
A fine-scale, output offset null, or DC operating point
adjustment, is sometimes required. Numerous techniques
are available for introducing DC offset control into an op
amp circuit. Most simple adjustment techniques do not
correct for temperature drift. It is possible to combine a
lower speed, precision op amp with the OPA694 to get the
DC accuracy of the precision op amp along with the signal
bandwidth of the OPA694. Figure 11 shows a noninverting
G = +10 circuit that holds an output offset voltage less than
) ǒI SǓ2
) ǒI FǓ2
2
2
ǒE
Ǹ
) 4kTR ǓNG
E
+
R
R
) 4kTR NG
NI
BN
BI
F
O
S
(4)
Dividing this expression by the noise gain (NG =
(1 + RF/RG)) will give the equivalent input-referred spot
noise voltage at the noninverting input, as shown in
Equation 6.
7.5mV over-temperature with
bandwidth.
>
150MHz signal
2
+ Ǹ
ǒ
SǓ2
ENI ) IBNR ) 4kTRS
IBIRF
) ǒ Ǔ )
NG
4kTRF
NG
2
EN
(5)
16
ꢂ ꢀꢉ ꢠꢡꢢ
www.ti.com
SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
THERMAL ANALYSIS
+5V
Due to the high output power capability of the OPA694,
heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired junction
temperature will set the maximum allowed internal power
dissipation, as described below. In no case should the
maximum junction temperature be allowed to exceed
150°C.
Power−supply
decoupling not shown.
DIS
VI
VO
OPA694
Ω
1.8k
+5V
−
5V
Ω
180
Ω
Ω
2.86k
OPA237
Operating junction temperature (TJ) is given by TA + PD × θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in
the output stage (PDL) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. PDL will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
Ω
20
−
5V
18k
Ω
2k
2
supplies). Under this condition PDL = VS /(4 × RL) where RL
Figure 11. Wideband, DC-Connected Composite
Circuit
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
This DC-coupled circuit provides very high signal
bandwidth using the OPA694. At lower frequencies, the
output voltage is attenuated by the signal gain and
compared to the original input voltage at the inputs of the
OPA237 (this is a low-cost, precision voltage-feedback op
amp with 1.5MHz gain bandwidth product). If these two do
not agree (due to DC offsets introduced by the OPA694),
the OPA237 sums in a correction current through the
2.86kΩ inverting summing path. Several design
considerations will allow this circuit to be optimized. First,
the feedback to the OPA237 noninverting input must be
precisely matched to the high-speed signal gain. Making
the 2kΩ resistor to ground an adjustable resistor would
allow the low- and high-frequency gains to be precisely
matched. Second, the crossover frequency region where
the OPA237 passes control to the OPA694 must occur with
exceptional phase linearity. These two issues reduce to
designing for pole/zero cancellation in the overall transfer
function. Using the 2.86kΩ resistor will nominally satisfy
this requirement for the circuit in Figure 11. Perfect
cancellation over process and temperature is not possible.
However, this initial resistor setting and precise gain
matching will minimize long-term pulse settling tails.
As a worst-case example, compute the maximum TJ using
an OPA694IDBV (SOT23-5 package) in the circuit of
Figure 1 operating at the maximum specified ambient
temperature of +85°C and driving a grounded 20Ω load to
+2.5V DC:
PD = 10V × 6.0mA + 52/(4 × (20Ω || 804Ω)) = 380mΩ
Maximum TJ = +85°C + (0.38W × (150°C/W) = 142°C
Although this is still below the specified maximum junction
temperature, system reliability considerations may require
lower junction temperatures. Remember, this is a
worst-case internal power dissipation—use your actual
signal and load to compute PDL. The highest possible
internal dissipation will occur if the load requires current to
be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The Output Voltage and Current
Limitations plot shown in the Typical Characteristics
includes a boundary for 1W maximum internal power
dissipation under these conditions.
17
ꢂꢀꢉꢠ ꢡꢢ
www.ti.com
SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
Characteristic tables at a gain of +2 on 5V supplies is a
good starting point for design. Note that a 430Ω feedback
resistor, rather than a direct short, is recommended for the
unity-gain follower application. A current-feedback op amp
requires a feedback resistor even in the unity-gain follower
configuration to control stability.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA694 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the plot of Recommended RS vs
Capacitive Load. Low parasitic capacitive loads (< 5pF)
may not need an RS, since the OPA694 is nominally
compensated to operate with a 2pF parasitic load. If a long
trace is required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line using
microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A
50Ω environment is normally not necessary onboard, and
in fact, a higher impedance environment will improve
distortion, as shown in the Distortion versus Load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA694
is used as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance will be the parallel combination of
the shunt resistor and the input impedance of the
destination device: this total effective impedance should
be set to match the trace impedance. The high output
voltage and current capability of the OPA694 allows
multiple destination devices to be handled as separate
transmission lines, each with their own series and shunt
terminations. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as
a capacitive load in this case and set the series resistor
value as shown in the plot of Recommended RS vs
Capacitive Load. This will not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.
b) Minimize the distance (< 0.25”) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling
capacitor across the two power supplies (for bipolar
operation) will improve 2nd-harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA694. Resistors should be a very
low reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal-film and carbon
composition, axially-leaded resistors can also provide
good high-frequency performance. Again, keep their leads
and PC-board trace length as short as possible. Never use
wirewound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side of the
board between the output and inverting input pins. The
frequency response is primarily determined by the
feedback resistor value, as described previously.
Increasing its value will reduce the bandwidth, while
decreasing it will give a more peaked frequency response.
The 402Ω feedback resistor used in the Electrical
e) Socketing a high-speed part like the OPA694 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA694 onto the board.
18
ꢂ ꢀꢉ ꢠꢡꢢ
www.ti.com
SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (for example,
in systems with 15V supply parts driving into the
OPA694), current-limiting series resistors should be
added into the two inputs. Keep these resistor values as
low as possible, since high values degrade both noise
performance and frequency response.
INPUT AND ESD PROTECTION
The OPA694 is built using
a very high speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins have
limited ESD protection using internal diodes to the power
supplies, as shown in Figure 12.
+VCC
External
Pin
Internal
Circuitry
−
VCC
Figure 12. Internal ESD Protection
19
PACKAGE OPTION ADDENDUM
www.ti.com
21−Sep−2004
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING
PINS
PACKAGE QTY
ECO−STATUS(2)
OPA694ID
OPA694IDR
N/A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO−8
SO−8
D
8
8
5
5
100
2500
250
D
N/A
OPA694DBVR
OPA694DBVT
SOT23
SOT23
DBV
DBV
Pb−Free, Green
Pb−Free, Green
3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime−buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco−Status information Additional details including specific material content can be accessed at www.ti.com/leadfree
GREEN: Ti defines Green to mean Lead (Pb)−Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.
N/A: Not yet available Lead (Pb)−Free; for estimated conversion dates, go to www.ti.com/leadfree.
Pb−FREE: Ti defines Lead (Pb)−Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product
weight, and, if designed to be soldered, suitable for use in specified lead−free soldering processes.
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
OPA694ID
ACTIVE
ACTIVE
SOIC
D
8
5
100
None
CU SNPB
Level-3-260C-168 HR
OPA694IDBVR
SOT-23
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA694IDBVT
OPA694IDR
ACTIVE
ACTIVE
SOT-23
SOIC
DBV
D
5
8
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500
None
CU SNPB
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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