OPA632 [BB]
Low Power, Single-Supply OPERATIONAL AMPLIFIERS TM; 低功耗，单电源运算放大器TM
| 型号： | OPA632 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Low Power, Single-Supply OPERATIONAL AMPLIFIERS TM |
| 文件： | 总17页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPA631
OPA631
OPA632
For most current data sheet and other product
information, visit www.burr-brown.com
TM
Low Power, Single-Supply
OPERATIONAL AMPLIFIERS
DESCRIPTION
FEATURES
The OPA631 and OPA632 are low power, high-speed,
voltage-feedback amplifiers designed to operate on a
single +3V or +5V supply. Operation on ±5V or +10V
supplies is also supported. The input range extends
below ground and to within 1V of the positive supply.
Using complementary common-emitter outputs pro-
vides an output swing to within 30mV of ground and
130mV of the positive supply. The high output drive
current and low differential gain and phase errors also
make them ideal for single-supply consumer video
products.
● HIGH BANDWIDTH: 75MHz (G = +2)
● LOW SUPPLY CURRENT: 6mA
● ZERO POWER DISABLE (OPA632)
● +3V AND +5V OPERATION
● INPUT RANGE INCLUDES GROUND
● 4.8V OUTPUT SWING ON +5V SUPPLY
● HIGH SLEW RATE: 100V/µs
● LOW INPUT VOLTAGE NOISE: 6nV/√HZ
● AVAILABLE IN SOT23 PACKAGE
Low distortion operation is ensured by the high gain
bandwidth (68MHz) and slew rate (100V/µs), making
the OPA631 and OPA632 ideal input buffer stages to
3V and 5V CMOS converters. Unlike other low power,
single-supply amplifiers, distortion performance im-
proves as the signal swing is decreased. A low 6nV
input voltage noise supports wide dynamic range op-
eration. Channel multiplexing or system power reduc-
tion can be achieved using the high speed disable line.
Power dissipation can be reduced to zero by taking the
disable line High.
APPLICATIONS
● SINGLE SUPPLY ADC INPUT BUFFER
● SINGLE SUPPLY VIDEO LINE DRIVER
● CCD IMAGING CHANNELS
● LOW POWER ULTRASOUND
● PLL INTEGRATORS
● PORTABLE CONSUMER ELECTRONICS
The OPA631 and OPA632 are available in an industry-
standard SO-8 package. The OPA631 is also available
in an ultra-small SOT23-5 package, while the OPA632
is available in the SOT23-6. Where higher full-power
bandwidth and lower distortion are required in a single-
supply operational amplifier, consider the OPA634
and OPA635.
+3V
Disable
2.26kΩ
+3V
374Ω
Pwrdn
22pF
DIS
VIN
100Ω
ADS901
10-Bit
20Msps
OPA632
RELATED PRODUCTS
SINGLES
DUALS
562Ω
750Ω
Medium Speed, No Disable
With Disable
OPA631
OPA632
OPA2631
—
High Speed, No Disable
With Disable
OPA634
OPA635
OPA2634
—
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1377A
Printed in U.S.A. June, 1999
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
OPA631U, N
OPA632U, N
TYP
GUARANTEED
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25°C
+25°C
70°C
+85°C
UNITS MAX LEVEL(1)
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
75
16
7.6
68
50
12
5.6
51
—
64
8.0
7.5
28
40
6.8
2.6
—
40
10
4.2
40
—
52
11
10
38
38
7.6
2.9
—
32
8.5
3.7
36
—
47
12.8
11.6
42
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz max
pA/√Hz max
%
min
min
min
min
typ
min
max
max
max
min
B
B
B
B
C
B
B
B
B
B
B
B
C
C
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
VO ≤ 0.5Vp-p
G = +2, 2V Step
0.5V Step
5
100
5.3
5.4
17
0.5V Step
G = +2, 1V Step
VO = 2Vp-p, f = 5MHz
f > 1MHz
42
35
6.0
1.9
0.5
1.2
7.9
3.6
—
f > 1MHz
typ
—
—
—
degrees typ
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
62
2.5
—
11
0.3
—
56
6
—
21
1
50
8
—
27
1.3
—
46
11
50
40
2
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
B
B
B
VCM = 2.0V
VCM = 2.0V
Input Offset Current
Input Offset Current Drift
—
7
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
–0.5
4.0
74
–0.1
3.7
70
–0.1
3.7
68
–0.1
3.5
60
V
V
dB
max
min
min
B
A
A
Input Referred
Differential-Mode
Common-Mode
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || pF typ
kΩ || pF typ
C
C
OUTPUT
Least Positive Output Voltage
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
0.03
0.16
4.87
4.60
80
90
100
0.2
0.06
0.17
4.8
4.4
25
38
—
—
0.09
0.20
4.7
4.4
20
24
—
—
0.12
1.7
4.6
3.1
5
10
—
—
V
V
V
max
max
min
min
min
min
typ
B
A
B
A
A
A
C
C
Most Positive Output Voltage
V
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
mA
mA
mA
Ω
G = +2, f ≤ 100kHz
typ
DISABLE (OPA632 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
1.0
3.7
70
0
1.0
3.8
110
—
20
—
1.0
4.0
120
—
25
—
1.0
4.2
120
—
30
—
V
V
min
max
max
typ
max
typ
A
A
A
C
A
C
C
C
µA
µA
µA
ns
ns
dB
0
100
60
70
Enable Time
Off Isolation
—
—
—
—
—
—
typ
typ
f = 5MHz, Input to Output
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
—
—
6
6
59
2.7
10.5
6.4
5.8
52
2.7
10.5
6.7
5.5
49
2.7
10.5
6.9
4.8
48
V
V
mA
mA
dB
min
max
max
min
min
A
A
A
A
A
VS = +5V
VS = +5V
Input Referred
THERMAL CHARACTERISTICS
Specification: U, N
–40 to +85
°C
typ
C
Thermal Resistance
U
N
SO-8
SOT23-5, SOT23-6
125
150
°C/W
°C/W
typ
typ
C
C
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
®
2
OPA631, OPA632
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
OPA631U, N
OPA632U, N
TYP
GUARANTEED
0
°
C to
MIN/ TEST
MAX LEVEL(1)
PARAMETER
CONDITIONS
+25°C
+25°C
70°C
UNITS
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
61
15
7.7
63
5
95
5.6
5.6
40
44
6.2
2.0
45
11
4.6
47
—
52
9
35
9
4.0
34
—
46
11.3
11.3
85
34
7.8
2.9
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz
pA/√Hz
min
min
min
min
typ
min
max
max
max
min
max
max
B
B
B
B
C
B
B
B
B
B
B
B
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
VO ≤ 0.5Vp-p
1V Step
0.5V Step
0.5V Step
1V Step
9
63
37
7.0
2.6
VO = 1Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
60
0.5
—
12
0.3
—
54
3.5
—
21
1
50
4
45
26
1.3
2
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
B
B
B
VCM = 1.0V
VCM = 1.0V
Input Offset Current
Input Offset Current Drift
—
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
–0.5
2
72
–0.3
1.75
66
–0.1
1.3
65
V
V
dB
max
min
min
B
A
A
Input Referred
Differential-Mode
Common-Mode
10 || 2.1
400 || 1.2
—
—
—
—
kΩ || p
kΩ || p
typ
typ
C
C
OUTPUT
Least Positive Output Voltage
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
0.03
0.05
2.95
2.85
55
55
80
0.2
0.05
0.15
2.85
2.66
21
21
—
—
0.05
0.16
2.84
2.60
14
14
—
—
V
V
V
max
max
min
min
min
min
typ
A
A
A
A
A
A
C
C
Most Positive Output Voltage
V
Current Output, Sourcing
Current Output, Sinking
Short Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
mA
mA
mA
Ω
Figure 2, f < 100kHz
typ
DISABLE (OPA632 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
1.0
1.7
66
0
1.0
1.8
100
—
20
—
1.0
1.8
110
—
25
—
V
V
min
max
max
typ
max
typ
A
A
A
C
A
C
C
C
µA
µA
µA
ns
ns
dB
0
100
60
70
Enable Time
Off Isolation
—
—
—
—
typ
typ
f = 5MHz, Input to Output
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
—
—
5.3
5.3
57
2.7
10.5
5.7
5.0
50
2.7
10.5
6.2
4.8
48
V
V
mA
mA
dB
min
max
max
min
min
A
A
A
A
A
VS = +3V
VS = +3V
Input Referred
THERMAL CHARACTERISTICS
Specification: U, N
–40 to +85
°C
typ
C
Thermal Resistance
U
N
SO-8
SOT23-5, SOT23-6
125
150
°C/W
°C/W
typ
typ
C
C
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.
®
3
OPA631, OPA632
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from perfor-
mancedegradationtocompletedevicefailure. Burr-BrownCorpo-
rationrecommendsthatallintegratedcircuitsbehandledandstored
using appropriate ESD protection methods.
Power Supply ................................................................................ +11VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range.................................................... –0.5 to +VS + 0.3V
Storage Temperature Range: P, U, N ...........................–40°C to +125°C
Lead Temperature (soldering, 10s).............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PIN CONFIGURATIONS
Top View—OPA631, OPA632
SO-8
NC
Inverting Input
Non-Inverting Input
GND
1
2
3
4
8
7
6
5
DIS (OPA632 only)
+VS
Output
NC
Top View—OPA631
SOT23-5
Top View—OPA632
SOT23-6
Output
GND
1
2
3
6
5
4
+VS
Output
GND
1
2
3
6
4
+VS
DIS
Non-Inverting Input
Inverting Input
Non-Inverting Input
Inverting Input
A32
A31
Pin Orientation/Package Marking
Pin Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
OPA631U
SO-8 Surface-Mount
182
"
331
"
–40°C to +85°C
OPA631U
OPA631U
Rails
"
OPA631N
"
"
"
"
A31
"
OPA631U/2K5
OPA631N/250
OPA631N/3K
Tape and Reel
Tape and Reel
Tape and Reel
5-Lead SOT23-5
–40°C to +85°C
"
"
OPA632U
SO-8 Surface-Mount
182
"
332
"
–40°C to +85°C
OPA632U
OPA632U
Rails
"
OPA632N
"
"
"
"
A32
"
OPA632U/2K5
OPA632N/250
OPA632N/3K
Tape and Reel
Tape and Reel
Tape and Reel
6-Lead SOT23-6
–40°C to +85°C
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces of “OPA632N/3K” will get a single 3000-
piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
4
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 200mVp-p
LARGE-SIGNAL FREQUENCY RESPONSE
VO = 0.2Vp-p
6
3
12
9
G = +2
0
6
–3
3
–6
0
–9
–3
–6
–9
–12
–15
–18
VO = 1Vp-p
VO = 2Vp-p
G = +5
–12
–15
–18
–21
–24
G = +10
VO = 4Vp-p
1
10
100
300
1
10
100
300
Frequency (MHz)
Frequency (MHz)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
VO = 200mVp-p
VO = 4Vp-p
VO
VO
VIN
VIN
Time (10ns/div)
Time (10ns/div)
DISABLE FEEDTHROUGH vs FREQUENCY
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
VDIS
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
OPA632 Only
VDIS = +5V
VO
VIN = 0.5V
OPA632 Only
1
10
100
Frequency (MHz)
1000
Time (50ns/div)
®
5
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
1MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
1MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
RL = 500Ω
RL = 250Ω
RL = 150Ω
RL = 250Ω
RL = 150Ω
0.1
1
4
0.1
1
4
Output Voltage (Vp-p)
Output Voltage (Vp-p)
5MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
5MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
RL = 250Ω
RL = 500Ω
RL = 250Ω
RL = 150Ω
RL = 150Ω
RL = 500Ω
0.1
1
4
0.1
1
4
Output Voltage (Vp-p)
Output Voltage (Vp-p)
10MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
10MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
RL = 500Ω
RL = 250Ω
RL = 150Ω
RL = 500Ω
RL = 250Ω
RL = 150Ω
0.1
1
4
0.1
1
4
Output Voltage (Vp-p)
Output Voltage (Vp-p)
®
6
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
2nd HARMONIC DISTORTION vs FREQUENCY
3rd HARMONIC DISTORTION vs FREQUENCY
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
VO = 2Vp-p
RL = 150Ω
VO = 2Vp-p
RL = 150Ω
G = +2
G = +5
G = +10
G = +2
G = +5
G = +10
0.1
1
Frequency (MHz)
10
0.1
1
10
Frequency (MHz)
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2Vp-p
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
fO = 10MHz
f
O = 5MHz
3rd Harmonic Distortion
fO = 5MHz
2nd Harmonic Distortion
Load Power at
Matched 50Ω Load
fO = 1MHz
–16
–14
–12
–10
–8
–6
–4
–2
0
100
200
300
400
500
Single-Tone Load Power (dBm)
RL (Ω)
CMRR AND PSRR vs FREQUENCY
CMRR
INPUT NOISE DENSITY vs FREQUENCY
80
75
70
65
60
55
50
45
40
35
30
100
10
1
PSRR
Voltage Noise, eni = 6.0nV/√Hz
Current Noise, ini = 1.9pA/√Hz
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
®
7
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 1000pF
1000
100
10
2
1
CL = 10pF
0
–1
–2
–3
–4
–5
–6
–7
–8
CL = 100pF
RS
OPA63x
VO
CL
1kΩ
+VS/2
1
1
10
100
1000
1
10
Frequency (MHz)
100
300
Capacitive Load (pF)
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
Open-Loop Phase
100
90
80
70
60
50
40
30
20
10
0
0
–30
100
10
1
G = +1
R
F = 25Ω
–60
–90
–120
–150
–180
–210
–240
–270
–300
–330
–360
Open-Loop Gain
–10
–20
0.1
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
POWER SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
INPUT DC ERRORS vs TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20
18
16
14
12
10
8
12
10
8
120
Sinking Output Current
Sourcing Output Current
100
80
60
40
20
0
Input Offset Voltage
6
Quiescent Supply Current
Input Bias Current
4
6
10X Input Offset Current
4
2
2
0
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
®
8
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 200mVp-p
LARGE-SIGNAL FREQUENCY RESPONSE
6
3
12
9
G = +2
VO = 200mVp-p
0
6
–3
3
G = +5
–6
0
–9
–3
–6
–9
–12
–15
–18
VO = 1Vp-p
–12
–15
–18
–21
–24
VO = 2Vp-p
G = +10
1
10
Frequency (MHz)
100
300
1
10
Frequency (MHz)
100
300
3rd HARMONIC DISTORTION vs FREQUENCY
2nd HARMONIC DISTORTION vs FREQUENCY
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
VO = 1Vp-p
RL = 150Ω
VO = 1Vp-p
RL = 150Ω
G = +2
G = +5
G = +2
G = +5
G = +10
G = +10
0.1
1
Frequency (MHz)
10
0.1
1
10
Frequency (MHz)
TWO-TONE, 3rd-ORDER
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 1Vp-p
INTERMODULATION SPURIOUS
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
fO = 10MHz
f
O = 5MHz
3rd Harmonic Distortion
fO = 5MHz
2nd Harmonic Distortion
fO = 1MHz
Load Power at
Matched 50Ω Load
100
200
300
400
500
–16
–14
–12
–10
–8
–6
–4
RL (Ω)
Single-Tone Load Power (dBm)
®
9
OPA631, OPA632
TYPICAL PERFORMANCE CURVES: VS = +3V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
VO = 0.2Vp-p
1000
100
10
6
3
CL = 10pF
CL = 1000pF
0
–3
–6
CL = 100pF
–9
–12
–15
–18
–21
–24
RS
OPA63x
VO
CL
1kΩ
+VS/2
1
1
50
3
10
100
1000
1
10
Frequency (MHz)
100
300
Capacitive Load (pF)
SUPPLY AND OUTPUT CURRENTS
vs SUPPLY VOLTAGE
OUTPUT SWING vs LOAD RESISTANCE
Maximum VO
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.0
10
9
8
7
6
5
4
3
2
1
0
200
180
160
140
120
100
80
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Quiescent Supply Current
Output Current, Sinking
60
40
Output Current, Sourcing
Minimum VO
20
0
100
1000
3
4
5
6
7
8
9
10
RL (Ω)
Supply Voltage (V)
SLEW RATE AND GAIN BANDWIDTH PRODUCT
vs SUPPLY VOLTAGE
120
100
80
60
40
20
0
120
100
80
60
40
20
0
Slew Rate
Gain Bandwidth Product
4
5
6
7
8
9
10
Supply Voltage (V)
®
10
OPA631, OPA632
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
+VS = 3V
6.8µF
The OPA631 and OPA632 are unity-gain stable, very high-
speed, voltage-feedback op amps designed for single-supply
operation (+3V to +5V). The input stage supports input
voltages below ground, and within 1.0V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 30mV of ground and
130mV of the positive supply. They are compensated to
provide stable operation with a wide range of resistive loads.
The OPA632’s internal disable circuitry is intended to mini-
mize system power when disabled.
+
0.1µF
+
2.26kΩ
374Ω
VIN
DIS (OPA632 only)
VOUT
57.6Ω
OPA63x
RL
150Ω
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150Ω || 1500Ω. The disable pin
(OPA635 only) needs to be driven by a low impedance
source, such as a CMOS inverter. The 1.50kΩ resistors at
the non-inverting input provide the common-mode bias
voltage. Their parallel combination equals the DC resistance
at the inverting input, minimizing the output DC offset.
562Ω
750Ω
+VS
2
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
SINGLE-SUPPLY ADC CONVERTER INTERFACE
The front page shows a DC-coupled, single-supply ADC
driver circuit. Many systems are now requiring +3V supply
capability of both the ADC and its driver. The OPA632
provides excellent performance in this demanding applica-
tion. Its large input and output voltage ranges, and low
distortion, support converters such as the ADS901 shown in
this figure. The input level-shifting circuitry was designed
so that VIN can be between 0V and 0.5V, while delivering an
output voltage of 1V to 2V for the ADS901. Both the
OPA632 and ADS901 have power reduction pins with the
same polarity for those systems that need to conserve power.
+VS = 5V
6.8µF
+
0.1µF
+
1.50kΩ
1.50kΩ
0.1µF
VIN
DIS (OPA632 only)
VOUT
53.6Ω
OPA63x
RL
150Ω
DC LEVEL SHIFTING
Figure 3 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount VOUT needs to be shifted up (∆VOUT) when VIN is at
the center of its range, the following equations give the
resistor values that produce the best DC offset.
0.1µF
750Ω
750Ω
+VS
2
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
NG = G + ∆VOUT/VS
R1 = R4/G
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Though not strictly a “rail-to-rail”
design, these parts come very close, while maintaining
excellent performance. They will deliver ≈ 2.9Vp-p on a
single +3V supply with 61MHz bandwidth. The 374Ω and
2.26kΩ resistors at the input level-shift VIN so that VOUT is
within the allowed output voltage range when VIN = 0. See
the Typical Performance Curves for information on driving
capacitive loads.
R2 = R4/(NG – G)
R3 = R4/(NG –1)
where:
NG = 1 + R4/R3 (Noise Gain)
VOUT = (G)VIN + (NG – G)VS
Make sure that VIN and VOUT stay within the specified input
and output voltage ranges.
®
11
OPA631, OPA632
A unity gain buffer can be designed by selecting RT = RF =
20.0Ω and RC = 40.2Ω (do not use RG). This gives a Noise
Gain of 2, so its response will be similar to the Characteris-
tics Plots with G = +2 which typically gives a flat frequency
response, but with less bandwidth.
+VS
R2
R1
VIN
DESIGN-IN TOOLS
VOUT
OPA63x
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA631 and OPA632 in
their three package styles. These are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
below:
R3
R4
FIGURE 3. DC Level-Shifting Circuit.
BOARD
PART
NUMBER
LITERATURE
REQUEST
NUMBER
The front page circuit is a good example of this type of
application. It was designed to take VIN between 0V and
0.5V, and produce VOUT between 1V and 2V, when using a
+3V supply. This means G = 2.00, and ∆VOUT = 1.50V – G
• 0.25V = 1.00V. Plugging into the above equations gives:
NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The
resistors were changed to the nearest standard values.
PRODUCT
PACKAGE
OPA63xU
OPA63xN
8-Pin SO-8
5-Pin SOT23-5
6-Pin SOT23-6
DEM-OPA68xU
DEM-OPA6xxN
MKT-351
MKT-348
Contact the Burr-Brown Applications support line to request
any of these boards.
NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Figure 4 shows a non-inverting amplifier that reduces peak-
ing at low gains. The resistor RC compensates the OPA631
or OPA632 to have higher Noise Gain (NG), which reduces
the AC response peaking (typically 5dB at G = +1 without
RC) without changing the DC gain. VIN needs to be a low
impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both RT and RF helps
minimize the impact of parasitic impedances.
Since the OPA631 and OPA632 are voltage feedback op
amps, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 25Ω resistor, not a direct short (see
Figure 4). This will isolate the inverting input capacitance
from the output pin and improve the frequency response
flatness. Usually, for G > 1 application, the feedback resistor
value should be between 200Ω and 1.5kΩ. Below 200Ω, the
feedback network will present additional output loading
which can degrade the harmonic distortion performance.
Above 1.5kΩ, the typical parasitic capacitance (approxi-
mately 0.2pF) across the feedback resistor may cause unin-
tentional band-limiting in the amplifier response.
RT
VIN
RC
VOUT
OPA63x
RG
RF
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 1) to be less than approximately 400Ω.
The combined impedance RF || RG interacts with the invert-
ing input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, hold-
ing RF || RG <400Ω will keep this pole above 130MHz. By
itself, this constraint implies that the feedback resistor RF
can increase to several kΩ at high gains. This is acceptable
as long as the pole formed by RF and any parasitic capaci-
tance appearing in parallel is kept out of the frequency range
of interest.
FIGURE 4. Compensated Non-Inverting Amplifier.
The Noise Gain can be calculated as follows:
RF
G1 = 1+
RG
RT + RF / G1
G2 = 1+
RC
NG = G1G2
®
12
OPA631, OPA632
BANDWIDTH VS GAIN: NON-INVERTING OPERATION
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90°, as it
does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA631 and
OPA632 are compensated to give a slightly peaked response
in a non-inverting gain of 2 (Figure 1). This results in a
typical gain of +2 bandwidth of 75MHz, far exceeding that
predicted by dividing the 68MHz GBP by 2. Increasing the
gain will cause the phase margin to approach 90° and the
bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +10, the 7.6MHz bandwidth shown
in the Typical Specifications is close to that predicted using
the simple formula and the typical GBP.
+5V
+
0.1µF
6.8µF
2RT
523Ω
DIS
RO
50Ω
OPA63x
0.1µF
2RT
523Ω
50Ω Load
50Ω
Source
RG
374Ω
RF
750Ω
RM
57.6Ω
The OPA631 and OPA632 exhibit minimal bandwidth re-
duction going to +3V single supply operation as compared
with +5V supply. This is because the internal bias control
circuitry retains nearly constant quiescent current as the total
supply voltage between the supply pins is changed.
FIGURE 5. Gain of –2 Example Circuit.
load. In general, the feedback resistor should be limited to
the 200Ω to 1.5kΩ range. In this case, it is preferable to
increase both the RF and RG values as shown in Figure 5, and
then achieve the input matching impedance with a third
resistor (RM) to ground. The total input impedance becomes
the parallel combination of RG and RM.
INVERTING AMPLIFIER OPERATION
Since the OPA631 and OPA632 are general purpose,
wideband voltage feedback op amps, all of the familiar op
amp application circuits are available to the designer. Figure
5 shows a typical inverting configuration where the I/O
impedances and signal gain from Figure 1 are retained in an
inverting circuit configuration. Inverting operation is one of
the more common requirements and offers several perfor-
mance benefits. The inverting configuration shows improved
slew rate and distortion. It also allows the input to be biased
at VS/2 without any headroom issues. The output voltage can
be independently moved to be within the output voltage
range with coupling capacitors, or bias adjustment resistors.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 5, the RM value
combines in parallel with the external 50Ω source imped-
ance, yielding an effective driving impedance of 50Ω ||
576Ω = 26.8Ω. This impedance is added in series with RG
for calculating the noise gain. The resultant is 2.87 for
Figure 5, as opposed to only 2 if RM could be eliminated as
discussed above. The bandwidth will therefore be lower for
the gain of –2 circuit of Figure 5 (NG = +3) than for the
gain of +2 circuit of Figure 1.
In the inverting configuration, three key design consider-
ation must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), RG
may be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to
50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This has the interesting
advantage that the noise gain becomes equal to 2 for a 50Ω
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100Ω feedback resistor in parallel with the external
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on
the non-inverting input (a parallel combination of RT =
263Ω). If this resistor is set equal to the total DC resistance
looking out of the inverting node, the output DC error, due
to the input bias currents, will be reduced to (Input Offset
Current) • RF. If the 50Ω source impedance is DC-coupled
in Figure 5, the total resistance to ground between the
inverting input and the source will be 401Ω. Combining
this in parallel with the feedback resistor gives the RT =
263Ω used in this example. To reduce the additional high
frequency noise introduced by this resistor, and power
supply feedthrough, RT is bypassed with a capacitor. As
long as RT < 400Ω, its noise contribution will be minimal.
As a minimum, the OPA631 and OPA632 require an RT
®
13
OPA631, OPA632
value of 50Ω to damp out parasitic-induced peaking—a
direct short to ground on the non-inverting input runs the
risk of a very high frequency instability in the input stage.
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a gain of
+2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring rela-
tively high values of RS to flatten the response at the load.
Increasing the noise gain will also reduce the peaking (see
Figure 4).
OUTPUT CURRENT AND VOLTAGE
The OPA631 and OPA632 provide outstanding output volt-
age capability. Under no-load conditions at +25°C, the
output voltage typically swings closer than 130mV to either
supply rail; the guaranteed swing limit is within 400mV of
either rail (VS = +5V).
DISTORTION PERFORMANCE
The OPA631 and OPA632 provide good distortion perfor-
mance into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads and/or
operating on a single +3V supply. Generally, the 3rd har-
monic will dominate the distortion. Focusing then on the 3rd
harmonic, increasing the load impedance improves distor-
tion directly. Remember that the total load includes
the feedback network; in the non-inverting configuration
(Figure 1) this is sum of RF + RG, while in the inverting
configuration, it is just RF.
The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
NOISE PERFORMANCE
High slew rate, unity gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 6.0nV/√Hz input voltage noise for
the OPA631 and OPA632 is, however, much lower than
comparable amplifiers. The input-referred voltage noise,
and the two input-referred current noise terms (1.9pA/√Hz),
combine to give low output noise under a wide variety of
operating conditions. Figure 6 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or
current density terms in either nV/√Hz or pA/√Hz.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA631 and OPA632 can be very suscep-
tible to decreased stability and closed-loop response peaking
when a capacitive load is placed directly on the output pin.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 6.
ENI
EO
OPA63x
RS
IBN
ERS
The Typical Performance Curves show the recommended
RS versus capacitive load and the resulting frequency re-
sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA631
and OPA632. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this value.
Always consider this effect carefully, and add the recom-
mended series resistor as close as possible to the output pin
(see Board Layout Guidelines).
RF
√4kTRS
√4kTRF
IBI
RG
4kT
RG
4kT = 1.6 • 10–20
J
at 290°K
FIGURE 6. Noise Analysis Model.
®
14
OPA631, OPA632
Equation 1:
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
2
2
2
EO
=
ENI + IBNRS + 4kTRS NG2 + IBIRF + 4kTRFNG
(
)
(
)
(
)
Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
DISABLE OPERATION
Equation 2:
The OPA632 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. To disable, the con-
trol pin must be asserted HIGH. Figure 7 shows a simplified
internal circuit for the disable control feature.
2
IBIRF
NG
4kTRF
2
2
EN
=
ENI + IBNRS + 4kTRS +
+
(
)
NG
Evaluating these two equations for the circuit and compo-
nent values shown in Figure 1 will give a total output spot
noise voltage of 13.1nV/√Hz and a total equivalent input
spot noise voltage of 6.6nV/√Hz. This is including the noise
added by the resistors. This total input-referred spot noise
voltage is not much higher than the 6.0nV/√Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
400Ω, and the input attenuation is low. Since the resistor-
induced noise is relatively negligible, additional capacitive
decoupling across the bias current cancellation resistor (RT)
for the inverting op amp configuration of Figure 5 is not
required.
In normal operation, base current to Q1 is provided through
the DIS pin and the 50kΩ resistor.
+VS
Q1
DC ACCURACY AND OFFSET CONTROL
IS Control
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA631
and OPA632 gives even tighter control than comparable
products. Although the high-speed input stage does require
relatively high input bias current (typically 11µA out of each
input terminal), the close matching between them may be
used to reduce the output DC error caused by this current.
This is done by matching the DC source resistances appear-
ing at the two inputs. Evaluating the configuration of Figure
1 (which has matched DC input resistances), using worst-
case +25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to: (NG = non-
inverting signal gain at DC)
50kΩ
VDIS
FIGURE 7. Simplified Disable Control Circuit (OPA632).
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. Adding a simple RC filter into the DIS
pin from a higher speed logic line will reduce the glitch. If
extremely fast transition logic is used, a 1kΩ series resistor
will provide adequate band limiting using just the parasitic
input capacitance on the DIS pin while still ensuring ad-
equate logic level swing.
±(NG • VOS(MAX)) ± (RF • IOS(MAX)
)
= ±(1 • 6.0mV) ± (750Ω • 2.0µA)
= ±6.8mV = Output Offset Range for Figure 1
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path is
intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
THERMAL ANALYSIS
Maximum desired junction temperature will set the maxi-
mum allowed internal power dissipation as described below.
In no case should the maximum junction temperature be
allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD•θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
®
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OPA631, OPA632
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for resistive load
connected to mid-supply (VS/2), be at a maximum when the
output is fixed at a voltage equal to VS/4 or 3VS/4. Under this
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance.
Resistors should be a very low reactance type. Surface-
mount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high frequency performance. Again,
keep their leads and PC board traces as short as possible.
Never use wirewound type resistors in a high frequency
application. Since the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close as
possible to the output pin. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package. Where double-side component
mounting is allowed, place the feedback resistor directly
under the package on the other side of the board between the
output and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, excessively high
resistor values can create significant time constants that can
degrade performance. Good axial metal film or surface-
mount resistors have approximately 0.2pF in shunt with the
resistor. For resistor values > 1.5kΩ, this parasitic capaci-
tance can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. The
750Ω feedback used in the typical performance specifica-
tions is a good starting point for design. See Figure 4 for the
unity gain follower application.
2
condition, PDL = VS /(16 • RL), where RL includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA632 (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a 150Ω load at mid-supply.
PD = 10V • 6.9mA + 52/(16 • (150Ω || 1500Ω)) = 80mW
Maximum TJ = +85°C + (0.08W • 150°C/W) = 97°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
BOARD LAYOUT GUIDELINES
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA631 and OPA632 are nominally compensated to oper-
ate with a 2pF parasitic load. Higher parasitic capacitive
loads without an RS are allowed as the signal gain increases
(increasing the unloaded phase margin) If a long trace is
required, and the 6dB signal loss intrinsic to a doubly
terminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environ-
ment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a character-
istic board trace impedance defined (based on board mate-
rial and trace dimensions), a matching series resistor into the
trace from the output of the OPA631 and OPA632 is used
as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. If the 6dB attenuation of a doubly termi-
Achieving optimum performance with a high frequency
amplifier like the OPA631 and OPA632 requires careful
attention to board layout parasitics and external component
types. Recommendations that will optimize performance
include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
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OPA631, OPA632
nated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value
as shown in the plot of Recommended RS vs Capacitive
Load. This will not preserve signal integrity as well as a
doubly terminated line. If the input impedance of the desti-
nation device is low, there will be some signal attenuation
due to the voltage divider formed by the series output into
the terminating impedance.
INPUT AND ESD PROTECTION
The OPA631 and OPA632 are is built using a very high
speed complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are pro-
tected with internal ESD protection diodes to the power
supplies as shown in Figure 8.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA631 and OPA632), current-limit-
ing series resistors should be added into the two inputs. Keep
these resistor values as low as possible since high values
degrade both noise performance and frequency response.
e) Socketing a high speed part is not recommended. The
additional lead length and pin-to-pin capacitance introduced
by the socket can create an extremely troublesome parasitic
network which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained
by soldering the OPA631 and OPA632 onto the board.
+VCC
External
Pin
Internal
Circuitry
–VCC
FIGURE 8. Internal ESD Protection.
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OPA631, OPA632
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