PCM1702P-JG4 [BB]
BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER; BiCMOS高级注册幅度20位数字 - 模拟转换器
| 型号： | PCM1702P-JG4 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总13页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PCM1702P
PCM1702U
BiCMOS Advanced Sign Magnitude 20-Bit
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● ULTRA LOW –96dB max THD+N
The PCM1702 is a precision 20-bit digital-to-analog
converter with ultra-low distortion (–96dB typ with a
full scale output). Incorporated into the PCM1702 is
an advanced sign magnitude architecture that elimi-
nates unwanted glitches and other nonlinearities around
bipolar zero. The PCM1702 also features a very low
noise (120dB typ SNR: A-weighted method) and fast
settling current output (200ns typ, 1.2mA step) which
is capable of 16X oversampling rates.
(No External Adjustment Required)
● NEAR-IDEAL LOW LEVEL OPERATION
● GLITCH-FREE OUTPUT
● 120dB SNR TYP (A-Weight Method)
● INDUSTRY STD SERIAL INPUT FORMAT
● FAST (200ns) CURRENT OUTPUT
(±1.2mA)
Applications include very low distortion frequency
synthesis and high-end consumer and professional
digital audio applications.
● CAPABLE OF 16X OVERSAMPLING
● COMPLETE WITH REFERENCE
● LOW POWER (150mW typ)
Clock
Data
LE
Input Shift Register
and Control Logic
Balanced Current
Segment DAC A
DCOM
ACOM
+VCC
Balanced Current
IOUT
Segment DAC B
Reference
and
–VCC
Servo
Bipolar Offset
BPO DC
RF DC SERV DC
International Airport Industrial Park
•
Mailing Address: PO Box 11400
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111
•
Twx: 910-952-1111
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1993 Burr-Brown Corporation
PDS-1175B
Printed in U.S.A. June, 1995
SBAS026
SPECIFICATIONS
All specifications at 25°C, ±VCC and +VDD = ±5V unless otherwise noted.
PCM1702P/U, -J, -K
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Bits
RESOLUTION
20
DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight
110
dB
DIGITAL INPUT
Logic Family
Logic Level: VIH
VIL
TTL/CMOS Compatible
+2.4
0
+VDD
0.8
V
V
IIH
IIL
VIH = +VDD
VIL = 0V
±10
±10
µA
µA
Data Format
Serial, MSB First, BTC(1)
12.5
Input Clock Frequency
20.0
MHz
TOTAL HARMONIC DISTORTION + N(2)
P/U
VO = 0dB
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
fS = 352.8kHz(3), f = 1002Hz(4)
–92
–82
–46
–96
–83
–48
–100
–84
–50
–88
–74
–40
–92
–76
–42
–96
–80
–44
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
V
V
V
V
V
V
V
O = –20dB
O = –60dB
O = 0dB
O = –20dB
O = –60dB
O = 0dB
P/U, -J
P/U, -K
O = –20dB
O = –60dB
ACCURACY
Level Linearity
Gain Error
At –90dB Signal Level
±0.5
±0.5
±0.25
±25
±5
dB
%
%
±3
Bipolar Zero Error(5)
Gain Drift
0°C to 70°C
0°C to 70°C
ppm of FSR/°C
ppm of FSR/°C
minute
Bipolar Zero Drift
Warm-up Time
1
IDLE CHANNEL SNR(6)
Bipolar Zero, A-weighted Filter
110
120
dB
ANALOG OUTPUT
Output Range
Output Impedance
Settling Time
±1.2
1.0
200
mA
kΩ
ns
(±0.003% of FSR, 1.2mA Step)
Glitch Energy
No Glitch Around Zero
POWER SUPPLY REQUIREMENTS
Supply Voltage Range: +VCC = +VDD
–VCC = –VDD
Combined Supply Current: +ICC
Combined Supply Current: –ICC
Power Dissipation
+4.75
–4.75
+5.00
–5.00
+5.00
–25.00
150
+5.25
–5.25
+9.0
–41.0
250
V
V
mA
mA
mW
+VCC = +VDD = +5V
–VCC = –VDD = –5V
±VCC = ±VDD = ±5V
TEMPERATURE RANGE
Operating
Storage
–25
–55
+85
+125
°C
°C
NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling).
(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5kΩ feedback and an A-weighted filter.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
PCM1702
ABSOLUTE MAXIMUM RATINGS (DIP Package)
ABSOLUTE MAXIMUM RATINGS (SOP Package)
PowerSupply Voltage .................................................................. ±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V
Operating Temperature..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation .......................................................................... 500mW
Lead Temperature (soldering, 10s) .................................................. 260°C
Power Supply Voltage .................................................................. ±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V
Operating Temperature..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation .......................................................................... 300mW
Lead Temperature (soldering, 5s) .................................................... 260°C
PIN ASSIGNMENTS (DIP Package)
PIN ASSIGNMENTS (SOP Package)
PIN
MNEMONIC
PIN
MNEMONIC
PIN
MNEMONIC
PIN
MNEMONIC
1
2
3
4
5
6
7
8
DATA
CLOCK
+VDD
DCOM
–VDD
LE
9
+VCC
BPO DC
IOUT
ACOM
ACOM
SERV DC
REF DC
–VCC
1
2
3
4
5
6
7
8
9
DATA
CLOCK
NC
+VDD
DCOM
–VDD
LE
NC
NC
NC
11
12
13
14
15
16
17
18
19
20
+VCC
BPO DC
NC
10
11
12
13
14
15
16
IOUT
ACOM
ACOM
SERV DC
NC
RFE DC
–VCC
NC
NC
10
PACKAGE INFORMATION(1)
PACKAGE DRAWING
NUMBER
GRADE MARKING (SOP Package)
MODEL
PACKAGE
MODEL
PACKAGE
PCM1702P
PCM1702U
16-Pin Plastic DIP
20-Pin Plastic SOP
180
248
PCM1702U
PCM1702U-J
PCM1702U-K
Marked PCM1702.
Marked with white dot by pin 10.
Marked with red dot by pin 10.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
CONNECTION DIAGRAM
47µF
+
–5V VCC
2
1
7
4
5
6
2
1
6
3
4
5
CLOCK
DATA
LE
16 20
15 19
14 17
11 14
10 12
22µF
100µF
+
+
RNF
+5V VDD
VOUT
+
+
47µF
+
47µF
47µF
+5V VCC
–5V VDD
9
11
+
47µF
13 16
12 15
= SOP
= DIP
®
3
PCM1702
TYPICAL PERFORMANCE CURVES
All specifications at 25°C, ±VA and ±VD = ±5.0V unless otherwise noted.
16-BIT LEVEL LINEARITY
(Dithered Fade-to-Noise)
THD+N vs FREQUENCY
–40
8
6
–60dB
–60
4
–40dB
2
–80
0
–20dB
–2
–4
–6
–8
–100
0dB
–120
20
100
1k
10k
–120
–110
–100
–90
–80
–70
–60
Output Frequency (Hz)
Output Signal Level (dB)
–90dB SIGNAL SPECTRUM
(100Hz Bandwidth)
16-BIT MONOTONICITY
1.5
1
–80
–100
–120
–140
–160
0.5
0
–0.5
–1
–1.5
8.83ms/div
0
4k
8k
12k
16k
20k
Frequency (Hz)
–90dB SIGNAL
–110dB SIGNAL
(10Hz to 20kHz Bandwidth)
(10Hz to 20kHz Bandwidth)
200
100
0
40
20
0
–100
–200
–20
–40
0
400
800
1200
1600
2000
0
400
800
1200
1600
2000
Time (µs)
Time (µs)
®
4
PCM1702
THEORY OF OPERATION
ADVANCED SIGN MAGNITUDE
DISCUSSION OF
SPECIFICATIONS
Digital audio systems have traditionally used laser-trimmed,
current-source DACs in order to achieve sufficient accuracy.
However, even the best of these suffer from potential low-
level nonlinearity due to errors at the major carry bipolar
zero transition. More recently, DACs employing a different
architecture which utilizes noise shaping techniques and
very high over-sampling frequencies, have been introduced
(“Bitstream”, “MASH”, or 1-bit DAC). These DACs over-
come the low level linearity problem, but only at the expense
of signal-to-noise performance, and often to the detriment of
channel separation and intermodulation distortion if the
succeeding circuitry is not carefully designed.
DYNAMIC SPECIFICATIONS
Total Harmonic Distortion + Noise
The key specifications for the PCM1702 is total harmonic
distortion plus noise (THD+N).
Digital data words are read into the PCM1702 at eight times
the standard compact disk audio sampling frequency of
44.1kHz (352.8kHz) so that a sine wave output of 1002Hz
is realized.
For production testing, the output of the DAC goes to an
I to V converter, then through a 40kHz low pass filter, and
then to a programmable gain amplifier to provide gain at
lower signal output test levels before being fed into an
analog-type distortion analyzer. Figure 1 shows a block
diagram of the production THD+N test setup.
The PCM1702 is a new solution to the problem. It combines
all the advantages of a conventional DAC (excellent full
scale performance, high signal-to-noise ratio and ease of
use) with superior low-level performance. Two DACs are
combined in a complementary arrangement to produce an
extremely linear output. The two DACs share a common
reference, and a common R-2R ladder for bit current sources
by dual balanced current segments to ensure perfect tracking
under all conditions. By interleaving the individual bits of
each DAC and employing precise laser trimming of resis-
tors, the highly accurate match required between DACs is
achieved.
For the audio bandwidth, THD+N of the PCM1702 is
essentially flat for all frequencies. The typical performance
curve, “THD+N vs Frequency”, shows four different output
signal levels: 0dB, –20dB, –40dB, and –60dB. The test
signals are derived from a special compact test disk (the
CBS CD-1). It is interesting to note that the –20dB signal
falls only about 10dB below the full scale signal instead of
the expected 20dB. This is primarily due to the superior low
level signal performance of the advanced sign magnitude
architecture of the PCM1702.
This new, complementary linear or advanced sign magni-
tude approach, which steps away from zero with small steps
in both directions, avoids any glitching or “large” linearity
errors and provides an absolute current output. The low level
performance of the PCM1702 is such that real 20-bit reso-
lution can be realized, especially around the critical bipolar
zero point.
In terms of signal measurement, THD+N is the ratio of
DistortionRMS + NoiseRMS/ SignalRMS expressed in dB. For the
PCM1702, THD+N is 100% tested at all three specified
output levels using the test setup shown in Figure 1. It is
significant to note that this test setup does not include any
output deglitching circuitry. All specifications are achieved
without the use of external deglitchers.
Table 1 shows the conversion made by the internal logic of
the PCM1702 from binary two’s complement (BTC). Also,
the resulting internal codes to the upper and lower DACs
(see front page block diagram) are listed. Notice that only
the LSB portions of either internal DAC are changing
around bipolar zero. This accounts for the superlative per-
formance of the PCM1702 in this area of operation.
Dynamic Range
Dynamic range in audio converters is specified as the mea-
sure of THD+N at an effective output signal level of –60dB
referred to 0dB. Resolution is commonly used as a theoreti-
cal measure of dynamic range, but it does not take into
account the effects of distortion and noise at low signal
levels. The advanced sign magnitude architecture of the
PCM1702, with its ideal performance around bipolar zero,
provides a more usable dynamic range, even using the strict
audio definition, than any previously available D/A con-
verter.
INPUT CODE
LOWER DAC CODE
UPPER DAC CODE
ANALOG OUTPUT
(20-bit Binary Two's Complement)
(19-bit Straight Binary)
(19-bit Straight Binary)
+Full Scale
011...111
011...110
000...010
000...001
000...000
111...111
111...110
100...001
100...000
111...111+1LSB(1)
111...111+1LSB(1)
111...111+1LSB(1)
111...111+1LSB(1)
111...111+1LSB(1)
111...111
111...111
111...110
000...010
000...001
000...000
000...000
000...000
000...000
000...000
+Full Scale –1LSB
Bipolar Zero +2LSB
Bipolar Zero +1LSB
Bipolar Zero
Bipolar Zero –1LSB
Bipolar Zero –2LSB
–Full Scale +LSB
–Full Scale
111...110
000...001
000...000
NOTE: (1) The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.
TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart.
®
5
PCM1702
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Programmable
Gain Amp
0dB to 60dB
Low-Pass Filter
40kHz 3rd Order
GIC Type
Distortion
Analyzer
Meter Settings
(Shiba Soku Model
725 or Equivalent)
I to V
Converter
OPA627
DATA
Binary
Counter
Digital Code
(EPROM)
Parallel-to-Serial
Conversion
DUT
(PCM1702)
CLOCK
LE (Latch Enable)
Sampling Rate = 44.1kHz x 8(352.8kHz)
Output Frequency = 1002Hz
Timing
Logic
FIGURE 1. Production THD+N Test Setup.
Level Linearity
Monotonicity
Deviation from ideal versus actual signal level is sometimes
called “level linearity” in digital audio converter testing. See
the “–90dB Signal Spectrum” plot in the Typical Perfor-
mance Curves section for the power spectrum of a PCM1702
at a –90dB output level. (The “–90dB Signal” plot shows the
actual –90dB output of the DAC). The deviation from ideal
for PCM1702 at this signal level is typically less than
±0.3dB. For the “–110dB Signal” plot in the Typical Perfor-
mance Curves section, true 20-bit digital code is used to
generate a –110dB output signal.
Because of the unique advanced sign magnitude architecture
of the PCM1702, increasing values of digital input will
always result in increasing values of DAC output as the
signal moves away from bipolar zero in one-LSB steps (in
either direction). The “16-bit Monotonicity” plot in the
Typical Performance Curves section was generated using
16-bit digital code from a test compact disk. The test starts
with 10 periods of bipolar zero. Next are 10 periods of
alternating 1LSBs above and below zero, and then 10
periods of alternating 2LSBs above and below zero, and so
on until 10LSBs above and below zero are reached. The
signal pattern then begins again at bipolar zero.
This type of performance is possible only with the low-
noise, near-theoretical performance around bipolar zero of
the PCM1702 advanced sign magnitude.
With PCM1702, the low-noise steps are clearly defined and
increase in near-perfect proportion. This performance is
achieved without any external adjustments. By contrast,
sigma-delta (“Bit-stream”, “MASH”, or 1-bit DAC) archi-
tectures are too noisy to even see the first 3 or 4 bits change
(at 16 bits), other than by a change in the noise level.
A commonly tested digital audio parameter is the amount of
deviation from ideal of a 1kHz signal when its amplitude is
decreased form –60dB to –120dB. A digitally dithered input
signal is applied to reach effective output levels of
–120dB using only the available 16-bit code from a special
compact disk test input. See the “16-bit Level Linearity” plot
in the Typical Performance Curves section for the results of
a PCM1702 tested using this 16-bit dithered fade-to-noise
signal. Note the very small deviation from ideal as the signal
goes from –60dB to –100dB.
Absolute Linearity
Even though absolute integral and differential linearity specs
are not given for the PCM1702, the extremely low THD+N
performance is typically indicative of 17-bit integral linearity
in the DAC. The relationship between THD+N and linearity,
however, is not such that an absolute linearity specification
for every individual output code can be guaranteed.
DC SPECIFICATION
Offset, Gain, and Temperature Drift
Idle Channel SNR
Although the PCM1702 is primarily meant for use in dy-
namic applications, specifications are also given for more
traditional DC parameters such as gain error, bipolar zero
offset error, and temperature gain and offset drift.
Another appropriate specification for a digital audio con-
verter is idle channel signal-to-noise ratio (idle channel
SNR). This is the ratio of noise on the DAC output at bipolar
zero in relation to the full scale range of the DAC. To make
this measurement, the digital input is continuously fed the
code for bipolar zero, while the output of the DAC is band-
limited from 20Hz to 20kHz and an A-weighted filter is
applied. The idle channel SNR for the PCM1702 is typically
greater than 120dB, making it ideal for low-noise applica-
tions.
DIGITAL INPUT
Timing Considerations
The PCM1702 accepts TTL compatible logic input levels.
The data format of the PCM1702 is binary two’s comple-
ment (BTC) with the most significant bit (MSB) being first
®
6
PCM1702
in the serial input bit stream. Table II describes the exact
relationship of input data to voltage output coding. Any
number of bits can precede the 20 bits to be loaded, since
only the last 20 will be transferred to the parallel DAC
register after Latch Enable (Pin6 <PCM1702P>, Pin7
<PCM1702U>, LE) has gone low.
INSTALLATION
POWER SUPPLIES
Refer to CONNECTION DIAGRAM for proper connection
of the PCM1702. The PCM1702 only requires a ±5V sup-
ply. Both positive supplies should be tied together at a single
point. Similarly, both negative supplies should be connected
together. No real advantage is gained by using separate
analog and digital supplies. It is more important that both
these supplies be as “clean” as possible to reduce coupling
of supply noise to the output. Power supply decoupling
capacitors should be used at each supply pin to maximize
power supply rejection, as shown in CONNECTION DIA-
GRAM regardless of how good the supplies are. Both
commons should be connected to an analog ground plane as
close to the PCM1702 as possible.
All DAC serial input data (Pin1, DATA) bit transfers are
triggered on positive clock (Pin2, CLOCK), edges. The
serial-to-parallel data transfer to the DAC occurs on the
falling edge of Latch Enable. The change in the output of the
DAC occurs at a rising edge of the 4th clock of the CLOCK
after the falling edge of Latch Enable. Refer to Figure 2 for
graphical relationships of these signals.
Maximum Clock Rate
A typical clock rate of 16.9MHz for the PCM1702 is derived
by multiplying the standard audio sample rate of 44.1kHz by
sixteen times (16X over-sampling) the standard audio word
bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note
that this clock rate accommodates a 24-bit word length, even
though only 20 bits are actually being used. The setup and
hold timing relationships are shown in Figure 3.
FILTER CAPACITOR REQUIREMENTS
As shown in CONNECTION DIAGRAM, various size
decoupling capacitors can be used, with no special tolerances
being required. The size of the offset decoupling capacitor is
not critical either, with larger values (up to 100µF) giving
slightlybetterSNRreadings.Allcapacitorsshouldbeasclose
to the appropriate pins of the PCM1702 as possible to reduce
noise pickup from surrounding circuitry.
“Stopped Clock” Operation
The PCM1702 is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 20 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
Latch Enable goes low. Latch Enable must remain low until
after the first clock cycle of the next data word to insure
proper DAC operation. In any case, the setup and hold times
for Data and LE must be observed as shown in Figure 3.
> 40ns
Data Input
LSB
MSB
> 15ns > 15ns
Clock
Input
> 20ns
> 20ns
DIGITAL INPUT
ANALOG OUTPUT
CURRENT OUTPUT
1,048,576LSBs
1LSB
7FFFFHEX
00000HEX
80000HEX
Full Scale Range
NA
+Full Scale
Bipolar Zero –1LSB
–Full Scale
2.40000000mA
2.28882054nA
–1.19999771mA
0.00000000mA
+1.20000000mA
> 15ns
Latch
Enable
> 15ns
> One Clock Cycle
> One Clock Cycle
TABLE II. Digital Input/Output Relationships.
FIGURE 3. Setup and Hold Timing Diagram.
Clock
DATA "N"
1
2
3
4
12 13 14 15 16 17 18 19 20
1
Data
MSB
LSB
Latch
Enable
IOUT
N-1
N
NOTES : (1) If clock is stopped between input of 20-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 20-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable
(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative. (5)
IOUT changes on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).
FIGURE 2. Timing Diagram.
®
7
PCM1702
φ
FIGURE 4. Typical Application for Stereo Audio 8X Oversampling system.
®
8
PCM1702
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2007
PACKAGING INFORMATION
Orderable Device
PCM1702P
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
16
16
16
16
16
20
20
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
PCM1702P-J
PCM1702P-JG4
PCM1702P-K
PCM1702PG4
PCM1702U
PDIP
PDIP
PDIP
PDIP
SO
N
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
NS
NS
38
Pb-Free
(RoHS)
CU SNBI
Level-2-260C-1 YEAR
PCM1702U-J
SO
38
Pb-Free
(RoHS)
CU SNBI
Level-2-260C-1 YEAR
PCM1702U-J/2KE6
PCM1702U-JE6
ACTIVE
ACTIVE
SO
SO
NS
NS
20
20
TBD
Call TI
Call TI
38
38
Pb-Free
(RoHS)
CU SNBI
Level-2-260C-1 YEAR
PCM1702U-K
ACTIVE
SO
NS
20
Pb-Free
(RoHS)
CU SNBI
Level-2-260C-1 YEAR
PCM1702U-K/2KE6
PCM1702U-KE6
ACTIVE
ACTIVE
SO
SO
NS
NS
20
20
TBD
Call TI
Call TI
38
2000
2000
38
Pb-Free
(RoHS)
CU SNBI
Level-2-260C-1 YEAR
PCM1702U/2K
PCM1702U/2KE6
PCM1702UE6
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
20
20
20
Pb-Free
(RoHS)
CU SNBI
CU SNBI
CU SNBI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2007
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
PCM1702U/2K
NS
20
SITE 49
330
25
8.8
13.1
2.8
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
PCM1702U/2K
NS
20
SITE 49
0.0
0.0
0.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
PCM1702P/PCM1702U
PCM1702P. PCM1702U - BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
BB
PCM1702U-J/2K
D/A Converter, 1 Func, Serial Input Loading, 0.2us Settling Time, PDSO20, ROHS COMPLIANT, PLASTIC, SOP-20
BB
PCM1702U-K/2K
D/A Converter, 1 Func, Serial Input Loading, 0.2us Settling Time, PDSO20, ROHS COMPLIANT, PLASTIC, SOP-20
BB
©2020 ICPDF网 联系我们和版权申明