PGA103U [BB]

Programmable Gain AMPLIFIER; 可编程增益放大器


型号：	PGA103U
厂家：	BURR-BROWN CORPORATION
描述：	Programmable Gain AMPLIFIER 可编程增益放大器放大器
文件：	总7页 (文件大小：122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PGA103

Programmable Gain

AMPLIFIER

FEATURES

● DIGITALLY PROGRAMABLE GAINS:

DESCRIPTION

The PGA103 is a programmable-gain amplifier for

general purpose applications. Gains of 1, 10, or 100 are

digitally selected by two CMOS/TTL-compatible in-

puts. The PGA103 is ideal for systems that must

handle wide dynamic range signals.

G=1, 10, 100V/V

● CMOS/TTL-COMPATIBLE INPUTS

● LOW GAIN ERROR: ±0.05% max, G=10

● LOW OFFSET VOLTAGE DRIFT: 2µV/°C

● LOW QUIESCENT CURRENT: 2.6mA

● LOW COST

The PGA103’s high speed circuitry provides fast set-

tling time, even at G=100 (8µs to 0.01%). Bandwidth

is 250kHz at G=100, yet quiescent current is only

2.6mA. It operates from ±4.5V to ±18V power

supplies.

● 8-PIN PLASTIC DIP, SO-8 PACKAGES

The PGA103 is available in 8-pin plastic DIP and

SO-8 surface-mount packages, specified for the –40°C

to +85°C temperature range.

APPLICATIONS

● DATA ACQUISITION SYSTEMS

● GENERAL PURPOSE ANALOG BOARDS

● MEDICAL INSTRUMENTATION

V+

V–

V_O

PGA103

V_IN

V_O= G • V_IN

GAIN

A₁

A₀

100

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

Telex: 066-6491

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (520) 746-1111 Twx: 910-952-1111

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1208B

Printed in U.S.A. November, 1993

PGA103

SPECIFICATIONS

ELECTRICAL

T_A= +25°C, V_S= ±15V, R_L= 2kΩ unless otherwise specified.

PGA103P, U

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

INPUT

Offset Voltage, RTI

G = 1

T_A= +25°C

±200

±100

±1500

±500

µV

G = 10

G = 100

vs Temperature

G = 1

G = 10

T_A= T_MINto T_MAX

±5

±2

µV/°C

G = 100

vs Power Supply

G = 1

G = 10

G = 100

Impedance

V_S= ±4.5V to ±18V

µV/V

10⁸|| 2

Ω || pF

INPUT BIAS CURRENT

Initial Bias Current

vs Temperature

±50

±100

±150

pA/°C

NOISE VOLTAGE, RTI

f = 10Hz

f = 100Hz

f = 1kHz

f_B= 0.1Hz to 10Hz

G = 100, R_S= 0Ω

0.6

nV/√Hz

µVp-p

NOISE CURRENT

f = 10Hz

f = 1kHz

2.8

0.3

pA/√Hz

pAp-p

f_B= 0.1Hz to 10Hz

GAIN

Gain Error

G = 1

G = 10

G = 100

Gain vs Temperature

G = 1

±0.005

±0.02

±0.04

±0.02

±0.05

±0.2

±2

±10

±30

ppm/°C

G = 10

G = 100

Nonlinearity

G = 1

G = 10

G = 100

±0.001

±0.002

±0.004

±0.003

±0.005

±0.01

% of FSR

OUTPUT

Voltage, Positive

Negative

Load Capacitance, max

Short-Circuit Current

(V+) –3.5

(V–) +3.5

(V+) –2.5

(V–) +2.5

1000

±25

FREQUENCY RESPONSE

Bandwidth, –3dB

G = 1

G = 10

G = 100

1.5

750

250

MHz

kHz

V/µs

Slew Rate

V_O= ±10V

Settling Time, 0.1%

G = 1

G = 10

2.2

6.5

µs

G = 100

Settling Time, 0.01%

G = 1

G = 10

G = 100

Overload Recovery

2.5

µs

50% Overdrive

2.5

DIGITAL LOGIC INPUTS

Digital Low Voltage

Digital Low or High Current

Digital High Voltage

–5.6

0.8

V+

µA

PGA103

SPECIFICATIONS (CONT)

ELECTRICAL

T_A= +25°C, V_S= ±15V, R_L= 2kΩ unless otherwise specified.

PGA103P, U

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

POWER SUPPLY

Voltage Range

Current

±4.5

±15

±2.6

±18

±3.5

V_IN= 0V

TEMPERATURE RANGE

Specification

Operating

–40

+85

+125

°C

θ_JA: P or U Package

100

°C/W

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ................................................................................. ±18V

Analog Input Voltage Range ..................................................... V– to V+

Logic Input Voltage Range ........................................................ V– to V+

Output Short Circuit (to ground) ............................................ Continuous

Operating Temperature ................................................ –40°C to +125°C

Storage Temperature .................................................... –40°C to +125°C

Junction Temperature ...................................................................+150°C

Lead Temperature (soldering,10s) .............................................. +300°C

Top View

DIP/SO-8

A₀

V+

A₁

Ground

V_IN

V_O

V–

PACKAGE INFORMATION

PACKAGE DRAWING

MODEL

PACKAGE

NUMBER⁽¹⁾

ORDERING INFORMATION

PGA103P

PGA103U

8-Pin Plastic DIP

SO-8 Surface-Mount

006

182

MODEL

PACKAGE

TEMPERATURE RANGE

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

PGA103P

PGA103U

8-Pin Plastic DIP

SO-8 Surface-Mount

–40°C to +85°C

ELECTROSTATIC

DISCHARGE SENSITIVITY

Any integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with ap-

propriate precautions. Failure to observe proper handling and

installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet published speci-

fications.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

PGA103

DICE INFORMATION

PAD

FUNCTION

A₀

A₁

Ground

V_IN

3A, 3B, 3C⁽¹⁾

4A, 4B, 4C⁽²⁾

V–

V_O

V+

NC: No Connection

NOTES: (1) Connect all three indicated pads. (2) Connect

all three indicated pads.

Substrate Bias: Internally connected to V– power supply.

MECHANICAL INFORMATION

MILS (0.001")

MILLIMETERS

Die Size

Die Thickness

Min. Pad Size

69 x 105 ±5

20 ±3

1.75 x 2.67 ±0.13

0.51 ±0.08

4 x 4

0.1 x 0.1

PGA103 DIE TOPOGRAPHY

Backing

Gold

TYPICAL PERFORMANCE CURVES

T_A= +25°C, V_S= ±15V unless otherwise noted.

VOLTAGE GAIN vs FREQUENCY

POWER SUPPLY REJECTION vs FREQUENCY

120

100

G=100

G=10

G=1

–10

10k

100k

Frequency (Hz)

10M

100

10k

100k

Frequency (Hz)

PGA103

TYPICAL PERFORMANCE CURVES (CONT)

T_A= +25°C, V_S= ±15V unless otherwise noted.

INPUT CURRENT NOISE vs FREQUENCY

INPUT VOLTAGE NOISE vs FREQUENCY

1000

100

G=1

G=10

G=100

Bandwidth

Limited

All Gains

0.1

100

10k

100k

100

10k

100k

Frequency (Hz)

SMALL SIGNAL RESPONSE

QUIESCENT CURRENT vs TEMPERATURE

G=1

G=10

G=100

2µs/div

–50

–25

100

125

Temperature (°C)

LARGE SIGNAL RESPONSE

G=10

G=1

G=100

2µs/div

PGA103

Some applications select gain of the PGA103 with switches

or jumpers. Figure 2 shows pull-up resistors connected to

assure a noise-free logic “1” when the switch or jumper is

off or open. Fixed-gain applications can connect the logic

inputs directly to V+ or ground (or other valid logic level)

without a series resistor.

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation

of the PGA103. Applications with noisy or high impedance

power supplies may require decoupling capacitors close to

the device pins as shown.

V+

V–

V+ V–

+15V –15V

0.1µF

PGA103

V_IN

100kΩ

V_O

V+

100kΩ

V_O= G • V_IN

PGA103

V_IN

A₀

GAIN

S₁

S₀

A₁

100

Closed Closed

Closed Open

Open Closed

S₁

S₀

Not Valid Open Open

FIGURE 2. Switch or Jumper-Selected Gains.

GAIN

A₁

A₀

OFFSET TRIMMING

Logic 0: (–5.6) ≤ V ≤ 0.8V

Logic 1: 2V ≤ V ≤ (V+)

Logic voltages referred to pin 3.

100

Offset voltage is laser-trimmed to typically less than 200µV

(referred to input) in all three gains. The input-referred offset

voltage can be different for each gain.

Not Valid

NOTE: (1) Low impedance ground connection required for good gain

accuracy—see text.

FIGURE 1. Basic Connections.

+15V –15V

The input and output are referred to the ground terminal,

pin 3. This must be a low-impedance connection to assure

good gain accuracy. A resistance of 0.1Ω in series with the

ground pin will cause the gain in G=100 to decrease by

approximately 0.2%.

V_IN

V_O= G (V_IN– V_TRIM)

PGA103

A₀

A₁

V_TRIM

(1)

+15V

DIGITAL INPUTS

OPA602

±5mV

The digital inputs, A₀and A₁, select the gain according to

the logic table in Figure 1. The digital inputs interface

directly to common CMOS and TTL logic components. The

logic inputs are referenced to the ground terminal, pin 3.

100kΩ

50kΩ

Trim Range

33Ω

Logic threshold voltage

is altered by V_TRIM

OK for V_TRIM≤ 100mV.

–15V

The logic table in Figure 1 shows that logic “1” on both A₀

and A₁is invalid. This logic code will not cause damage, but

the amplifier output will not be predictable while this code

is selected. The output will recover when a valid code is

selected.

NOTE: (1) Op amp buffer is required to preserve good gain accuracy—see

text.

The digital inputs are not latched, so a change in logic inputs

immediately selects a new gain. Switching time of the logic

is approximately 0.5µs. The time to respond to gain change

is equal to the switching time plus the time it takes the

amplifier to settle to a new output voltage in the newly

selected gain (see settling time specifications).

FIGURE 3. Offset Voltage Trim Circuit.

Figure 3 shows a circuit used to trim the offset voltage of the

PGA103. An op amp buffers the trim voltage to provide a

low impedance at the ground terminal. This is required to

maintain accurate gain. Remember that the logic inputs, A₀

and A₁, are referenced to this ground connection, so the

logic threshold voltage will be affected by the trim voltage.

This is insignificant if the offset adjustment is used only to

trim offset voltage. If a large offset is used (greater than

0.1V), be sure that the logic input signals provide valid logic

levels when referred to the voltage at the ground terminal,

pin 3.

Many applications use an external logic latch to access gain

control signals from a high speed data bus. Using an external

latch isolates the high speed digital bus from sensitive

analog circuitry. Locate the latch circuitry as far as practical

from analog circuitry to avoid coupling digital noise into the

analog circuitry.

PGA103

V⁺V^–

G₁= 1, 2, 4, 8

+15V –15V

G₂= 1, 10, 100

G = 0.1, 1, 10

V_O

–

V_IN

D₁

D₂

102kΩ

V_O

PGA103

PGA205

PGA103

V_IN

A₀

V_IN

G = G₁• G₂

A₁

Accepts inputs

to ±120V.

11.3kΩ

True

instrumentation

amplifier input.

D₁, D₂; IN4148

A₁A₀

GAIN

FIGURE 5. Wide Input Voltage Range Amplifer.

100

200

400

800

FIGURE 4. Programmable Gain Instrumentation Amplifier.

G₁

G₂= 1, 10, 100

MODEL

CHARACTERISTICS

–

V_IN

INA103

INA105

INA106

INA114

INA117

INA111

INA131

Low Noise, 1nV/√Hz IA

G = 1 Difference Amp

G = 10 Difference Amp

Resistor-Programmed Gain, Precision

±200V C-M Input Range Difference Amp

FET Input, High Speed IA

Precision, G = 100 IA

V_O

G = G₁• G₂

PGA103

INA

V_IN

A₁A₀

FIGURE 6. Instrumentation Amplifier with Programmable Gain Output Amp.

PGA103

PGA103U [BB]

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