PLL1705DBQR [BB]
3.3-V DUAL PLL MULTICLOCK GENERATOR; 3.3 V双PLL MULTICLOCK发生器
| 型号： | PLL1705DBQR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 3.3-V DUAL PLL MULTICLOCK GENERATOR |
| 文件： | 总18页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL1705
PLL1706
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
3.3-V DUAL PLL MULTICLOCK GENERATOR
FEATURES
APPLICATIONS
D
D
D
D
DVD Players
D
D
27-MHz Master Clock Input
Generated Audio System Clock:
DVD Add-On Cards for Multimedia PCs
Digital HDTV Systems
Set-Top Boxes
– SCKO0: 768 f (f = 44.1 kHz)
S
S
– SCKO1: 384 f , 768 f (f = 44.1 kHz)
S
S
S
– SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2,
S
S
DESCRIPTION
96 kHz)
– SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2,
†
†
The PLL1705 and PLL1706 are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1705 and
PLL1706 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1705can be controlled by sampling frequency-control
pins and those of the PLL1706 can be controlled through
serial-modecontrolpins. Thedevicegivescustomersboth
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitterperformance needed for high performance audio
DACs and/or ADCs. The PLL1705 and PLL1706 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top
boxes.
S
S
96 kHz)
D
D
D
Zero PPM Error Output Clocks
Low Clock Jitter: 50 ps (Typical)
Multiple Sampling Frequencies:
– f = 32, 44.1, 48, 64, 88.2, 96 kHz
S
D
D
3.3-V Single Power Supply
PLL1705: Parallel Control
PLL1706: Serial Control
D
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
FUNCTIONAL BLOCK DIAGRAM
(ML)
SR
(MC) (MD)
FS2
FS1
CSEL
V
CC
AGND
V 1–3 DGND1–3
DD
ModeControl Interface
Power Supply
Reset
PLL2
XT1
OSC
XT2
PLL1
Divider
Divider
SCKO2
Divider
SCKO3
MCKO1 MCKO2
( ): PLL1706
SCKO0
SCKO1
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
ThisintegratedcircuitcanbedamagedbyESD.TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriate
precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
PACKAGE CODE
PLL1705DBQ
PLL1705DBQR
PLL1706DBQ
PLL1706DBQR
Tube
PLL1705DBQ
PLL1706DBQ
SSOP 20
SSOP 20
20DBQ
20DBQ
–25°C to 85°C
–25°C to 85°C
PLL1705
PLL1706
Tape and reel
Tube
Tape and reel
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)
PLL1705 AND PLL1706
Supply voltage: V , V 1–3
CC DD
4 V
Supply voltage differences: V , V 1–3
±0.1 V
±0.1 V
CC DD
Ground voltage differences: AGND, DGND1–3
Digital input voltage: FS1 (MD), FS2 (MC), SR (ML), CSEL
Analog input voltage, XT1, XT2
– 0.3 V to (V
– 0.3 V to (V
+ 0.3) V
+ 0.3) V
DD
CC
Input current (any pins except supplies)
Ambienttemperatureunderbias
Storagetemperature
±10 mA
–40°C to 125°C
–55°C to 150°C
150°C
Junctiontemperature
Leadtemperature(soldering)
260°C, 5 s
260°C
Package temperature (IR reflow, peak)
(1)
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V 1–V 3 (= V ) = V
= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)
A
DD
DD
DD
CC
M
S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logicinput
CMOScompatible
0.7V
(1)
(1)
V
V
3.6
IH
DD
Input logic level
Vdc
0.3 V
IL
DD
(1)
(1)
I
IH
I
IL
V
= V
DD
= 0 V
65
100
IN
IN
Input logic current
Logicoutput
µA
V
±10
CMOS
(2)
V
OH
V
OL
I
I
= –4 mA
V – 0.4 V
DD
Vdc
Vdc
OH
Output logic level
(2)
= 4 mA
0.4
48
96
OL
Standardf
32
64
44.1
88.2
S
Samplingfrequency
kHz
Double f
S
MASTER CLOCK (MCKO1, 2) CHARACTERISTICS (f = 27 MHz, C = C = 15 pF, C = 20 pF on measurement pin)
M
1
2
L
Master clock frequency
26.73
27
27.27
MHz
V
V
IH
V
IL
0.7 V
CC
(3)
Inputlevel
0.3 V
CC
I
IH
I
IL
V
IN
V
IN
= V
CC
= 0 V
±10
(3)
Inputcurrent
µA
±10
(4)
Output voltage
3.5
2.0
Vp-p
ns
Output rise time
Output fall time
20% to 80% of V
80% to 20% of V
DD
2.0
ns
DD
For crystal oscillation
For external clock
45%
48%
50%
50
55%
1.5
Duty cycle
(5)
Clock jitter
Power-up time
PLL AC CHARACTERISTICS (SCKO0–3) (f = 27 MHz, C = 20 pF on measurement pin)
ps
(6)
0.5
ms
M
L
SCKO0
SCKO1
SCKO2
SCKO3
Fixed
Selectable for 44.1 kHz
33.8688
16.9344
8.192
33.8688
24.576
36.864
Output system clock frequency
MHz
256 f
384 f
12.288
18.432
2.0
S
S
12.288
Output rise time
Output fall time
Output duty cycle
20% to 80% of V
ns
ns
%
DD
DD
80% to 20% of V
2.0
45
50
55
100
150
200
6
(5)
Output clock jitter
50
ps
ns
ns
ms
PLL1705, to stated output frequency
PLL1706, to stated output frequency
To stated output frequency
50
(7)
Frequency Settling Time
80
(8)
Power-up time
3
(1)
(2)
(3)
(4)
(5)
Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0
Pin 10: XT1
Pin 11: XT2
Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.
The delay time from power on to oscillation
The settling time when the sampling frequency is changed
The delay time from power on to lockup
(6)
(7)
(8)
(9)
f
M
= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)
While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode.
3
PLL1705
PLL1706
www.ti.com
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
ELECTRICAL CHARACTERISTICS(continued)
all specifications at T = 25°C, V 1–V 3 (= V ) = V
= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)
A
DD
DD
DD
CC
M
S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY REQUIREMENTS
, V Supply voltage range
V
2.7
3.3
19
3.6
25
Vdc
mA
µA
CC DD
V
= V
= 3.3 V, f = 48 kHz
CC S
DD
(9)
Supply current
I + I
DD CC
(10)
Power down
320
63
500
90
Powerdissipation
TEMPERATURE RANGE
Operatingtemperature
Thermalresistance
V
DD
= V
= 3.3 V, f = 48 kHz
mW
CC
S
–25
85
°C
θ
PLL1705/6DBQ: 20-pin SSOP (150 mil)
150
°C/W
JA
(1)
(2)
(3)
(4)
(5)
Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0
Pin 10: XT1
Pin 11: XT2
Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.
The delay time from power on to oscillation
The settling time when the sampling frequency is changed
The delay time from power on to lockup
(6)
(7)
(8)
(9)
f
M
= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)
While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode.
PIN ASSIGNMENTS
PLL1705
(TOP VIEW)
PLL1706
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
1
V
3
V
1
V
3
DD
DD
DD
DD
SCKO2
SCKO3
DGND1
FS1
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
SCKO2
SCKO3
DGND1
MD
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
FS2
MC
ML
SR
V
V
2
V
V
2
CC
DD
CC
DD
AGND
XT1
CSEL
XT2
AGND
XT1
CSEL
XT2
4
PLL1705
PLL1706
www.ti.com
TERMINAL
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
Terminal Functions
I/O
DESCRIPTION
NAME
NO.
9
AGND
–
IN
Analogground
(1)
CSEL
12
4
SCKO1 frequency selection control
Digital ground 1
DGND1
DGND2
DGND3
FS1(MD)
FS2(MC)
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
SR(ML)
–
16
–
Digital ground 2
17
5
–
Digital ground 3
(1)
Sampling frequency group control in PLL1705, data input for serial control in PLL1706
IN
(1)
6
IN
Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706
14
15
19
18
2
OUT
OUT
OUT
OUT
OUT
OUT
IN
27-MHz master clock output 1
27-MHz master clock output 2
System clock output 0 (33.8688 MHz fixed)
System clock output 1 (selectable for 44.1 kHz)
System clock output 2 (256 f )
S
3
System clock output 3 (384 f )
S
(1)
7
Sampling rate control in PLL1705, load strobe input for serial control in PLL1706
Analog power supply, 3.3 V
V
V
V
V
8
–
CC
DD
DD
DD
1
2
3
1
–
Digital power supply 1, 3.3 V
13
20
10
11
–
Digital power supply 2, 3.3 V
–
Digital power supply 3, 3.3 V
XT1
XT2
IN
27-MHz crystal oscillator, or external clock input
27-MHz crystal oscillator, must be OPEN for external clock input mode
OUT
(1)
Schmitt-triggerinputwithinternalpulldown.
5
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
TYPICAL PERFORMANCE CURVES
JITTER
vs
JITTER
vs
LOAD CAPACITANCE
SAMPLING FREQUENCY
70
60
50
40
30
70
60
50
40
30
SCKO3
SCKO0
SCKO2
SCKO1
MCKO1
MCKO2
MCKO1
SCKO0
SCKO1
SCKO2
MCKO2
SCKO3
0
5
10
15
20
30
40
50
60
70
80
90
100
C
L
– Load Capacitance – pF
f
S
– Sampling Frequency – kHz
Figure 1
Figure 2
JITTER
vs
JITTER
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
70
70
60
50
40
30
60
50
40
30
SCKO0
SCKO3
SCKO3
SCKO0
MCKO2
SCKO1
MCKO1
SCKO1
SCKO2
MCKO1
SCKO2
MCKO2
–50
–25
0
25
50
75
100
2.7
3.0
3.3
3.6
T
A
– Free-Air Temperature – °C
V
CC
– Supply Voltage – V
Figure 3
Figure 4
:
NOTE All specifications at T = 25°C, V 1–3 (= V ) = V
DD DD
= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency
M 1 2
A
CC
(33.8688MHz for SCKO0, 33.8688 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement
S
S
L
pin, unless otherwise noted.
6
PLL1705
PLL1706
www.ti.com
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
DUTY CYCLE
vs
DUTY CYCLE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
55
53
51
49
47
55
53
51
49
47
45
SCKO0
SCKO1
SCKO2
SCKO2
SCKO3
SCKO1
SCKO3
SCKO0
MCKO2
MCKO2
MCKO1
MCKO1
45
2.7
3.0
3.3
3.6
–50
–25
0
25
50
75
100
V
CC
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 5
Figure 6
:
NOTE All specifications at T = 25°C, V 1–3 (= V ) = V
DD DD
= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency
M 1 2
A
CC
(33.8688MHz for SCKO0, 33.8688 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement
S
S
L
pin, unless otherwise noted.
7
PLL1705
PLL1706
www.ti.com
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1705/6 consists of a dual PLL clock and master clock generator which generates four system clocks and two
buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1705/6. The PLL is
designed to accept a 27-MHz master clock.
SCKO3
384 f
S
Counter N
Counter M
Divider
Divider
SCKO0–3
Frequency
Control
PhaseDetector
and
Loop Filter
VCO
PLL2
PLL1
Counter M
Counter N
PhaseDetector
and
Loop Filter
VCO
OSC
Divider
XT1 XT2 MCKO1 MCKO2
27 MHz 27 MHz
SCKO0
SCKO1
SCKO2
33.8688MHz 33.8688/16.9344MHz 256 f
S
Figure 7. Block Diagram
8
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,
and Figure 9 illustrates the 27-MHz master clock timing requirement.
MCKO2
MCKO1
MCKO2
MCKO1
27-MHz
Internal
Master
Clock
27-MHz
Internal
Master
Clock
XT1
XT1
XT2
External
Clock
C1
C2
Crystal
Crystal
OSC
Circuit
Crystal
OSC
Circuit
XT2
PLL1705/PLL1706
PLL1705/PLL1706
C1, C2 = 10 pF to 33 pF
CrystalResonatorConnection
External Clock Input Connection
Figure 8. Master Clock Generator Connection Diagram
t
(XT1H)
0.7 V
0.3 V
CC
CC
XT1
t
(XT1L)
DESCRIPTION
SYMBOL
MIN
10
MAX
UNIT
ns
Master clock pulse duration HIGH
Master clock pulse duration LOW
t
XT1H
t
10
ns
XT1L
Figure 9. External Master Clock Timing Requirement
The PLL1705/6 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
384 fS or 768 fS (fS = 44.1 kHz) which is selected by CSEL (pin 12) for a CD-DA DSP. The output frequency of the remaining
clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3 output 256-fS
and 384-fS system clocks, respectively. Table 2 shows each sampling frequency, which can be programmed. The system
clock output frequencies for programmed sampling frequencies are shown in Table 3.
Table 1. Generated System Clock SCKO1 Frequency
CSEL
LOW
HIGH
SCKO1 FREQUENCY
33.8688MHz
16.9344MHz
Table 2. Sampling Frequencies
SAMPLING RATE
SAMPLING FREQUENCY (kHz)
Standardsamplingfrequencies
Doublesamplingfrequencies
32
64
44.1
88.2
48
96
9
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
Table 3. Sampling Frequencies and System Clock Output Frequencies
SAMPLING FREQUENCY (kHz)
SAMPLING RATE
Standard
Standard
Standard
Double
SCKO2 (MHZ) SCKO3 (MHZ)
32
44.1
48
8.192
11.2896
12.288
16.384
22.5792
24.576
12.288
16.9344
18.432
24.576
33.8688
36.864
64
88.2
96
Double
Double
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from
sampling frequency change to SCKO settling is 200 ns maximum. This clock transient timing is not synchronized with the
SCKOx signals. Figure 10 illustrates SCKO transient timing in the PLL1706. External buffers are recommended on all
output clocks in order to avoid degrading the jitter performance of the PLL1705/6.
ML
200 ns
1–2 Clocks of MCKO1,2
SCKO2
SCKO3
Stable
Clock TransitionRegion
Stable
SCKO0
SCKO1
33.8688 MHz, 384 or 768 of 44.1 kHz
Figure 10. System Clock Transient Timing
POWER-ON RESET
The PLL1705/6 has an internal power-on reset circuit. The mode register of PLL1706 is initialized with default settings by
power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power up time.
Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on
reset timing is shown in Figure 11.
V
DD
2.4 V
2.0 V
1.6 V
Reset
ResetRemoval
InternalReset
MasterClock
1024 Master Clocks
Figure 11. Power-On Reset Timing
10
PLL1705
PLL1706
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SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
FUNCTION CONTROL
The built-in functions of the PLL1705 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1
(pin 5) and FS2 (pin 6). The PLL1706 can be controlled in the serial mode (software mode), which uses a three-wire
interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.
Table 4. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Samplingrateselect(standard/double)
Each clock output enable/disable
Power down
PARALLEL MODE
SERIAL MODE
Yes
Yes
No
Yes
Yes
Yes
Yes
No
PLL1705 (Parallel Mode)
In the parallel mode, the following functions can be selected:
Sampling Frequency Group Select
The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6)
LOW
FS1 (PIN 5)
LOW
SAMPLING FREQUENCY
48 kHz
LOW
HIGH
44.1 kHz
HIGH
LOW
32 kHz
HIGH
HIGH
Reserved
Sampling Rate Select
The sampling rate can be selected by SR (pin 7)
SR (PIN 7)
LOW
SAMPLING RATE
Standard
HIGH
Double
PLL1706 (Serial Mode)
The built-in functions of the PLL1706 are shown in Table 5. These functions are controlled using the ML, MC, and MD serial
control signals.
Table 5. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Samplingrateselect(standard/double)
Each clock output enable/disable
Power down
DEFAULT
48-kHz group
Standard
Enabled
Disabled
11
PLL1705
PLL1706
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SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
Program-Register Bit Mapping
The built-in functions of the PLL1706 are controlled through a 16-bit program register. This register is loaded using MD,
MC and ML. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register.
Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in
Figure 12 and Figure 13, respectively.
ML
MC
MD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12. Serial Mode Control Format
t
(MHH)
t
(MLL)
ML
V /2
DD
t
t
t
(MLS)
(MCL)
(MLS)
t
t
(MLH)
(MCH)
MC
MD
V
V
/2
/2
DD
t
(MCY)
MSB
LSB
DD
t
(MDH)
t
(MDS)
DESCRIPTION
SYMBOL
MIN
100
40
TYP
MAX
UNIT
ns
MC pulse cycle time
t
MCY
MC pulse duration LOW
MC pulse duration HIGH
MD hold time
t
ns
MCL
t
t
40
ns
MCH
MDH
40
ns
MD setup time
t
40
ns
MDS
(1)
ML low-level time
MLhigh-leveltime
(2)
ML hold time
t
16
MC clocks
MLL
MHH
MLH
t
200
40
ns
ns
ns
t
(3)
ML setup time
t
40
MLS
(1)
(2)
(3)
MC clocks: MC clock period
MC rising edge for LSB to ML rising edge
ML rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any ML rise time is accepted.
Figure 13. Control Data Input Timing
12
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
Mode Register
D15
0
D14
1
D13
1
D12
1
D11
0
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
SR
D1
D0
CE6
CE5
CE4
CE3
CE2
CE1
RSV
FS2
FS1
Table 6. Register Mapping
REGISTER
BIT NAME
CE6
DESCRIPTION
MCKO2outputenable/disable
MCKO1outputenable/disable
SCKO1outputenable/disable
SCKO3outputenable/disable
SCKO2outputenable/disable
SCKO0outputenable/disable
Reserved, must be 0
CE5
CE4
CE3
CE2
Modecontrol
CE1
RSV
SR
Sampling rate select
FS[2:1]
Samplingfrequencyselect
FS[2:1]: Sampling Frequency Group Select
FS2
0
FS1
0
SAMPLING FREQUENCY
48 kHz
DEFAULT
O
0
1
44.1 kHz
1
0
32 kHz
1
1
Reserved
SR: Sampling Rate Select
SR
0
SAMPLING RATE
Standard
DEFAULT
O
1
Double
CE [6:1]: Clock Output Control
CE1–CE6
CLOCK OUTPUT CONTROL
Clock output disable
DEFAULT
0
1
Clock output enable
O
While all the bits of CE [6:1] are 0, the PLL1706 goes into the power-down mode, all dynamic operation including PLLs
and the oscillator halt, but serial mode control is enabled for resumption.
CONNECTION DIAGRAM
Figure 14 shows the typical connection circuit for the PLL1705. There are four grounds for digital and analog power
supplies. However, the use of one common ground connection is recommended to avoid latch-up or other
power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1705/6 are MPEG-2 based systems such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1705/6 provides audio system clocks for a CD-DA DSP,
DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock.
13
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
3.3 V
(2)
PLL1705/6
V
1
V
3
1
2
20
19
18
17
16
15
14
13
12
11
DD
DD
SCKO2
SCKO3
DGND1
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
(1)
(1)
(1)
3
4
(4)
FS1 (MD)
FS2 (MC)
SR(ML)
5
6
7
V
CC
V
DD
2
8
(2)
(1)
(3)
AGND
XT1
CSEL
XT2
9
10
(3)
Clock Outputs (5)
(1)
(2)
(3)
(4)
0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout
10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout
27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2
This connection is for PLL1705 (parallel mode); when PLL1706 (serial mode) is to be used, control pins must be connected to serial interfaced
controller.
(5)
For good jitter performance, minimize the load capacitance on the clock output.
Figure 14. Typical Connection Diagram
14
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
BLOCK DIAGRAM OF MPEG-2 BASED SYSTEM APPLICATION
PLL1705/6
384 f
S
S
SCKO3
SCKO2
27-MHz
Crystal
256 f
PCM1716
PCM1716
PCM1716
Front
27 MHz
MCKO1/2
SCKO0 or 1
Surround
Center
CD-DA/
MPEG/AC-3
AudioDecoder
Subwoofer
DVD DSP
15
PLL1705
PLL1706
www.ti.com
SLES046A– AUGUST 2002 – REVISED SEPTEMBER 2002
MECHANICAL DATA
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
0.012(0,30)
0.008(0,20)
0.025(0,64)
24
0.005(0,13)
13
0.157(3,99) 0.244(6,20)
0.008 (0,20) NOM
0.150(3,81)
0.228(5,80)
GaugePlane
1
12
A
0.010(0,25)
0°–8°
0.035(0,89)
0.016(0,40)
0.069 (1,75) MAX
SeatingPlane
0.004(0,10)
0.010(0,25)
0.004(0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
A MIN
M0–137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/02
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO–137.
16
PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2006
PACKAGING INFORMATION
Orderable Device
PLL1705DBQ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
20
20
20
20
20
20
20
20
56 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PLL1705DBQG4
PLL1705DBQR
PLL1705DBQRG4
PLL1706DBQ
SSOP/
QSOP
DBQ
DBQ
DBQ
DBQ
DBQ
DBQ
DBQ
56 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
56 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PLL1706DBQG4
PLL1706DBQR
PLL1706DBQRG4
SSOP/
QSOP
56 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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