PLL1707 [BB]
3.3 V DUAL PLL MULTICLOCK GENERATOR; 3.3 V双PLL MULTICLOCK发生器
| 型号： | PLL1707 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| 文件： | 总22页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES065 – DECEMBER 2002
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FEATURES
APPLICATIONS
D
27-MHz Master Clock Input
D
D
D
D
D
D
D
HDD + DVD Recorders
DVD Recorders
HDD Recorders
DVD Players
D
Generated Audio System Clock (PLL1707):
– SCKO0: 768 f (f = 44.1 kHz)
S
S
– SCKO1: 768 f , 512 f (f = 48 kHz)
S
S
S
– SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2,
S
S
96 kHz)
– SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2,
S
S
DVD Add-On Cards for Multimedia PCs
Digital HDTV Systems
96 kHz)
Generated Audio System Clock (PLL1708):
– SCKO0: 768 f (f = 44.1 kHz)
D
S
S
Set-Top Boxes
– SCKO1: 768 f , 512 f , 384 f , 256 f
S
S
S
S
(f = 48 kHz)
S
– SCKO2: 256 f (f = 16, 22.05, 24, 32, 44.1,
S
S
DESCRIPTION
48, 64, 88.2, 96 kHz)
– SCKO3: 384 f (f = 16, 22.05, 24, 32, 44.1,
S
S
†
†
The PLL1707 and PLL1708 are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1707 and
PLL1708 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1707 can be controlled by sampling frequency-control
pins and those of the PLL1708 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1707 and PLL1708 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD recorders, HDD recorders, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.
48, 64, 88.2, 96 kHz)
D
D
D
D
Zero PPM Error Output Clocks
Low Clock Jitter: 50 ps (Typical)
Multiple Sampling Frequencies (PLL1707):
– f = 32, 44.1, 48, 64, 88.2, 96 kHz
S
Multiple Sampling Frequencies (PLL1708):
– f = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,
S
96 kHz
D
D
D
3.3-V Single Power Supply
PLL1707: Parallel Control
PLL1708: Serial Control
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
ꢀꢖ ꢑ ꢊꢋ ꢐ ꢎꢏ ꢑꢕ ꢊ ꢌꢎꢌ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢇ ꢀꢛ ꢚꢦꢡ ꢠꢞꢟ
ꢠ ꢚꢘ ꢙꢚꢛ ꢜ ꢞꢚ ꢟ ꢣꢢ ꢠ ꢗ ꢙꢗ ꢠ ꢝ ꢞꢗ ꢚꢘꢟ ꢣ ꢢꢛ ꢞꢧꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢎꢢꢨ ꢝꢟ ꢏꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ ꢟꢞ ꢝꢘꢦ ꢝꢛ ꢦ ꢩ ꢝꢛ ꢛ ꢝ ꢘꢞꢪꢇ
ꢀꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢫ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢪ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢫ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢇ
Copyright 2002, Texas Instruments Incorporated
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SLES065 – DECEMBER 2002
FUNCTIONAL BLOCK DIAGRAM
(MS)
SR
(MC) (MD)
FS2
FS1
CSEL
V
CC
AGND
V 1–3 DGND1–3
DD
Mode Control Interface
Power Supply
Reset
PLL2
XT1
OSC
XT2
PLL1
Divider
Divider
SCKO2
Divider
SCKO3
MCKO1 MCKO2
( ): PLL1708
SCKO0
SCKO1
PACKAGE/ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
PACKAGE CODE
MARKING
PLL1707
PLL1708
PLL1707DBQ
PLL1707DBQR
PLL1708DBQ
PLL1708DBQR
Tube
PLL1707DBQ
PLL1708DBQ
SSOP 20
SSOP 20
20DBQ
20DBQ
–25°C to 85°C
–25°C to 85°C
Tape and reel
Tube
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PLL1705 AND PLL1706
Supply voltage: V , V 1–V
3
4 V
CC DD DD
Supply voltage differences: V , V 1–V
3
±0.1 V
±0.1 V
CC DD DD
Ground voltage differences: AGND, DGND1–DGND3
Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL
Analog input voltage, XT1, XT2
– 0.3 V to (V
– 0.3 V to (V
+ 0.3) V
+ 0.3) V
DD
CC
Input current (any pins except supplies)
Ambient temperature under bias
±10 mA
–40°C to 125°C
–55°C to 150°C
150°C
Storage temperature
Junction temperature
Lead temperature (soldering)
260°C, 5 s
260°C
Package temperature (IR reflow, peak)
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLES065 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V 1–V 3 (= V ) = V
= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)
A
DD
DD
DD
CC
M
S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic input
CMOS compatible
0.7V
(1)
(1)
V
V
3.6
IH
DD
Input logic level
Vdc
0.3 V
IL
DD
(1)
(1)
I
IH
I
IL
V
= V
DD
= 0 V
65
100
IN
IN
Input logic current
Logic output
µA
V
±10
CMOS
(2)
V
OH
V
OL
I
I
= –4 mA
V – 0.4 V
DD
Vdc
Vdc
OH
Output logic level
(2)
= 4 mA
0.4
48
96
24
48
96
OL
Standard f
32
64
16
32
64
44.1
88.2
S
PLL1707
PLL1708
Double f
S
Half f
S
Standard f
22.05
44.1
Sampling frequency
kHz
S
Double f
88.2
S
MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (f = 27 MHz, C = C = 15 pF, C = 20 pF on measurement pin)
M
1
2
L
Master clock frequency
26.73
27
27.27
MHz
V
V
IH
V
IL
0.7 V
CC
(3)
Input level
0.3 V
CC
I
IH
I
IL
V
IN
V
IN
= V
CC
= 0 V
±10
(3)
Input current
µA
±10
(4)
Output voltage
3.5
2.0
Vp-p
ns
Output rise time
Output fall time
20% to 80% of V
80% to 20% of V
DD
2.0
ns
DD
For crystal oscillation
For external clock
45%
51%
50%
50
55%
1.5
Duty cycle
(5)
Clock jitter
Power-up time
ps
(6)
0.5
ms
PLL AC CHARACTERISTICS (SCKO0–SCKO3) (f = 27 MHz, C = 20 pF on measurement pin)
M
L
SCKO0
SCKO1
SCKO2
SCKO3
SCKO0
SCKO1
SCKO2
SCKO3
Fixed
33.8688
Selectable for 48 kHz
24.576
8.192
36.864
24.576
36.864
PLL1707
PLL1708
256 f
384 f
12.288
18.432
33.8688
24.576
12.288
18.432
2.0
S
12.288
Output system clock
frequency
S
MHz
Fixed
Selectable for 48 kHz
12.288
4.096
6.144
36.864
24.576
36.864
256 f
384 f
S
S
Output rise time
Output fall time
Output duty cycle
20% to 80% of V
80% to 20% of V
ns
ns
%
DD
DD
2.0
45
50
55
(1)
(2)
(3)
(4)
(5)
Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
Pin 10: XT1
Pin 11: XT2
Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.
The delay time from power on to oscillation
The settling time when the sampling frequency is changed
The delay time from power on to lockup
(6)
(7)
(8)
(9)
f
M
= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)
While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
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SLES065 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS (continued)
all specifications at T = 25°C, V 1–V 3 (= V ) = V
= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)
A
DD
DD
DD
CC
M
S
PARAMETER
TEST CONDITIONS
MIN
TYP
58
50
50
80
3
MAX
100
100
150
300
6
UNIT
ps
SCKO0, SCKO1
(5)
Output clock jitter
SCKO2, SCKO3
ps
PLL1707, to stated output frequency
PLL1708, to stated output frequency
To stated output frequency
(7)
Frequency Settling Time
ns
(8)
Power-up time
POWER SUPPLY REQUIREMENTS
, V Supply voltage range
ms
V
2.7
3.3
19
3.6
25
Vdc
mA
µA
CC DD
V
= V
CC
= 3.3 V, f = 48 kHz
S
(10)
DD
Power down
= V
(9)
Supply current
I
+ I
DD CC
350
63
550
90
Power dissipation
TEMPERATURE RANGE
Operating temperature
Thermal resistance
V
DD
= 3.3 V, f = 48 kHz
mW
CC
S
–25
85
°C
θ
PLL1707/8DBQ: 20-pin SSOP (150 mil)
150
°C/W
JA
(1)
(2)
(3)
(4)
(5)
Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
Pin 10: XT1
Pin 11: XT2
Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.
The delay time from power on to oscillation
The settling time when the sampling frequency is changed
The delay time from power on to lockup
(6)
(7)
(8)
(9)
f
M
= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)
While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
PIN ASSIGNMENTS
PLL1707
(TOP VIEW)
PLL1708
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
1
V
3
V
1
V
3
DD
DD
DD
DD
SCKO2
SCKO3
DGND1
FS1
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
SCKO2
SCKO3
DGND1
MD
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
FS2
MC
MS
SR
V
V
2
V
V
2
CC
DD
CC
DD
AGND
XT1
CSEL
XT2
AGND
XT1
CSEL
XT2
4
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TERMINAL
SLES065 – DECEMBER 2002
PLL1707 Terminal Functions
I/O
DESCRIPTION
NAME
NO.
9
AGND
CSEL
–
I
Analog ground
(1)
12
4
SCKO1 frequency selection control
Digital ground 1
DGND1
DGND2
DGND3
FS1
–
–
–
I
16
Digital ground 2
17
5
Digital ground 3
(1)
(1)
Sampling frequency group control 1
Sampling frequency group control 2
27-MHz master clock output 1
27-MHz master clock output 2
FS2
6
I
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
SR
14
15
18
19
2
O
O
O
O
O
O
I
System clock output 0 (33.8688 MHz fixed)
System clock output 1 (selectable for 48 kHz)
System clock output 2 (256 f selectable)
S
3
System clock output 3 (384 f selectable)
S
(1)
Sampling rate control
7
V
V
V
V
8
–
–
–
–
I
Analog power supply, 3.3 V
CC
DD
DD
DD
1
2
3
1
Digital power supply 1, 3.3 V
13
20
10
11
Digital power supply 2, 3.3 V
Digital power supply 3, 3.3 V
XT1
XT2
27-MHz crystal oscillator, or external clock input
27-MHz crystal oscillator, must be OPEN for external clock input mode
O
(1)
Schmitt-trigger input with internal pulldown.
5
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SLES065 – DECEMBER 2002
PLL1708 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
CSEL
NO.
9
–
I
Analog ground
(1)
12
4
SCKO1 frequency selection control
Digital ground 1
DGND1
DGND2
–
–
–
I
16
Digital ground 2
DGND3
MC
17
6
Digital ground 3
(1)
Bit clock input for serial control
27-MHz master clock output 1
27-MHz master clock output 2
MCKO1
MCKO2
MD
14
15
5
O
O
I
(1)
Data input for serial control
(1)
Chip select input for serial control
MS
7
I
SCKO0
SCKO1
SCKO2
SCKO3
18
19
2
O
O
O
O
–
–
–
–
I
System clock output 0 (33.8688 MHz fixed)
System clock output 1 (selectable for 48 kHz)
System clock output 2 (256 f selectable)
S
3
System clock output 3 (384 f selectable)
S
V
CC
V
DD
V
DD
V
DD
8
Analog power supply, 3.3 V
1
2
3
1
Digital power supply 1, 3.3 V
13
20
10
11
Digital power supply 2, 3.3 V
Digital power supply 3, 3.3 V
XT1
XT2
27-MHz crystal oscillator, or external clock input
27-MHz crystal oscillator, must be OPEN for external clock input mode
O
(1)
Schmitt-trigger input with internal pulldown.
6
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SLES065 – DECEMBER 2002
TYPICAL PERFORMANCE CURVES
JITTER
vs
JITTER
vs
LOAD CAPACITANCE
SAMPLING FREQUENCY
70
65
60
55
50
45
40
70
65
60
55
50
45
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
SCKO1
SCKO3
SCKO0
SCKO2
MCKO2
MCKO1
40
30
0
5
10
15
20
40
50
60
70
80
90
100
C
L
– Load Capacitance – pF
f
S
– Sampling Frequency – kHz
Figure 1
Figure 2
JITTER
vs
JITTER
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
70
70
65
60
55
50
45
65
60
55
50
45
40
SCKO1
SCKO3
SCKO1
SCKO0
SCKO0
SCKO3
MCKO2
SCKO2
MCKO2
MCKO1
75
MCKO1
SCKO2
0
40
–50
–25
25
50
100
2.7
3.0
3.3
3.6
T
A
– Free-Air Temperature – °C
V
CC
– Supply Voltage – V
Figure 3
Figure 4
:
NOTE All specifications at T = 25°C, V 1–3 (= V ) = V
DD DD
= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency
M 1 2
A
CC
S
(33.8688MHz for SCKO0, 36.864 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement pin,
S
L
unless otherwise noted.
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SLES065 – DECEMBER 2002
DUTY CYCLE
vs
DUTY CYCLE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
55
55
54
53
52
51
50
49
48
47
46
45
54
MCKO1
53
MCKO2
MCKO2
52
51
50
49
48
47
46
45
SCKO2
SCKO1
MCKO1
SCKO2
SCKO1
SCKO3
SCKO3
SCKO0
SCKO0
2.7
3.0
3.3
3.6
–50
–25
0
25
50
75
100
V
CC
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 5
Figure 6
:
NOTE All specifications at T = 25°C, V 1–3 (= V ) = V
DD DD
= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency
M 1 2
A
CC
S
(33.8688MHz for SCKO0, 36.864 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement pin,
S
L
unless otherwise noted.
8
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SLES065 – DECEMBER 2002
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two
buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL is
designed to accept a 27-MHz master clock.
SCKO3
384 f
S
Counter N
Counter M
Divider
Divider
SCKO0–3
Frequency
Control
Phase Detector
and
Loop Filter
VCO
PLL2
PLL1
Counter M
Counter N
Phase Detector
and
Loop Filter
VCO
OSC
Divider
XT1 XT2 MCKO1 MCKO2
27 MHz 27 MHz
SCKO0
33.8688 MHz
SCKO1
SCKO2
256 f
36.864/24.576 MHz
(36.864/24.576 MHz)
(18.432/12.288 MHz)
S
( ): PLL1708
Figure 7. Block Diagram
9
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SLES065 – DECEMBER 2002
The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,
and Figure 9 illustrates the 27-MHz master clock timing requirement.
MCKO2
MCKO1
MCKO2
MCKO1
27-MHz
Internal
Master
Clock
27-MHz
Internal
Master
Clock
XT1
XT1
XT2
External
Clock
C1
C2
Crystal
Crystal
OSC
Circuit
Crystal
OSC
Circuit
XT2
PLL1707/PLL1708
PLL1707/PLL1708
C1, C2 = 10 pF to 33 pF
Crystal Resonator Connection
External Clock Input Connection
Figure 8. Master Clock Generator Connection Diagram
t
(XT1H)
0.7 V
0.3 V
CC
XT1
CC
t
(XT1L)
DESCRIPTION
SYMBOL
MIN
10
MAX
UNIT
ns
Master clock pulse duration HIGH
Master clock pulse duration LOW
t
(XT1H)
t
10
ns
(XT1L)
Figure 9. External Master Clock Timing Requirement
The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
256 fS, 384 fS 512 fS, or 768 fS (fS = 48 kHz) which is selected by hardware or software control. The output frequency of
the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3
output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency which can be programmed.
The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling
frequencies on SCKO2 and SCKO3 and 256 fS and 384 fS on SCKO1 are supported only on the PLL1708.
Table 1. Generated System Clock SCKO1 Frequency
f
SCKO1 FREQUENCY
12.288 MHz
S
†
†
256 f
384 f
S
S
18.432 MHz
512 f
24.576 MHz
S
768 f
36.864 MHz
S
†
PLL1708 only
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SLES065 – DECEMBER 2002
Table 2. Sampling Frequencies
SAMPLING RATE
Half sampling frequencies
SAMPLING FREQUENCY (kHz)
†
16
32
64
22.05
44.1
88.2
24
48
96
Standard sampling frequencies
Double sampling frequencies
PLL1708 only
†
Table 3. Sampling Frequencies and System Clock Output Frequencies
256 f
384 f
S
S
SAMPLING FREQUENCY (kHz)
SAMPLING RATE
SCKO2 (MHZ) SCKO3 (MHZ)
†
16
Half
Half
4.096
5.6448
6.144
6.144
8.4672
9.216
†
22.05
†
24
Half
32
44.1
48
Standard
Standard
Standard
Double
Double
Double
8.192
12.288
16.9344
18.432
24.576
33.8688
36.864
11.2896
12.288
16.384
22.5792
24.576
64
88.2
96
†
PLL1708 only
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from
sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the
PLL1708.
MS
300 ns
1–2 Clocks of MCKO1, 2
SCKO2
SCKO3
Stable
Clock Transition Region
Stable
SCKO0
SCKO1
33.8688 , 36.864, or 24.576 MHz
Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient
timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on
all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.
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SLES065 – DECEMBER 2002
SR
FS2, 1
CSEL
150 ns
50 ns
SCKO1
SCKO2
SCKO3
Stable
Clock Transition Region
Stable
SCKO0
33.8688 MHz
Figure 11. SCKO Transient Timing
POWER-ON RESET
The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settings
by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time.
Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on
reset timing is shown in Figure 12.
V
DD
2.4 V
2.0 V
1.6 V
Reset
Reset Removal
Internal Reset
Master Clock
1024 Master Clocks
Figure 12. Power-On Reset Timing
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SLES065 – DECEMBER 2002
FUNCTION CONTROL
The built-in functions of the PLL1707 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1
(pin 5) and FS2 (pin 6). The PLL1708 can be controlled in the serial mode (software mode), which has a three-wire interface
using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.
Table 4. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Sampling rate select (standard/double)
Sampling rate select (half)
PARALLEL MODE
SERIAL MODE
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Each clock output enable/disable
Power down
SCKO1 configuration
PLL1707 (Parallel Mode)
In the parallel mode, the following functions can be selected:
Sampling Frequency Group Select
The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6)
LOW
FS1 (PIN 5)
LOW
SAMPLING FREQUENCY
48 kHz
LOW
HIGH
44.1 kHz
HIGH
LOW
32 kHz
HIGH
HIGH
Reserved
Sampling Rate Select
The sampling rate can be selected by SR (pin 7)
SR (PIN 7)
LOW
SAMPLING RATE
Standard
Double
HIGH
System Clock SCKO1 Frequency Select
System clock SCKO1 frequency can be selected by CSEL (pin 12).
CSEL (PIN 12)
LOW
SCKO1 FREQUENCY
36.864 MHz
HIGH
24.576 MHz
PLL1708 (Serial Mode)
The built-in functions of the PLL1708 are shown in Table 5. These functions are controlled using the MS, MC, and MD serial
control signals.
Table 5. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Sampling rate select (half, standard, double)
Each clock output enable/disable
Power down
DEFAULT
48-kHz group
Standard
Enabled
Disabled
SCKO1 configuration
36.864 MHz, 24.576 MHz
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SLES065 – DECEMBER 2002
Program-Register Bit Mapping
The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD,
MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register.
Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in
Figure 13 and Figure 14, respectively.
MS
MC
MD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 13. Serial Mode Control Format
t
(MHH)
t
(MSL)
MS
V /2
DD
t
t
t
(MSS)
(MCL)
(MSS)
t
t
(MSH)
(MCH)
MC
MD
V
V
/2
/2
DD
t
(MCY)
MSB
LSB
DD
t
(MDH)
t
(MDS)
DESCRIPTION
SYMBOL
MIN
100
40
TYP
MAX
UNIT
ns
MC pulse cycle time
t
(MCY)
MC pulse duration LOW
MC pulse duration HIGH
MD hold time
t
ns
(MCL)
t
t
40
ns
(MCH)
(MDH)
40
ns
MD setup time
t
40
ns
(MDS)
(1)
MS low-level time
MS high-level time
(2)
MS hold time
t
16
MC clocks
(MSL)
(MHH)
t
200
40
ns
ns
ns
t
(MSH)
(3)
MS setup time
t
40
(MSS)
(1)
(2)
(3)
MC clocks: MC clock period
MC rising edge for LSB to MS rising edge
MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.
Figure 14. Control Data Input Timing
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SLES065 – DECEMBER 2002
Mode Register
D15
0
D14
1
D13
1
D12
1
D11
0
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CE6
CE5
CE4
CE3
CE2
CE1
SR2
SR1
FS2
FS1
Table 6. Mode Register Mapping
REGISTER
BIT NAME
CE6
DESCRIPTION
MCKO2 output enable/disable
MCKO1 output enable/disable
SCKO1 output enable/disable
SCKO3 output enable/disable
SCKO2 output enable/disable
SCKO0 output enable/disable
Sampling rate select
CE5
CE4
CE3
Mode control
CE2
CE1
SR[2:1]
FS[2:1]
Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
FS2
0
FS1
0
SAMPLING FREQUENCY
48 kHz (default)
44.1 kHz
0
1
1
0
32 kHz
1
1
Reserved
SR[2:1]: Sampling Rate Select
SR2
SR1
SAMPLING RATE
Standard (default)
Double
0
0
1
1
0
1
0
1
Half
Reserved
CE [6:1]: Clock Output Control
CE1–CE6
CLOCK OUTPUT CONTROL
Clock output disable
0
1
Clock output enable (default)
While all the bits of CE [6:1] are 0, the PLL1708 goes into the power-down mode, all dynamic operation including PLLs
and the oscillator halts, but serial mode control is enabled for resumption.
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SLES065 – DECEMBER 2002
Configuration Register
D15
0
D14
1
D13
1
D12
0
D11
1
D10
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RSV RSV RSV RSV RSV CFG1
RSV
RSV
RSV
RSV
Table 7. Configuration Register Mapping
REGISTER
BIT NAME
RSV
DESCRIPTION
Reserved, must be 0
SCKO1 configuration
Configuration
CFG1
CFG1: SCKO1 Configuration Control
CFG1
CONFIGURATION 1
0
1
36.864 MHz, 24.576 MHz for SCKO1 (default)
18.432 MHz, 12.288 MHz for SCKO1
The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).
CFG1
(REGISTER)
CSEL
(PIN 12)
SCKO1
0
0
1
1
LOW
HIGH
LOW
HIGH
36.864 MHz
24.576 MHz
18.432 MHz
12.288 MHz
CONNECTION DIAGRAM
Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power
supplies. However, the use of one common ground connection is recommended to avoid latch-up or other
power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players,
DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system
clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.
16
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SLES065 – DECEMBER 2002
3.3 V
(2)
PLL1707/8
V
1
V
3
1
2
20
19
18
17
16
15
14
13
12
11
DD
DD
SCKO2
SCKO3
DGND1
SCKO1
SCKO0
DGND3
DGND2
MCKO2
MCKO1
(1)
(1)
(1)
3
4
(4)
FS1 (MD)
FS2 (MC)
SR(MS)
5
6
7
V
CC
V
DD
2
8
(2)
(1)
(3)
AGND
XT1
CSEL
XT2
9
10
(3)
Clock Outputs (5)
(1)
(2)
(3)
(4)
0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout
10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout
27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2
This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced
controller.
For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers,
especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern
between them.
(5)
Figure 15. Typical Connection Diagram
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SLES065 – DECEMBER 2002
BLOCK DIAGRAM OF DVD PLAYER APPLICATION
PLL1707/8
384 f
S
SCKO3
27 MHz
Crystal
256 f
S
SCKO2
27 MHz
MCKO1/2
SCKO0
Front
CD-DA/
DVD DSP
MPEG/AC-3
Audio Decoder
Surround
PCM/DSD1608
Center, Subwoofer
Down Mix
BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION
MPEG
Encoder
PCM1802
SCKO1
PLL1707/8
MCKO1/2
XTI
SCKO2, 3
MPEG
Decoder
PCM1742
27-MHz Master Clock
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SLES065 – DECEMBER 2002
MECHANICAL DATA
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.008 (0,20) NOM
0.150 (3,81)
0.228 (5,80)
Gauge Plane
1
12
A
0.010 (0,25)
0°–8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
A MIN
M0–137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/02
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO–137.
19
MECHANICAL DATA
MSOI004E JANUARY 1995 – REVISED MAY 2002
DBQ (R–PDSO–G**)
PLASTIC SMALL–OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.150 (3,81) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane
1
12
A
0.010 (0,25)
0°–8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0–137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO–137.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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