SHC298JU [BB]
Monolithic SAMPLE/HOLD AMPLIFIER; 单片采样/保持放大器
| 型号： | SHC298JU |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Monolithic SAMPLE/HOLD AMPLIFIER |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
SHC298
SHC298A
Monolithic
SAMPLE/HOLD AMPLIFIER
FEATURES
DESCRIPTION
● 12-BIT THROUGHPUT ACCURACY
● LESS THAN 10µs ACQUISITION TIME
● WIDEBAND NOISE LESS THAN 20µVrms
● RELIABLE MONOLITHIC CONSTRUCTION
● 1010Ω INPUT RESISTANCE
The SHC298 and SHC298A are high-performance
monolithic sample/hold amplifiers featuring high DC
accuracy with fast acquisition times and a low droop
rate. Dynamic performance and holding performance
can be optimized with proper selection of the external
holding capacitor. With a 1000pF holding capacitor,
12-bit accuracy can be achieved with a 6µs acquisition
time. Droop rates less than 5mV/min are possible with
a 1µF holding capacitor.
● TTL-CMOS-COMPATIBLE LOGIC INPUT
These sample/holds will operate over a wide supply
voltage ranging from ±5V to ±18V with very little
change in performance. A separate Offset Adjust pin
is used to adjust the offset in either the Sample on the
Hold modes. The fully differential logic inputs have
low input current, and are compatible with TTL, 5V
CMOS, and CMOS logic families.
Offset Adjust
2
30kΩ
The SHC298AM is available in a hermetically sealed
8-pin TO-99 package and is specified over a tempera-
ture range from –25°C to +85°C. The SHC298JP and
SHC298JU are 8-pin plastic DIP and SOIC packaged
parts specified over 0°C to +70°C.
5
Output
A2
A1
3
Analog
Input
150Ω
6
Hold
Capacitor
8
7
Logic
The SHC298AJP, specified over 0°C to +70°C, is
available in an 8-pin plastic DIP. The SHC298A grade
features improved gain and offset error, improved drift
over temperature, and faster acquisition time.
C1
Logic
Reference
Mode Control (S/H) Input
The SHC298 family is a price-performance bargain. It
is well suited for use with several 12-bit A/D convert-
ers in data acquisition systems, data distribution
systems, and analog delay circuits.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1977 Burr-Brown Corporation
PDS-373E
Printed in U.S.A. August, 1996
SPECIFICATIONS
ELECTRICAL
At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
SHC298AM, JP, JU
SHC298AJP
TYP
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
ANALOG INPUT
Resistance
Bias Current(1)
1010
10
✻
✻
Ω
nA
50
25
DIGITAL INPUT
Pin 7
Pin 8
Circuit State
Mode Control Truth Table
0V
0V
+2.4V
+0.8V
+2.4V
+0.8V
+2.8V
+2.8V
Sample (Track)
Hold
Hold
Sample (Track)
Mode Control and Mode Control Reference Input Current
Differential Logic Threshold
10
2.4
µA
V
0.8
1.4
+1
±0.004
±2
±30
TRANSFER CHARACTERISTICS
ACCURACY (+25°C)
Gain
Gain Error
Input Voltage Offset (adjust to zero)(1)
Droop Rate(1)
Power Supply Rejection
✻
±0.001
±1
✻
✻
V/V
%
mV
µV/ms
µV/V
±0.010
±7
±0.005
±2
±25
±100
✻
ACCURACY DRIFT
Gain Drift
Input Offset Drift
Droop Rate at TJ = +85°C
3
15
10
4
70
1
✻
✻
2
25
ppm/°C
µV/°C
mV/ms
DYNAMIC CHARACTERISTICS
Aperture Time : Negative Input Step
Positive Input Step
Acquisition Time (C = 1000pF): to ±0.1%, 10V Step
Sample/Hold Transient: Peak Amplitude
Settling to 1mV
200
150
5
160
1
✻
✻
4
✻
✻
ns
ns
µs
mV
µs
6
Feedthrough (Response to 10V Input Step)
±0.007
±0.004
% of 20V
OUTPUT
ANALOG OUTPUT
Voltage Range
Current Range
±11.5
±2
0.5
✻
✻
✻
V
mA
Impedance (in Hold Mode)
4
✻
Ω
POWER SUPPLY
Rate Voltage
Range
15
✻
✻
VDC
VDC
mA
±5
±18
±6.5
✻
✻
✻
Current(1)
±4.5
✻ Same as specifications for SHC298AM, JP, JU.
NOTES: (1) These parameters guaranteed over a supply voltage range of ±5V to = ±18V. (2) Charge offset is sensitive to stray capacitive coupling between input
logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the
charge offset is inversely proportional to hold capacitor value.
®
SHC298/298A
2
PIN CONFIGURATIONS
Top View
TO-99
Top View
Plastic DIP/Small Outline
Tab
8
Mode Control (S/H) Input
Mode Control
8
Mode Control
Reference
+VCC
1
2
3
4
+VCC
1
Logic
7
Input
Logic
+VCC
Offset
Adjust
Mode Control
7
Reference
1kΩ
Hold Cap
6
2
Analog
Input
6
5
Hold Capacitor
Output
24kΩ
3
Output
5
Analog
Input
–VCC
4
–VCC
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
Supply Voltage .................................................................................. ±18V
Power Dissipation (Package Limitation) ........................................ 500mV
Junction Temperature, TJ MAX
PACKAGE
DRAWING TEMPERATURE
NUMBER(1)
PRODUCT
PACKAGE
RANGE
AM................................................................................................ 125°C
JP, JU .......................................................................................... 100°C
Operating Temperature Range ....................................... –25°C to +85°C
Storage Temperature Range ........................................ –65°C to +150°C
Input Voltage ....................................................... Equal to Supply Voltage
Logic-to-Logic Reference Differential Voltage(1) ..................... +7V, –30V
Output Short Circuit Duration ......................................................Indefinite
Hold Capacitor Short Circuit Duration ................................................. 10s
Lead Temperature (soldering, 10s) ................................................. 300°C
SHC298AM
SHC298JP
SHC298JU
SHC298AJP
TO-99
8-Pin Plastic DIP
8-Lead SOIC
001
006
182
006
–25°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8-Pin Plastic DIP
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
NOTE: (1) Although the differential voltage may not exceed the limits given,
the common-mode voltage on the logic pins may be equal to the supply
voltages without causing damage to the circuit. For proper logic operation,
however, one of the logic pins must always be at least 2V below the positive
supply and 3V above the negative supply.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
SHC298/298A
TYPICAL PERFORMANCE CURVES
At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
CHARGE OFFSET
APERTURE TIME
+VCC = –VCC = 15V
100
10
1
500
400
300
200
VIN = 0V
∆VOUT ≤ mV
∆VIN = 10V
TJ = 25°C
Negative
Input Step
Positive
Input Step
0.1
100
0
0.01
0.0001
0.001
0.01
0.1
1
–50
–25
0
25
50
75
100
125
150
Hold Capacitor (µF)
Junction Temperature (°C)
SAMPLE-TO-HOLD
OUTPUT DROOP RATE
TRANSIENT SETTLING TIME
100
10–1
10–2
2
1.8
1.6
1.4
1.2
1
+VCC = –VCC = 15V
Settling to 1mV
TJ = 125°C
TJ = 70°C
0.8
0.6
0.4
10–3
10–4
TJ = 25°C
TJ = 0°C
0.2
0
0.0001
0.001
0.01
Hold Capacitor (µF)
0.1
1
–50
–25
0
25
50
75
100
125
150
Junction Temperature (°C)
OUTPUT NOISE
ACQUISITION TIME
160
140
120
100
80
1
VIN = 0V to ±10V
TJ = 25°C
“Hold” Mode
10
0.1%
60
100
40
0.01%
“Sample” Mode
100
20
0
1000
10
1k
10k
100k
0.001
0.01
0.1
1
Frequency (Hz)
Hold Capacitor (µF)
®
SHC298/298A
4
TYPICAL PERFORMANCE CURVES (CONT)
At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
DYNAMIC SAMPLING ERROR
GAIN ERROR
100
10
1
0.3
0.2
0.1
0
+VCC = –VCC = 15V
J = 25°C
TJ = 25°C
RL = 10kΩ
Sample Mode
T
1000pF
Hold Capacitor
0.01µF
–0.1
0.1µF
Slope ≈ 0.0007%
0.1
3000pF
–0.2
–0.3
1µF
0.01
–15
–10
–5
0
5
10
15
0.1
1
10
100
1000
Output Voltage (V)
Input Slew Rate (V/ms)
POWER SUPPLY REJECTION
CHARGE OFFSET
1.6
1.2
0.8
0.4
0
160
140
120
100
80
TJ = 25°C
+VCC = –VCC = 15V
VOUT = 0V
CH = 0.01µF
TJ = 25°C
TJ = –55°C
Positive Supply
Negative Supply
–0.4
–0.8
60
TJ = 125°C
TJ = 25°C
40
–1.2
–1.6
20
0
–15
–10
–5
0
5
10
15
100
1k
10k
100k
1M
Input Voltage (V)
Frequency (Hz)
INPUT BIAS CURRENT
FEEDTHROUGH REJECTION RATIO
130
25
20
15
10
5
+VCC = –VCC = 15V
IN = 10Vp-p
J = 25°C
120
110
100
90
V
C
H ≥ 0.1µF
T
CH = 0.01µF
CH = 1000pF
80
0
70
–5
–10
–15
60
50
–50
–25
–0
25
50
75
100
125
150
10
100
1k
10k
100k
1M
Junction Temperature (°C)
Frequency (Hz)
®
5
SHC298/298A
TYPICAL PERFORMANCE CURVES (CONT)
At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
PHASE AND GAIN
(Input to Output, Small Signal)
CHARGE OFFSET
5
0
80
70
60
50
40
30
20
3.5
3
CH = 0
CH = 1000pF
CH = 0.01µF
TJ = 25°C
VIN = 0V
–5
2.5
2
CH = 0.01µF
–10
CH = 1000pF
1.5
1
CH = 0.01µF
0.5
10
0
0
CH = 0
1M
C
H ≥ 0.1µF
–0.5
1k
10k
100k
Frequency (Hz)
10M
0.01
0.1
1
10
100
Logic Slew Rate (V/µs)
DISCUSSION OF
SPECIFICATIONS
THROUGHPUT NONLINEARITY
ACQUISITION TIME
Throughput nonlinearity is defined as total Hold mode,
nonadjustable, input to output error caused by charge offset,
gain nonlinearity, 1ms of droop, feedthrough, and thermal
transients. It is the inaccuracy due to these errors which
cannot be corrected by offset and gain adjustments. Through-
put nonlinearity is tested with a 1000pF holding capacitor,
10V input changes, 10µs acquisition time, and 1ms Hold
time (see Figure 1).
Acquisition Time is the time required for the sample/hold
output to settle within a given error band of its final value
when the mode control is switched from Hold to Sample.
Control
Signal
Sample
Hold
Sample
Time
GAIN ACCURACY
Gain Accuracy is the difference between input and output
voltage (when in the Sample mode) due to amplifier gain
errors.
Input
Voltage
DROOP RATE
Droop Rate is the voltage decay at the output when in the
Hold mode due to storage capacitor, FET switch leakage
currents, and output amplifier bias current.
Time
FEEDTHROUGH
Acquisition
Time
Feedthrough is the amount of the input voltage change that
appears at the output when the amplifier is in the Hold mode.
Output
Voltage
Gain
Error
Actual
APERTURE TIME
Aperture Time is the time required to switch from Sample to
Hold. The time is measured from the 50% point of the mode
control transition to the time at which the output stops
tracking the input.
Aperture Time
Throughput
Error
Ideal
Time
Offset Error
FIGURE 1. Sample/Hold Errors.
®
SHC298/298A
6
CHARGE OFFSET
With a 0.1µF storage capacitor, the output may be held 10
seconds with less than 0.1% error. With a 1µF storage
capacitor, the output may be held more than 15 minutes with
less than 1% error.
Charge Offset is the offset that results from the charge
coupled through the gate capacitance of the switching FET.
This charge is coupled into the storage capacitor when the
FET is switched to the “hold” mode.
CAPACITIVE LOADING
SHC298 is sensitive to capacitive loading on the output and
may oscillate. When driving long lines, a buffer should be
used.
OPERATING INSTRUCTIONS
EXTERNAL CAPACITOR SELECTION
Capacitors with high insulation resistance and low dielectric
absorption, such as Teflon®, polystyrene or polypropylene
units, should be used as storage elements (polystyrene should
not be used above +85°C). Care should be taken in the
printed circuit layout to minimize AC and DC leakage
currents from the capacitor to reduce charge offset and
droop errors.
HIGH SPEED DATA ACQUISITION
The minimum sample time for one channel in a data acqui-
sition system is usually considered to be the acquisition time
of the sample/hold plus the conversion time of the analog-to-
digital converter. If two or more sample/holds are used with
a high-speed multiplexer, the acquisition time of the sample/
hold can be virtually eliminated. While the first channel is in
hold and switched on to the ADC, the multiplexer may be
addressed to the next channel. The second sample/hold will
have acquired this data by the time the conversion is com-
plete. Then, the sample/holds reverse roles and another
channel is addressed (see Figure 5). For low-level systems,
and instrumentation amplifier and double-ended multiplexer
may be connected to the sample/hold inputs. The settling
time of the multiplexer, instrumentation amplifier, and
sample/hold can be eliminated from the channel conversion
time as before.
The value of the external capacitor determines the droop,
charge offset and acquisition time of the Sample/Hold. Both
droop and charge offset will vary linearly with capacitance
from the values given in the specification table for a 0.001µF
capacitor. With a capacitor of 0.01µF, the droop will reduce
to approximately 2.5µV/ms and the charge offset to approxi-
mately 1.5mV. The behavior of acquisition time with changes
in external capacitance is shown in the Typical Performance
Curves.
OFFSET ADJUSTMENT
The offset should be adjusted with the input grounded.
During the adjustment, the sample/hold should be switching
continuously between the Sample and the Hold mode. The
error should then be adjusted to zero when the unit is in the
Hold mode. In this way, charge offset as well as amplifier
offset will be adjusted. When a 0.001µF capacitor is used, it
will not be possible to adjust the full offset error at the
sample/hold. It should be adjusted elsewhere in the system.
–15VDC
0.005µF
0.1µF
Storage
To A/D
Converter
Analog
Inputs
4
6
3
8
5
SHC298
PAM
Output
7
2
1
Analog
Multiplexer
APPLICATIONS
Mode
Control
0.1µF
DATA ACQUISITION
1kΩ
The SHC298 may be used to hold data for conversion with
an analog-to-digital converter or used to provide Pulse
Amplitude Modulation (PAM) data output (see Figures 2
and 3).
24kΩ
+15VDC
FIGURE 2. Data Acquisition.
DATA DISTRIBUTION
The SHC298 may be used to hold the output of a digital-to-
analog converter whose digital inputs are multiplexed (see
Figure 4).
PAM Output
Actual Input
TEST SYSTEMS
The SHC298 is also well suited for use in test systems to
acquire and hold data transients for human operators or for
the other parts of the test system such as comparators, digital
voltmeters, etc.
Mode Control Hold
FIGURE 3. PAM Output.
®Teflon, DuPont de Nemours
®
7
SHC298/298A
1000pF
Storage
0.1µF
Capacitor
–15VDC
6
4
6
Analog
Output
3
8
5
SHC298
3
5
SHC298
Channel 1
1
Digital
Output
7
2
1
Ch1
Ch2
Offset
Adjust
B1
B2
8
0.1µF
(1)
(0)
A/D
Converter
1000pF
1kΩ
MUX
24kΩ
+15VDC
6
ChN
B12
6
–15VDC
High
Speed
Switch
Analog
Input
Address
Digital
Inputs
4
7
3
5
SHC298
3
8
2
5
SHC298
D/A
Converter
Channel 2
2
1
8
Mode Control
FIGURE 5. “Ping-Pong” Sample Holds.
+15VDC
Additional SHC298 Units
–15VDC
4
7
6
3
8
5
SHC298
Channel N
2
1
Mode
Control
Logic
Digital
Inputs
+15VDC
FIGURE 4. Data Distribution.
®
SHC298/298A
8
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