TSC2046IPWR [BB]
Low Voltage I/O TOUCH SCREEN CONTROLLER; 低电压I / O触摸屏控制器
| 型号： | TSC2046IPWR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Low Voltage I/O TOUCH SCREEN CONTROLLER |
| 文件： | 总23页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T
S
®
T
S
C
®
C
2
TSC2046
2
0
4
6
0
4
6
T
®
S
C
2
0
4
6
SBAS265C – OCTOBER 2002 – REVISED JULY 2004
Low Voltage I/O
TOUCH SCREEN CONTROLLER
FEATURES
DESCRIPTION
z SAME PINOUT AS ADS7846
The TSC2046 is a next-generation version to the ADS7846
4-wire touch screen controller which supports a low-voltage
I/O interface from 1.5V to 5.25V. The TSC2046 is 100% pin-
compatible with the existing ADS7846, and will drop into the
same socket. This allows for easy upgrade of current appli-
cations to the new version. The TSC2046 also has an on-
chip 2.5V reference that can be used for the auxiliary input,
battery monitor, and temperature measurement modes. The
reference can also be powered down when not used to
conserve power. The internal reference operates down to
2.7V supply voltage, while monitoring the battery voltage
from 0V to 6V.
z 2.2V TO 5.25V OPERATION
z 1.5V TO 5.25V DIGITAL I/O
z INTERNAL 2.5V REFERENCE
z DIRECT BATTERY MEASUREMENT (0V to 6V)
z ON-CHIP TEMPERATURE MEASUREMENT
z TOUCH-PRESSURE MEASUREMENT
z QSPITM AND SPITM 3-WIRE INTERFACE
z AUTO POWER-DOWN
z AVAILABLE IN TSSOP-16, QFN-16, AND
The low-power consumption of < 0.75mW typ at 2.7V (refer-
ence off), high-speed (up to 125kHz sample rate), and on-
chip drivers make the TSC2046 an ideal choice for battery-
operated systems such as personal digital assistants (PDAs)
with resistive touch screens, pagers, cellular phones, and
other portable equipment. The TSC2046 is available in
TSSOP-16, QFN-16, and VFBGA-48 packages and is speci-
fied over the –40°C to +85°C temperature range.
VFBGA-48 PACKAGES
APPLICATIONS
z PERSONAL DIGITAL ASSISTANTS
z PORTABLE INSTRUMENTS
z POINT-OF-SALE TERMINALS
z PAGERS
z TOUCH SCREEN MONITORS
z CELLULAR PHONES
Pen
Detect
PENIRQ
US Patent No. 6246394
QSPI and SPI are registered trademarks of Motorola.
+VCC
X+
X–
Temperature
SAR
Sensor
IOVDD
Y+
Y–
TSC2046
DOUT
BUSY
Comparator
CS
6-Channel
MUX
Serial
Data
CDAC
In/Out
DCLK
DIN
Battery
Monitor
V
BAT
AUX
Internal 2.5V
Reference
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002-2004, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
ISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
+VCC and IOVDD to GND .....................................................–0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
D
Digital Inputs to GND .......................................... –0.3V to IOVDD + 0.3V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ....................................... –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings can cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
NOMINAL
PENIRQ
PULLUP
RESISTOR
VALUES
MAXIMUM
INTEGRAL
LINEARITY
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
TSC2046
ERROR (LSB) PACKAGE-LEAD DESIGNATOR
50kΩ
90kΩ
±2
±2
VFBGA-48
VFBGA-48
GQC
GQC
–40°C to +85°C
–40°C to +85°C
AZ2046
TSC2046IGQCR
Tape and Reel, 2500
TSC2046-90
AZ2046A
TSC2046IGQCR-90 Tape and Reel, 2500
TSC2046
50kΩ
±2
TSSOP-16
PW
–40°C to +85°C
TSC2046I
TSC2046IPW
Rails, 100
"
"
"
"
"
"
"
TSC2046IPWR
Tape and Reel, 2500
TSC2046
50kΩ
"
±2
"
QFN-16
"
RGV
"
–40°C to +85°C
TSC2046
TSC2046IRGVT
TSC2046IRGVR
Tape and Reel, 250
Tape and Reel, 2500
"
"
"
NOTE: (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet.
TSC2046
2
SBAS265C
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD,
and +VCC must be • IOVDD, unless otherwise noted.
TSC2046
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input-Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VCC + 0.2
+0.2
V
V
V
Negative Input
Capacitance
Leakage Current
25
0.1
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Offset Error
12
Bits
Bits
11
±2
±6
±4
LSB(1)
LSB
Gain Error
External VREF
LSB
Noise
Including Internal VREF
70
70
µVrms
dB
Power-Supply Rejection
SAMPLING DYNAMICS
Conversion Time
12
CLK Cycles
Acquisition Time
3
CLK Cycles
Throughput Rate
Multiplexer Settling Time
Aperture Delay
125
kHz
ns
ns
500
30
Aperture Jitter
Channel-to-Channel Isolation
100
100
ps
dB
VIN = 2.5Vp-p at 50kHz
Duration 100ms
SWITCH DRIVERS
On-Resistance
Y+, X+
Y–, X–
Drive Current(2)
5
6
Ω
Ω
mA
50
REFERENCE OUTPUT
Internal Reference Voltage
Internal Reference Drift
Quiescent Current
2.45
1.0
2.50
15
500
2.55
V
ppm/°C
µA
REFERENCE INPUT
Range
+VCC
V
Input Impedance
SER/DFR = 0, PD1 = 0,
Internal Reference Off
Internal Reference On
1
GΩ
250
Ω
BATTERY MONITOR
Input Voltage Range
Input Impedance
Sampling Battery
Battery Monitor Off
Accuracy
0.5
6.0
V
10
1
kΩ
GΩ
%
VBAT = 0.5V to 5.5V, External VREF = 2.5V
VBAT = 0.5V to 5.5V, Internal Reference
–2
–3
+2
+3
%
TEMPERATURE MEASUREMENT
Temperature Range
Resolution
–40°C
+85
°C
°C
°C
°C
°C
Differential Method(3)
TEMP0(4)
Differential Method(3)
TEMP0(4)
1.6
0.3
±2
Accuracy
±3
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH
VIL
VOH
VOL
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
IOVDD • 0.7
–0.3
IOVDD • 0.8
IOVDD + 0.3
0.3 • IOVDD
V
V
V
V
0.4
Data Format
Straight Binary
POWER-SUPPLY REQUIREMENTS
(5)
+VCC
Specified Performance
Operating Range
2.7
2.2
1.5
3.6
5.25
+VCC
650
V
V
V
µA
µA
µA
µA
IOVDD(6)
Quiescent Current(7)
Internal Reference Off
Internal Reference On
280
780
220
fSAMPLE = 12.5kHz
Power-Down Mode with
CS = DCLK = DIN = IOVDD
+VCC = +2.7V
3
Power Dissipation
1.8
mW
°C
TEMPERATURE RANGE
Specified Performance
–40
+85
NOTES: (1) LSB means least significant bit. With VREF = +2.5V, one LSB is 610µV. (2) Assured by design, but not tested. Exceeding 50mA source current may result
in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is –2.1mV/°C. (5) TSC2046 operates
down to 2.2V. (6) IOVDD must be - +VCC. (7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with
PD0 = 0.
TSC2046
SBAS265C
3
www.ti.com
PIN CONFIGURATION
Top View
VFBGA
Top View
TSSOP
DCLK
CS
DIN BUSY DOUT
+VCC
X+
1
2
3
4
5
6
7
8
16 DCLK
15 CS
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
NC
Y+
14 DIN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
X–
13 BUSY
12 DOUT
11 PENIRQ
10 IOVDD
+VCC
+VCC
X+
PENIRQ
IOVDD
VREF
TSC2046
Y–
GND
VBAT
AUX
NC
NC
NC
9
VREF
Y+
AUX
NC
NC
NC
NC
G
X–
Y–
GND GND VBAT
Top View
TSSOP
BUSY
DIN
1
2
3
4
12 AUX
11 VBAT
10 GND
TSC2046
CS
DCLK
9
Y–
PIN DESCRIPTION
TSSOP PIN #
VFBGA PIN #
QFN PIN #
NAME
DESCRIPTION
1
2
B1 and C1
5
6
+VCC
X+
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
D1
3
E1
7
Y+
4
G2
8
X–
5
G3
9
Y–
6
G4 and G5
10
11
12
13
14
15
16
GND
VBAT
AUX
VREF
IOVDD
PENIRQ
DOUT
7
G6
E7
D7
C7
B7
A6
Battery Monitor Input
Auxiliary Input to ADC
8
9
Voltage Reference Input/Output
Digital I/O Power Supply
Pen Interrupt
10
11
12
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13
14
15
A5
A4
A3
1
2
3
BUSY
DIN
Busy Output. This output is high impedance when CS is high.
Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
CS
16
A2
4
DCLK
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
TSC2046
4
SBAS265C
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
+V
SUPPLY CURRENT vs TEMPERATURE
IOVDD SUPPLY CURRENT vs TEMPERATURE
CC
400
350
300
250
200
150
100
30
25
20
15
10
5
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
POWER-DOWN SUPPLY CURRENT vs TEMPERATURE
+VCC SUPPLY CURRENT vs +VCC
140
120
100
80
450
400
350
300
250
200
150
100
fSAMPLE = 125kHz
fSAMPLE = 12.5kHz
60
40
–40
–20
0
20
40
60
80
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Temperature (°C)
+VCC (V)
IOVDD SUPPLY CURRENT vs IOVDD
+VCC ≥ IOVDD
MAXIMUM SAMPLE RATE vs +VCC
1M
100k
10k
1k
60
50
40
30
20
10
0
fSAMPLE = 125kHz
fSAMPLE = 12.5kHz
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
+VCC (V)
IOVDD (V)
TSC2046
SBAS265C
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
CHANGE IN GAIN vs TEMPERATURE
CHANGE IN OFFSET vs TEMPERATURE
0.15
0.10
0.05
0
0.6
0.4
0.2
0
–0.05
–0.10
–0.15
–0.2
–0.4
–0.6
–40
–20
0
20
40
60
80
100
125
5.0
–40
–20
0
20
40
60
80
100
100
100
Temperature (°C)
Temperature (°C)
REFERENCE CURRENT vs SAMPLE RATE
REFERENCE CURRENT vs TEMPERATURE
14
12
10
8
18
16
14
12
10
8
6
4
2
0
6
0
25
50
75
100
–40
–20
0
20
40
60
80
Sample Rate (kHz)
Temperature (°C)
SWITCH ON-RESISTANCE vs +VCC
SWITCH ON-RESISTANCE vs TEMPERATURE
(X+, Y+: +VCC to Pin; X–, Y–: Pin to GND)
(X+, Y+: +VCC to Pin; X–, Y–: Pin to GND)
8
7
6
5
4
3
2
1
8
7
6
5
4
3
Y–
Y–
X+, Y+
X–
X–
X+, Y+
–40
–20
0
20
40
60
80
2.0
2.5
3.0
3.5
4.0
4.5
Temperature (°C)
+VCC (V)
TSC2046
6
SBAS265C
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
MAXIMUM SAMPLING RATE vs RIN
INTERNAL VREF vs TEMPERATURE
2.5080
2.5075
2.5070
2.5065
2.5060
3.5055
2.5050
2.5045
2.5040
2.5035
2.5030
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
INL: RIN = 500Ω
INL: RIN = 2kΩ
DNL: RIN = 500Ω
DNL: RIN = 2kΩ
20
40
60
80
100 120 140 160 180 200
Sampling Rate (kHz)
Temperature (°C)
INTERNAL VREF vs +VCC
INTERNAL V
REF
vs TURN-ON TIME
2.510
2.505
2.500
2.495
2.490
2.485
2.480
100
80
60
40
20
0
No Cap
(42µs)
12-Bit Settling
1µF Cap
(1240µs)
12-Bit Settling
2.5
3.0
3.5
4.0
+VCC (V)
4.5
5.0
0
200
400
600
800
1000
1200
1400
Turn-On Time (µs)
TEMP DIODE VOLTAGE vs TEMPERATURE
TEMP0 DIODE VOLTAGE vs +VCC
850
800
750
700
650
600
550
500
450
604
602
600
598
596
594
90.1mV
TEMP1
135.1mV
TEMP0
2.7
3.0
3.3
+VCC (V)
Temperature (°C)
TSC2046
SBAS265C
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
TEMP1 DIODE VOLTAGE vs +VCC
720
718
716
714
712
710
2.7
3.0
3.3
+VCC (V)
+VCC. The value of the reference voltage directly sets the
input range of the converter.
THEORY OF OPERATION
The TSC2046 is a classic successive approximation register
(SAR) analog-to-digital converter (ADC). The architecture is
based on capacitive redistribution, which inherently includes
a sample-and-hold function. The converter is fabricated on a
0.6µm CMOS process.
The analog input (X-, Y-, and Z-Position coordinates, auxiliary
input, battery voltage, and chip temperature) to the converter is
provided via a multiplexer. A unique configuration of low on-
resistance touch panel driver switches allows an unselected
ADC input channel to provide power and the accompanying pin
to provide ground for an external device, such as a touch
screen. By maintaining a differential input to the converter and
a differential reference architecture, it is possible to negate the
error from each touch panel driver switch’s on-resistance (if this
is a source of error for the particular measurement).
The basic operation of the TSC2046 is shown in Figure 1.
The device features an internal 2.5V reference and uses an
external clock. Operation is maintained from a single supply
of 2.7V to 5.25V. The internal reference can be overdriven
with an external, low-impedance source between 1V and
+2.7V to +5V
TSC2046
DCLK A2
1µF
+
Serial/Conversion Clock
Chip Select
B1 +VCC
C1 +VCC
D1 X+
to
0.1µF
10µF
(Optional)
CS A3
DIN A4
Serial Data In
Converter Status
Serial Data Out
Pen Interrupt
E1 Y+
BUSY A5
DOUT A6
PENIRQ B7
IOVDD C7
VREF D7
Touch
Screen
G2 X–
G3 Y–
To Battery
Voltage
G6 VBAT
E7 AUX
Auxiliary Input
G4
G5
GND
GND
Regulator
NOTE: BGA package and pin names shown.
FIGURE 1. Basic Operation of the TSC2046.
TSC2046
8
SBAS265C
www.ti.com
ANALOG INPUT
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The
input current into the analog inputs depends on the conver-
sion rate of the device. During the sample period, the source
must charge the internal sampling capacitor (typically 25pF).
After the capacitor has been fully charged, there is no further
input current. The rate of charge transfer from the analog
source to the converter is a function of conversion rate.
Figure 2 shows a block diagram of the input multiplexer on
the TSC2046, the differential input of the ADC, and the
differential reference of the converter. Table I and Table II
show the relationship between the A2, A1, A0, and SER/DFR
control bits and the configuration of the TSC2046. The
control bits are provided serially via the DIN pin—see the
Digital Interface section of this data sheet for more details.
+VCC
VREF
PENIRQ IOVDD
TEMP1
TEMP0
Level
Shifter
50kΩ
or
Logic
90kΩ
A2-A0
SER/DFR
(Shown 001B)
(Shown Low)
X+
X–
Ref On/Off
Y+
Y–
+REF
ADC
+IN
–IN
2.5V
Reference
–REF
7.5kΩ
VBAT
2.5kΩ
Battery
On
AUX
GND
FIGURE 2. Simplified Diagram of Analog Input.
A2
A1
A0
VBAT
AUXIN
TEMP
Y–
X+
Y+
Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS
Y-DRIVERS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+IN (TEMP0)
Off
Off
Off
X–, On
X–, On
On
Off
On
Off
Y+, On
Y+, On
Off
+IN
+IN
Measure
+IN
Measure
+IN
Measure
+IN
Measure
+IN
Off
Off
Off
Off
+IN (TEMP1)
TABLE I. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high).
A2
A1
A0
+REF
–REF
Y–
X+
Y+
Y-POSITION
X-POSITION
Z1-POSITION
Z2-POSITION
DRIVERS ON
0
0
1
1
0
1
0
0
1
1
0
1
Y+
Y+
Y+
X+
Y–
X–
X–
X–
+IN
+IN
Measure
Y+, Y–
Y+, X–
Y+, X–
X+, X–
Measure
+IN
Measure
+IN
Measure
TABLE II. Input Configuration (DIN), Differential Reference Mode (SER/DFR low).
TSC2046
SBAS265C
9
www.ti.com
INTERNAL REFERENCE
is made by connecting the X+ input to the ADC, turning on the
Y+ and Y– drivers, and digitizing the voltage on X+ (Figure 4
shows a block diagram). For this measurement, the resistance
in the X+ lead does not affect the conversion (it does affect the
settling time, but the resistance is usually small enough that
this is not a concern). However, since the resistance between
Y+ and Y– is fairly low, the on-resistance of the Y drivers does
make a small difference. Under the situation outlined so far, it
is not possible to achieve a 0V input or a full-scale input
regardless of where the pointing device is on the touch screen
because some voltage is lost across the internal switches. In
addition, the internal switch resistance is unlikely to track the
resistance of the touch screen, providing an additional source
of error.
The TSC2046 has an internal 2.5V voltage reference that can
be turned on or off with the control bit, PD1 (see Table V and
Figure 3). Typically, the internal reference voltage is only used
in the single-ended mode for battery monitoring, temperature
measurement, and for using the auxiliary input. Optimal touch
screen performance is achieved when using the differential
mode. The internal reference voltage of the TSC2046 must be
commanded to be off to maintain compatibility with the
ADS7843. Therefore, after power-up, a write of PD1 = 0 is
required to insure the reference is off (see the Typical Char-
acteristics for power-up time of the reference from power-
down).
Reference
Power-Down
+VCC
VREF
Y+
VREF
Band
Buffer
Gap
+REF
Converter
–REF
+IN
–IN
X+
Y–
Optional
To
CDAC
FIGURE 3. Simplified Diagram of the Internal Reference.
REFERENCE INPUT
GND
FIGURE 4. Simplified Diagram of Single-Ended Reference
SER/DFR high, Y switches enabled, X+ is ana-
The voltage difference between +REF and –REF (see Figure 2)
sets the analog input range. The TSC2046 operates with a
reference in the range of 1V to +VCC. There are several critical
items concerning the reference input and its wide voltage range.
As the reference voltage is reduced, the analog voltage weight
of each digital output code is also reduced. This is often referred
to as the LSB (least significant bit) size and is equal to the
reference voltage divided by 4096 in 12-bit mode. Any offset or
gain error inherent in the ADC appears to increase, in terms of
LSB size, as the reference voltage is reduced. For example, if
the offset of a given converter is 2LSBs with a 2.5V reference,
it is typically 5LSBs with a 1V reference. In each case, the
actual offset of the device is the same, 1.22mV. With a lower
reference voltage, more care must be taken to provide a clean
layout including adequate bypassing, a clean (low-noise, low-
ripple) power supply, a low-noise reference (if an external
reference is used), and a low-noise input signal.
(
log input).
This situation can be remedied as shown in Figure 5. By setting
the SER/DFR bit low, the +REF and –REF inputs are connected
directly to Y+ and Y–, respectively, which makes the analog-to-
digital conversion ratiometric. The result of the conversion is
+VCC
Y+
+REF
+IN
X+
The voltage into the VREF input directly drives the capacitor
digital-to-analog converter (CDAC) portion of the TSC2046.
Therefore, the input current is very low (typically < 13µA).
Converter
–IN
–REF
There is also a critical item regarding the reference when
making measurements while the switch drivers are ON. For this
discussion, it is useful to consider the basic operation of the
TSC2046, (see Figure 1). This particular application shows
the device being used to digitize a resistive touch screen. A
measurement of the current Y-Position of the pointing device
Y–
GND
FIGURE 5. Simplified Diagram of Differential Reference
(
SER/DFR low, Y switches enabled, X+ is
analog input).
TSC2046
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always a percentage of the external resistance, regardless of
how it changes in relation to the on-resistance of the internal
switches. Note that there is an important consideration regarding
power dissipation when using the ratiometric mode of operation
(see the Power Dissipation section for more details).
offers two modes of operation. The first mode requires
calibration at a known temperature, but only requires a single
reading to predict the ambient temperature. A diode is used
(turned on) during this measurement cycle. The voltage
across the diode is connected through the MUX for digitizing
the forward bias voltage by the ADC with an address of
A2 = 0, A1 = 0, and A0 = 0 (see Table I and Figure 6 for
details). This voltage is typically 600mV at +25°C with a 20µA
current through the diode. The absolute value of this diode
voltage can vary a few millivolts. However, the TC of this
voltage is very consistent at –2.1mV/°C. During the final test
of the end product, the diode voltage would be stored at a
known room temperature, in memory, for calibration pur-
poses by the user. The result is an equivalent temperature
measurement resolution of 0.3°C/LSB (in 12-bit mode).
As a final note about the differential reference mode, it must
be used with +VCC as the source of the +REF voltage and
cannot be used with VREF. It is possible to use a high-
precision reference on VREF and single-ended reference
mode for measurements which do not need to be ratiometric.
In some cases, it is possible to power the converter directly
from a precision reference. Most references can provide
enough power for the TSC2046, but might not be able to
supply enough current for the external load (such as a
resistive touch screen).
TOUCH SCREEN SETTLING
+VCC
In some applications, external capacitors may be required
across the touch screen for filtering noise picked up by the
touch screen (e.g., noise generated by the LCD panel or
backlight circuitry). These capacitors provide a low-pass filter
to reduce the noise, but cause a settling time requirement
when the panel is touched that typically shows up as a gain
error. There are several methods for minimizing or eliminating
this issue. The problem is the input and/or reference has not
settled to the final steady-state value prior to the ADC sampling
the input(s) and providing the digital output. Additionally, the
reference voltage may still be changing during the measure-
ment cycle. Option 1 is to stop or slow down the TSC2046
DCLK for the required touch screen settling time. This allows
the input and reference to have stable values for the Acquire
period (3 clock cycles of the TSC2046; see Figure 9). This
works for both the single-ended and the differential modes.
Option 2 is to operate the TSC2046 in the differential mode
only for the touch screen measurements and command the
TSC2046 to remain on (touch screen drivers ON) and not go
into power-down (PD0 = 1). Several conversions are made
depending on the settling time required and the TSC2046 data
rate. Once the required number of conversions have been
made, the processor commands the TSC2046 to go into its
power-down state on the last measurement. This process is
required for X-Position, Y-Position, and Z-Position measure-
ments. Option 3 is to operate in the 15 Clock-per-Conversion
mode, which overlaps the analog-to-digital conversions and
maintains the touch screen drivers on until commanded to stop
by the processor (see Figure 13).
TEMP0
TEMP1
MUX
ADC
FIGURE 6. Functional Block Diagram of Temperature Mea-
surement Mode.
The second mode does not require a test temperature calibra-
tion, but uses a two-measurement method to eliminate the
need for absolute temperature calibration and for achieving
2°C accuracy. This mode requires a second conversion with
an address of A2 = 1, A1 = 1, and A0 = 1, with a 91 times larger
current. The voltage difference between the first and second
conversion using 91 times the bias current is represented by
kT/q • ln (N), where N is the current ratio = 91,
k = Boltzmann’s constant (1.38054 • 10–23 electron volts/
degrees Kelvin), q = the electron charge (1.602189 • 10–19 C),
and T = the temperature in degrees Kelvin. This method can
provide improved absolute temperature measurement over
the first mode at the cost of less resolution (1.6°C/LSB). The
equation for solving for °K is:
TEMPERATURE MEASUREMENT
°K = q • ∆V/(k • ln (N))
where, ∆V = V (I91) – V (I1) (in mV)
(1)
In some applications, such as battery recharging, a measure-
ment of ambient temperature is required. The temperature
measurement technique used in the TSC2046 relies on the
characteristics of a semiconductor junction operating at a
fixed current level. The forward diode voltage (VBE) has a
well-defined characteristic versus temperature. The ambient
temperature can be predicted in applications by knowing the
+25°C value of the VBE voltage and then monitoring the delta
of that voltage as the temperature changes. The TSC2046
∴ °K = 2.573 °K/mV • ∆V
°C = 2.573 • ∆V(mV) – 273°K
NOTE: The bias current for each diode temperature mea-
surement is only on for 3 clock cycles (during the acquisition
mode) and, therefore, does not add any noticeable increase
in power, especially if the temperature measurement only
occurs occasionally.
TSC2046
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BATTERY MEASUREMENT
An added feature of the TSC2046 is the ability to monitor
the battery voltage on the other side of the voltage regulator
(DC/DC converter), as shown in Figure 7. The battery voltage
can vary from 0V to 6V, while maintaining the voltage to the
TSC2046 at 2.7V, 3.3V, etc. The input voltage (VBAT) is
divided down by 4 so that a 5.5V battery voltage is repre-
sented as 1.375V to the ADC. This simplifies the multiplexer
and control logic. In order to minimize the power consump-
tion, the divider is only on during the sampling period when
A2 = 0, A1 = 1, and A0 = 0 (see Table I for the relationship
between the control bits and configuration of the TSC2046).
Measure X-Position
X+
Y+
Y–
Touch
X-Position
X–
Measure Z1-Position
Y+
Y–
X+
Touch
2.7V
DC/DC
Converter
Battery
Z1-Position
X–
+
0.5V
to
5.5V
+VCC
Y+
X+
X–
Touch
0.125V to 1.375V
VBAT
ADC
Z2-Position
7.5kΩ
2.5kΩ
Y–
Measure Z2-Position
FIGURE 8. Pressure Measurement Block Diagrams.
DIGITAL INTERFACE
FIGURE 7. Battery Measurement Functional Block Diagram.
See Figure 9 for the typical operation of the TSC2046
digital interface. This diagram assumes that the source of
the digital signals is a microcontroller or digital signal
processor with a basic serial interface. Each communica-
tion between the processor and the converter, such as SPI,
SSI, or Microwire™ synchronous serial interface, consists
of eight clock cycles. One complete conversion can be
accomplished with three serial communications for a total
of 24 clock cycles on the DCLK input.
PRESSURE MEASUREMENT
Measuring touch pressure can also be done with the TSC2046.
To determine pen or finger touch, the pressure of the touch
needs to be determined. Generally, it is not necessary to have
very high performance for this test, therefore, the 8-bit resolu-
tion mode is recommended (however, calculations will be
shown here in the 12-bit resolution mode). There are several
different ways of performing this measurement. The TSC2046
supports two methods. The first method requires knowing the
X-plate resistance, measurement of the X-Position, and two
additional cross panel measurements (Z1 and Z2) of the touch
screen, as shown in Figure 8. Using Equation 2 calculates the
touch resistance:
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer and reference inputs appropriately, the
converter enters the acquisition (sample) mode and, if needed,
the touch panel drivers are turned on. After three more clock
cycles, the control byte is complete and the converter enters
the conversion mode. At this point, the input sample-and-
hold goes into the hold mode and the touch panel drivers turn
off (in single-ended mode). The next 12 clock cycles accom-
plish the actual analog-to-digital conversion. If the conver-
sion is ratiometric (SER/DFR = 0), the drivers are on during
the conversion and a 13th clock cycle is needed for the last
bit of the conversion result. Three more clock cycles are
needed to complete the last byte (DOUT will be low), which
are ignored by the converter.
X – Position Z2
RTOUCH = RX– plate
•
– 1
(2)
4096
Z
1
The second method requires knowing both the X-plate and
Y-plate resistance, measurement of X-Position and Y-Posi-
tion, and Z1. Using Equation 3 also calculates the touch
resistance:
RX−plate • X −Position
4096
RTOUCH
=
– 1
4096
Z1
(3)
Y − Position
–RY−plate 1−
4096
Microwire is a registered trademark of National Semiconductor.
TSC2046
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Control Byte
MODE—The mode bit sets the resolution of the ADC. With
this bit low, the next conversion has 12 bits of resolution,
whereas with this bit high, the next conversion has 8 bits of
resolution.
The control byte (on DIN), as shown in Table III, provides the
start conversion, addressing, ADC resolution, configuration,
and power-down of the TSC2046. Figure 9 and Tables III and
IV give detailed information regarding the order and descrip-
tion of these control bits within the control byte.
SER/DFR—The SER/DFR
bit controls the reference mode,
either single-ended (high) or differential (low). The differential
mode is also referred to as the ratiometric conversion mode
and is preferred for X-Position, Y-Position, and Pressure-
Touch measurements for optimum performance. The refer-
ence is derived from the voltage at the switch drivers, which
is almost the same as the voltage to the touch screen. In this
case, a reference voltage is not needed as the reference
voltage to the ADC is the voltage across the touch screen. In
the single-ended mode, the converter reference voltage is
Bit 7
Bit 0
(LSB)
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
S
A2
A1
A0
MODE SER/DFR PD1
PD0
TABLE III. Order of the Control Bits in the Control Byte.
BIT
NAME
DESCRIPTION
7
S
Start bit. Control byte starts with first high bit on DIN.
A new control byte can start every 15th clock cycle
in 12-bit conversion mode or every 11th clock cycle
in 8-bit conversion mode (see Figure 13).
always the difference between the V
REF and GND pins (see
Tables I and II, and Figures 2 through 5 for further informa-
tion).
6-4
3
A2-A0
MODE
Channel Select bits. Along with the SER/DFR bit, these
bits control the setting of the multiplexer input, touch driver
switches, and reference inputs (see Tables I and II).
If X-Position, Y-Position, and Pressure-Touch are measured
in the single-ended mode, an external reference voltage is
needed. The TSC2046 must also be powered from the
external reference. Caution should be observed when using
the single-ended mode such that the input voltage to the
ADC does not exceed the internal reference voltage, espe-
cially if the supply voltage is greater than 2.7V.
12-Bit/8-Bit Conversion Select bit. This bit controls
the number of bits for the next conversion: 12-bits
(low) or 8-bits (high).
2
SER/DFR Single-Ended/Differential Reference Select bit. Along
with bits A2-A0, this bit controls the setting of the
multiplexer input, touch driver switches, and reference
inputs (see Tables I and II).
NOTE: The differential mode can only be used for X-Position,
Y-Position, and Pressure-Touch measurements. All other
measurements require the single-ended mode.
1-0
PD1-PD0 Power-Down Mode Select bits. Refer to Table V for
details.
TABLE IV. Descriptions of the Control Bits within the Control Byte.
PD0 and PD1—Table V describes the power-down and the
internal reference voltage configurations. The internal refer-
ence voltage can be turned on or off independently of the
ADC. This can allow extra time for the internal reference
voltage to settle to the final value prior to making a conver-
sion. Make sure to also allow this extra wake-up time if the
internal reference is powered down. The ADC requires no
wake-up time and can be instantaneously used. Also note
Initiate START—The first bit, the S bit, must always be high
and initiates the start of the control byte. The TSC2046
ignores inputs on the DIN pin until the start bit is detected.
Addressing—The next three bits (A2, A1, and A0) select the
active input channel(s) of the input multiplexer (see Tables I, II,
and Figure 2), touch screen drivers, and the reference inputs.
CS
tACQ
DCLK
DIN
1
8
1
8
1
8
SER/
DFR
S
A2 A1 A0 MODE
Idle
PD1 PD0
Acquire
(START)
Conversion
Idle
BUSY
DOUT
11 10
(MSB)
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
Drivers 1 and 2(1)
(SER/DFR High)
Off
Off
On
Off
Drivers 1 and 2(1, 2)
(SER/DFR Low)
On
Off
NOTES: (1) For Y-Position, Driver 1 is on X+ is selected, and Driver 2 is off. For X-Position, Driver 1 is off, Y+ is selected,
and Driver 2 is on. Y– will turn on when power-down mode is entered and PD0 = 0. (2) Drivers will remain on if PD0 = 1 (no
power down) until selected input channel, reference mode, or power-down mode is changed, or CS is high.
FIGURE 9. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
TSC2046
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PD1 PD0 PENIRQ DESCRIPTION
IOVDD
0
0
Enabled Power-Down Between Conversions. When each
conversion is finished, the converter enters a
low-power mode. At the start of the next conver-
sion, the device instantly powers up to full power.
There is no need for additional delays to ensure
full operation, and the very first conversion is
valid. The Y– switch is on when in power-down.
Level
Shifter
PENIRQ
+VCC
50kΩ
or
90kΩ
+VCC
TEMP0
TEMP1
0
1
1
1
0
Disabled Reference is off and ADC is on.
Enabled Reference is on and ADC is off.
Y+
High except
when TEMP0,
TEMP1 activated.
1
Disabled Device is always powered. Reference is on and
ADC is ON.
TEMP
DIODE
TABLE V. Power-Down and Internal Reference Selection.
X+
Y–
that the status of the internal reference power-down is
latched into the part (internally) with BUSY going high. In
order to turn the reference off, an additional write to the
TSC2046 is required after the channel has been converted.
On
Y+ or X+ drivers on,
or TEMP0, TEMP1
measurements activated.
PENIRQ OUTPUT
The pen-interrupt output function is shown in Figure 10. While
in power-down mode with PD0 = 0, the Y– driver is on and
connects the Y-plane of the touch screen to GND. The
PENIRQ output is connected to the X+ input through two
transmission gates. When the screen is touched, the X+ input
is pulled to ground through the touch screen.
FIGURE 10. PENIRQ Functional Block Diagram.
processor. During the measurement cycle for X-, Y-, and Z-
Position, the X+ input is disconnected from the PENIRQ
internal pull-up resistor. This is done to eliminate any leak-
age current from the internal pull-up resistor through the
touch screen, thus causing no errors.
In most of the TSC2046 models, the internal pullup resistor
value is nominally 50kΩ, but this may vary between 36kΩ
and 67kΩ given process and temperature variations. In
order to assure a logic low of 0.35VDD is presented to the
PENIRQ circuitry, the total resistance between the X+ and
Y- terminals must be less than 21kΩ.
Furthermore, the PENIRQ output is disabled and low during
the measurement cycle for X-, Y-, and Z-Position. The PENIRQ
output is disabled and high during the measurement cycle for
battery monitor, auxiliary input, and chip temperature. If the
last control byte written to the TSC2046 contains PD0 = 1, the
pen-interrupt output function is disabled and is not able to
detect when the screen is touched. In order to re-enable the
pen-interrupt output function under these circumstances, a
control byte needs to be written to the TSC2046 with PD0 = 0.
If the last control byte written to the TSC2046 contains PD0
= 0, the pen-interrupt output function is enabled at the end of
the conversion. The end of the conversion occurs on the
falling edge of DCLK after bit 1 of the converted data is
The -90 version of the TSC2046 uses a nominal 90kΩ pullup
resistor, which allows the total resistance between the X+
and Y- terminals to be as high as 30kΩ. Note that the higher
pullup resistance will cause a slower response time of the
PENIRQ to a screen touch, so user software should take this
into account.
The PENIRQ output goes low due to the current path through
the touch screen to ground, which initiates an interrupt to the
CS
DCLK
1
8
1
8
1
8
1
DIN
BUSY
DOUT
S
S
Control Bits
Control Bits
11 10
9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 11. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
TSC2046
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clocked out of the TSC2046.
+VCC • 2.7V,
+VCC • IOVDD • 1.5V,
CLOAD = 50pF
It is recommended that the processor mask the interrupt
PENIRQ is associated with whenever the processor sends a
control byte to the TSC2046. This prevents false triggering
of interrupts when the PENIRQ output is disabled in the
cases discussed in this section.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
1.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIN Valid Prior to DCLK Rising 100
tDH
DIN Hold After DCLK High
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
50
16 Clocks-per-Conversion
tDO
tDV
200
200
200
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 11. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the con-
verter. This is possible, provided that each conversion com-
pletes within 1.6ms of starting. Otherwise, the signal that is
captured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the TSC2046 is fully
powered while other serial communications are taking place
during a conversion.
tTR
tCSS
tCSH
tCH
CS Falling to First DCLK Rising 100
CS Rising to DCLK Ignored
DCLK High
10
200
200
tCL
DCLK Low
tBD
DCLK Falling to BUSY Rising/Falling
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBDV
tBTR
TABLE VI. Timing Specifications, TA = –40°C to +85°C.
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tDO
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 12. Detailed Timing Diagram.
CS
Power-Down
DCLK
1
15
1
15
1
SER/
DFR
SER/
DFR
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
FIGURE 13. Maximum Conversion Rate, 15 Clocks-per-Conversion.
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Digital Timing
POWER DISSIPATION
Figures 9 and 12 and Table VI provide detailed timing for the
digital interface of the TSC2046.
There are two major power modes for the TSC2046: full-power
(PD0 = 1) and auto power-down (PD0 = 0). When operating at
full speed and 16 clocks-per-conversion (see Figure 11), the
TSC2046 spends most of the time acquiring or converting.
There is little time for auto power-down, assuming that this
mode is active. Therefore, the difference between full-power
mode and auto power-down is negligible. If the conversion rate
15 Clocks-per-Conversion
(1)
FS = Full-Scale Voltage = VREF
1LSB = VREF(1)/4096
1LSB
11...111
1000
11...110
11...101
fCLK = 16 • fSAMPLE
100
00...010
00...001
00...000
fCLK = 2MHz
Supply Current from
+VCC and IOVDD
10
TA = 25°C
0V
FS – 1LSB
+VCC = 2.7V
Input Voltage(2) (V)
IOVDD = 1.8V
1
NOTES: (1) Reference voltage at converter: +REF – (–REF), see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN), see Figure 2
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 14. Ideal Input Voltages and Output Codes.
FIGURE 15. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Maintain-
ing DCLK at the Maximum Possible Frequency.
Figure 13 provides the fastest way to clock the TSC2046.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method can be used with field pro-
grammable gate arrays (FPGAs) or application specific inte-
grated circuits (ASICs). Note that this effectively increases
the maximum conversion rate of the converter beyond the
values given in the specification tables, which assume 16
clock cycles per conversion.
is decreased by slowing the frequency of the DCLK input, the
two modes remain approximately equal. However, if the DCLK
frequency is kept at the maximum rate during a conversion but
conversions are done less often, the difference between the
two modes is dramatic.
Figure 15 shows the difference between reducing the DCLK
frequency (scaling DCLK to match the conversion rate) or
maintaining DCLK at the highest frequency and reducing the
number of conversions per second. In the latter case, the
converter spends an increasing percentage of time in power-
down mode (assuming the auto power-down mode is active).
Data Format
The TSC2046 output data is in Straight Binary format, as
shown in Figure 14. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
Another important consideration for power dissipation is the
reference mode of the converter. In the single-ended refer-
ence mode, the touch panel drivers are ON only when the
analog input voltage is being acquired (see Figure 9 and
Table I). The external device (e.g., a resistive touch screen),
therefore, is only powered during the acquisition period. In
the differential reference mode, the external device must be
powered throughout the acquisition and conversion periods
(see Figure 9). If the conversion rate is high, this could
substantially increase power dissipation.
8-Bit Conversion
The TSC2046 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. Not only does this shorten
each conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the TSC2046 is not as
critical—settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock rate
and fewer clock cycles combine to provide a 2x increase in
conversion rate.
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CS also puts the TSC2046 into power-down mode. When
CS goes high, the TSC2046 immediately goes into power-
down mode and does not complete the current conversion.
The internal reference, however, does not turn off with CS
going high. To turn the reference off, an additional write is
required before CS goes high (PD1 = 0).
power dissipation through the bypass capacitors when the
TSC2046 is in power-down mode.
A bypass capacitor is generally not needed on the VREF pin
because the internal reference is buffered by an internal op
amp. If an external reference voltage originates from an op amp,
make sure that it can drive any bypass capacitor that is used
without oscillation.
When the TSC2046 first powers up, the device draws about
20µA of current until a control byte is written to it with PD0 = 0
to put it into power-down mode. This can be avoided if the
TSC2046 is powered up with CS = 0 and DCLK = IOVDD.
The TSC2046 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the refer-
ence input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. Whereas
high-frequency noise can be filtered out, voltage variation due
to line frequency (50Hz or 60Hz) can be difficult to remove.
LAYOUT
The following layout suggestions provide the most optimum
performance from the TSC2046. Many portable applications,
however, have conflicting requirements concerning power,
cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the
internal components are very low power. This situation means
less bypassing for the converter power and less concern
regarding grounding. Still, each situation is unique and the
following suggestions should be reviewed carefully.
The GND pin must be connected to a clean ground point. In
many cases, this is the analog ground. Avoid connections
which are too near the grounding point of a microcontroller or
digital signal processor. If needed, run a ground trace directly
from the converter to the power-supply entry or battery-
connection point. The ideal layout includes an analog ground
plane dedicated to the converter and associated analog
circuitry.
For optimum performance, care should be taken with the
physical layout of the TSC2046 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
n-bitSAR converter, there are n ‘windows’ in which large
external transient voltages can easily affect the conversion
result. Such glitches can originate from switching power
supplies, nearby digital logic, and high-power devices. The
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
The error can change if the external event changes in time
with respect to the DCLK input.
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
and the touch screen. Although resistive touch screens have
fairly low resistance, the interconnection should be as short
and robust as possible. Longer connections are a source of
error, much like the on-resistance of the internal switches.
Likewise, loose connections can be a source of error when
the contact resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error
in touch screen applications (e.g., applications that require a
backlit LCD panel). This EMI noise can be coupled through
the LCD panel to the touch screen and cause “flickering” of
the converted data. Several things can be done to reduce
this error, such as using a touch screen with a bottom-side
metal layer connected to ground to shunt the majority of
noise to ground. Additionally, filtering capacitors from Y+,
Y–, X+, and X– pins to ground can also help. Caution should
be observed under these circumstances for settling time of
the touch screen, especially operating in the single-ended
mode and at high data rates.
With this in mind, power to the TSC2046 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VCC or IOVDD and the power supplies
is high. Low-leakage capacitors should be used to minimize
TSC2046
SBAS265C
17
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSC2046EIPW
TSC2046EIPWR
TSC2046EIZQCR
PREVIEW
PREVIEW
PREVIEW
TSSOP
TSSOP
PW
16
16
48
90
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PW
2000
2500
BGA MI
CROSTA
R JUNI
OR
ZQC
TSC2046IGQCR
TSC2046IPW
ACTIVE
ACTIVE
VFBGA
TSSOP
TSSOP
TSSOP
GQC
PW
48
16
16
16
2500
100
None
None
None
SNPB
Level-2A-235C-4 WKS
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
TSC2046IPWR
TSC2046IPWRG4
ACTIVE
PW
2500
PREVIEW
PW
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSC2046IRGVR
ACTIVE
ACTIVE
QFN
QFN
RGV
RGV
16
16
2500
None
CU NIPDAU Level-1-235C-UNLIM
TSC2046IRGVRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSC2046IRGVT
TSC2046IZQCR
ACTIVE
ACTIVE
QFN
RGV
ZQC
16
48
250
None
CU NIPDAU Level-1-235C-UNLIM
BGA MI
CROSTA
R JUNI
OR
2500
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
TSC2046IZQCR-90
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQC
48
2500
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPLG008D – APRIL 2000 – REVISED FEBRUARY 2002
GQC (S-PBGA-N48)
PLASTIC BALL GRID ARRAY
4,10
3,90
SQ
3,00 TYP
0,50
G
F
0,50
E
D
C
B
A
3,00 TYP
1
2
3
4
5
6
7
A1 Corner
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,08
0,35
0,25
0,15
0,25
0,05
M
4200460/E 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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