VFC320CM [BB]
Voltage-to-Frequency and Frequency-to-Voltage CONVERTER; 电压 - 频率和频率 - 电压转换器
| 型号： | VFC320CM |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Voltage-to-Frequency and Frequency-to-Voltage CONVERTER |
| 文件： | 总9页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
VFC320
Voltage-to-Frequency
and Frequency-to-Voltage
CONVERTER
FEATURES
DESCRIPTION
● HIGH LINEARITY, 12 to 14 bits
±0.005% max at 10kHz FS
±0.03% max at 100kHz FS
±0.1% typ at 1MHz FS
The VFC320 monolithic voltage-to-frequency and fre-
quency-to-voltage converter provides a simple low
cost method of converting analog signals into digital
pulses. The digital output is an open collector and the
digital pulse train repetition rate is proportional to the
amplitude of the analog input voltage. Output pulses
are compatible with TTL, and CMOS logic families.
● V/F OR F/V CONVERSION
● 6-DECADE DYNAMIC RANGE
● 20ppm/°C max GAIN DRIFT
● OUTPUT TTL/CMOS COMPATIBLE
High linearity (0.005%, max at 10kHz FS) is achieved
with relatively few external components. Two exter-
nal resistors and two external capacitors are required
to operate. Full scale frequency and input voltage are
determined by a resistor in series with –In and two
capacitors (one-shot timing and input amplifier inte-
gration). The other resistor is a non-critical open
collector pull-up (fOUT to +VCC). The VFC320 is avail-
able in three performance/temperature grades and two
package configurations. The TO-100 versions are her-
metically sealed, and specified for the –25°C to +85°C
and –55°C to +125°C ranges, and the dual-in-line
units are specified from –25°C to +85°C.
APPLICATIONS
● INEXPENSIVE A/D AND D/A CONVERTER
● DIGITAL PANEL METERS
● TWO-WIRE DIGITAL TRANSMISSION
WITH NOISE IMMUNITY
● FM MOD/DEMOD OF TRANSDUCER
SIGNALS
● PRECISION LONG TERM INTEGRATOR
● HIGH RESOLUTION OPTICAL LINK FOR
ISOLATION
● AC LINE FREQUENCY MONITOR
● MOTOR SPEED MONITOR AND CONTROL
+VCC
VOUT
fIN
–In
+In
Flip-
fOUT
Comparators
flop
–7.5V Ref
One-shot
–VCC
C1
Common
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1982 Burr-Brown Corporation
PDS-483J
Printed in U.S.A. August, 1993
SPECIFICATIONS
At TA = +25°C and ±15VDC power supply, unless otherwise noted.
VFC320BG/BM/SM
VFC320CG/CM
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
V/F CONVERTER fOUT = VIN/7.5 R1C1, Figure 4
INPUT TO OP AMP
Voltage Range(1)
Fig. 4 with e2 = 0
Fig. 4 with e1 = 0
IIN = VIN /RIN
>0
<0
+0.25
Note 2
–10
+750
V
V
µA
Current Range(1)
Bias Current
✻
✻
Inverting Input
4
10
8
30
±0.15
✻
✻
✻
✻
✻
nA
nA
mV
µV/°C
kΩ || pF
Noninverting Input
Offset Voltage(3)
Offset Voltage Drift
Differential Impedance
Common-Mode
Impedance
±5
✻
✻
300 || 5 650 || 5
✻
✻
300 || 3 500 || 3
✻
kΩ || pF
ACCURACY
Linearity Error(1) (4) (5)
Fig. 4 with e2 = 0(6)
0.01Hz ≤ fOUT ≤ 10kHz
0.1Hz ≤ fOUT ≤ 100kHz
1Hz ≤ fOUT ≤ 1MHz
±0.004
±0.008
±0.1
±0.005
±0.030
±0.0015
✻
✻
±0.002
✻
% FSR
% FSR
% FSR
Offset Error Input
Offset Voltage(3)
Offset Drift(7)
±15
✻
ppm FSR
ppm FSR/°C
% FSR
ppm FSR/°C
ppm FSR/°C
±0.5
±5
✻
✻
Gain Error(3)
±10
50
50
✻
20
20
Gain Drift(7)
Full Scale Drift
f = 10kHz
f = 10kHz
(Offset Drift and Gain Drift)(7)(8)(9)
Power Supply Sensitivity
±VCC = 14VDC to 18VDC
CLOAD ≤ 50pF
±0.015
✻
✻
% FSR%
DYNAMIC RESPONSE
Full Scale Frequency
Dynamic Range
1
MHz
Decades
6
✻
Settling Time
(V/F) to Specified Linearity
For a Full Scale Input Step
<50% Overload
Note 10
Note 10
✻
✻
Overload Recovery
OPEN COLLECTOR OUTPUT
Voltage, Logic “0”
Leakage Current, Logic “1”
Voltage, Logic “1”
I
SINK = 8mA, max
VO = 15V
0.4
1.0
✻
✻
V
µA
0.01
✻
External Pull-up Resistor
Required (See Figure 4)
For Best Linearity
VPU
✻
V
%
ns
Duty Cycle at FS
Fall Time
25
100
✻
✻
IOUT = 5mA, CLOAD = 500pF
F/V CONVERTER VOUT = 7.5 R1C1 fIN, Figure 9
INPUT TO COMPARATOR
Impedance
Logic “1”
Logic “0”
Pulse-width Range
50 || 10 150 || 10
✻
✻
✻
✻
✻
kΩ || pF
V
V
+1.0
–VCC
0.25
+VCC
–0.05
✻
✻
µs
OUTPUT FROM OP AMP
Voltage
Current
Impedance
Capacitive Load
IO = 6mA
VO = 7VDC
Closed-Loop
0 to +10
+10
✻
✻
V
mA
Ω
0.1
100
✻
✻
Without Oscillation
pF
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
±15
✻
✻
V
V
mA
±13
±20
±7.5
✻
✻
✻
✻
±6.5
TEMPERATURE RANGE
Specification
B and C Grades
S Grade
–25
–55
+85
+125
✻
°C
°C
Operating
B and C Grades
S Grade
Storage
–40
–55
–65
+85
+125
+150
✻
✻
✻
✻
°C
°C
°C
✻
Specification the same as for VFC320BG/BM/SM.
NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by RIN and full scale current range
constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between
the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity
error determines the final accuracy. (6) For e1 = 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift.
(8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature.
(10) One pulse of new frequency plus 50ns typical.
®
2
VFC320
CONNECTION DIAGRAM
Top View
TO-100
Top View
DIP
VOUT
+In
1
10
1
2
3
4
5
6
7
14
13
12
11
10
9
–In
NC
+In
+VCC
–In
2
4
9
7
VOUT
Input Amp
Input
Amp
One-
shot
NC
+VCC
Common
Switch
3
8
Common
–VCC (Case)
–VCC
One-Shot
Capacitor
Comparator
Input
One-Shot
Capacitor
Comparator
Input
NC
NC
NC
One-
shot
5
6
fOUT
NC
fOUT
8
NC = no internal connection
External connection permitted.
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
NUMBER(1)
Supply Voltage ................................................................................... ±20V
Output Sink Current at fOUT ............................................................... 50mA
Output Current at VOUT ................................................................... +20mA
Input Voltage, –Input .......................................................................... ±VCC
Input Voltage, +Input .......................................................................... ±VCC
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PRODUCT
PACKAGE
RANGE
VFC320BG
VFC320BM
VFC320SM
VFC320CG
VFC320CM
14-Pin Ceramic DIP
TO-100
TO-100
14-Pin Ceramic DIP
TO-100
163
007
007
163
007
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support
devices and/or systems.
®
3
VFC320
FREQUENCY STABILITY VS TEMPERATURE
DISCUSSION OF
SPECIFICATIONS
LINEARITY
The full scale frequency drift of the VFC320 versus tem-
perature is expressed as parts per million of full scale range
per °C. As shown in Figure 3, the drift increases above
10kHz. To determine the total accuracy drift over tempera-
ture, the drift coefficients of external components (espe-
cially R1 and C1) must be added to the drift of the VFC320.
Linearity is the maximum deviation of the actual transfer
function from a straight line drawn between the end points
(100% full scale input or frequency and 0.1% of full scale
called zero.) Linearity is the most demanding measure of
voltage-to-frequency converter performance, and is a func-
tion of the full scale frequency. Refer to Figure 1 to deter-
mine typical linearity error for your application. Once the
full scale frequency is chosen, the linearity is a function of
operating frequency as it varies between zero and full scale.
Examples for 10kHz full scale are shown in Figure 2. Best
linearity is achieved at lower gains (∆fOUT/∆VIN) with opera-
tion as close to the chosen full scale frequency as possible
1000
100
B and S Grades
The high linearity of the VFC320 makes the device an
excellent choice for use as the front end of A/D converters
with 12- to 14-bit resolution, and for highly accurate transfer
of analog data over long lines in noisy environments (2-wire
digital transmission.)
C Grade
10
1k
10k
100k
1M
Full Scale Frequency (Hz)
Figure 3. Full Scale Drift vs Full Scale Frequency.
0.10
RESPONSE
Response of the VFC320 to changes in input signal level is
specified for a full scale step, and is 50ns plus 1 pulse of the
new frequency. For a 10V input signal step with the VFC320
operating at 100kHz full scale, the settling time to within
±0.01% of full scale is 10µs.
0.01
TA = +25°C
DFS = 0.25
0.001
THEORY OF OPERATION
1k
10k
100k
1M
The VFC320 monolithic voltage-to-frequency converter pro-
vides a digital pulse train output whose repetition rate is
directly proportional to the analog input voltage. The circuit
shown in Figure 4 is composed of an input amplifier, two
comparators and a flip-flop (forming a on-shot), two switched
current sinks, and an open collector output transistor stage.
Essentially the input amplifier acts as an integrator that
produces a two-part ramp. The first part is a function of the
input voltage, and the second part is dependent on the input
voltage and current sink. When a positive input voltage is
applied at VIN, a current will flow through the input resistor,
causing the voltage at VOUT to ramp down toward zero,
according to dV/dt = VIN/R1C1. During this time the con-
stant current sink is disabled by the switch. Note, this period
is only dependent on VIN and the integrating components.
Full Scale Frequency (Hz)
Figure 1. Linearity Error vs Full Scale Frequency.
Figure
0.003
fFULL SCALE = 10kHz
0.002
0.001
0
B Grade
C Grade
–0.001
–0.002
–0.003
Typical, TA = +25°C
When the ramp reaches a voltage close to zero, comparator
A sets the flip-flop. This closes the current sink switches as
well as changing fOUT from logic 0 to logic 1. The ramp now
0
1k
2k
3k
4k
5k
6k
7k
8k
9k 10k
Operating Frequency (Hz)
begins to ramp up, and 1mA charges through C1 until VC1
=
–7.5V. Note this ramp period is dependent on the 1mA
current sink, connected to the negative input of the op amp,
as well as the input voltage. At this –7.5V threshold point
C1, comparator B resets the flip-flop, and the ramp voltage
Figure 2. Linearity Error vs Operating Frequency.
Figure
®
4
VFC320
C2
+VPULL-UP (VPU
(5V to 15V Typically)
)
+VCC
9
Integrating
Capacitor
VOUT
fIN
Input Resistor
R1
10
7
2
1
Pull-up
R2
Input
Amp
Resitor
A
IIN
e1
6
Flip-
flop
IB
Comparators
B
fOUT
–7.5V
Ref
Q1
Constant
Current Sinks
(1mA)
IA
VIN
e2
fOUT
=
7.5 R1 C1
Switch
One-shot
3
4
8
Common
C1
One-shot
Capacitor
–VCC
Pin numbers shown for “M” package (TO-100)
VIN:
For Postive Input Voltages use e1, short e2.
For Negative Input Voltages use e2, short e1.
For Differental Input Voltages use e1 and e2.
FIGURE 4. Functional Block Diagram of the VFC320.
begins to ramp down again before the input amplifier has a
chance to saturate. In effect the comparators and flip-flop
form a one-shot whose period is determined by the internal
reference and a 1mA current sink plus the external capacitor,
C1. After the one-shot resets, fOUT changes back to logic 0
and the cycle begins again.
In the time t1 + t2 the integrator capacitor C2 charges and
discharges but the net voltage change is zero.
Thus ∆Q = 0 = IIN t1 + (IIN – IA) t2
(2)
(3)
So that IIN (t1 + t2) = IA t2
VIN
1
fOUT
But since t1 + t2 =
and IIN
=
(4), (5)
(6)
R1
The transfer function for the VFC320 is derived for the
circuit shown in Figure 4. Detailed waveforms are shown in
Figure 5.
VIN
fOUT
=
IA R2 R2
1
fOUT
=
(1)
In the time t1, IB charges the one-shot capacitor C1 until its
voltage reaches –7.5V and trips comparator B.
t1 + t2
CIN 7.5
Thus t2 =
(7)
(8)
0V
IB
VIN
IB
IA
Using (7) in (6) yield fOUT
=
X
7.5 R1 C1
Since IA = IB the result is
VIN
–7.5V
fOUT
=
(9)
7.5 R1 C1
∆VOUT
Since the integrating capacitor, C2, affects both the rising
and falling segments of the ramp voltage, its tolerance and
temperature coefficient do not affect the output frequency. It
should, however, have a leakage current that is small com-
pared to IIN, since this parameter will add directly to the gain
error of the VFC. C1, which controls the one-shot period,
should be very precise since its tolerance and temperature
coefficient add directly to the errors in the transfer function.
t1
t2
FIGURE 5. Integrator and VFC Output Timing.
®
5
VFC320
The operation of the VFC320 as a highly linear frequency-
to-voltage converter, follows the same theory of operation as
the voltage-to-frequency converter. e1 and e2 are shorted and
FIN is disconnected from VOUT. FIN is then driven with a
signal which is sufficient to trigger comparator A. The one-
shot period will then be determined by C1 as before, but the
cycle repetition frequency will be dictated by the digital
input at FIN.
C2
Integrator Capacitor
14
Gain Adjustment
IIN
VIN
1
2
3
4
5
6
7
R1
R3
R4
13
NC
+15V
Input
Amp
(1)
12 +VCC
NC
R5
(1)
–VCC
11
10
9
DUTY CYCLE
–15V
Offset Adj.
The duty cycle (D) of the VFC is the ratio of the one-shot
period (t2) or pulse width, PW, to the total VFC period (t1 +
t2). For the VFC320, t2 is fixed and t1 + t2 varies as the input
voltage. Thus the duty cycle, D, is a function of the input
voltage. Of particular interest is the duty cycle at full scale
frequency, DFS, which occurs at full scale input. DFS is a user
determined parameter which affects linearity.
C1
One-shot
Capacitor
NC
NC
NC
One-
shot
+VPU
8
R2
fOUT
Pin numbers in squares
refer to DIP package.
NOTE: (1) Bypass with 0.01µF
t2
FIGURE 7. Connection Diagram for V/F Conversion,
Negative Input Voltages.
DFS
=
= PW X fFS
t1 + t2
Best linearity is achieved when DFS is 25%. By reducing
equations (7) and (9) it can be shown that
EXTERNAL COMPONENT SELECTION
In general, the design sequence consists of: (1) choosing
fMAX, (2) choosing the duty cycle at full scale (DFS = 0.25
typically), (3) determining the input resistor, R1 (Figure 4),
(4) calculating the one-shot capacitor, C1, (5) selecting the
integrator capacitor C2, and (6) selecting the output pull-up
resistor, R2.
IIN max
1mA
VIN max / R1
1mA
DFS
=
=
Thus DFS = 0.25 corresponds to IIN max = 0.25mA.
INSTALLATION AND
OPERATING INSTRUCTIONS
VOLTAGE-TO-FREQUENCY CONVERSION
Input Resistors R1 and R3
The input resistance (R1 and R3 in Figures 6 and 7) is
calculated to set the desired input current at full scale input
voltage. This is normally 0.25mA to provide a 25% duty
cycle at full scale input and output. Values other than DFS
0.25 may be used but linearity will be affected.
The VCF320 can be connected to operate as a V/F converter
that will accept either positive or negative input voltages, or
an input current. Refer to Figures 6 and 7.
=
The nominal value is R1 is
VINmax
C2
Integrator Capacitor
R1 =
Gain Adjustment
0.25mA
(10)
If gain trimming is to be done, the nominal value is reduced
by the tolerance of C1 and the desired trim range. R1 should
have a very-low temperature coefficient since its drift adds
directly to the errors in the transfer function.
IIN
VIN
1
2
3
4
5
6
7
14
R3
R1
R4
13
NC
+15V
Input
Amp
(1)
12 +VCC
NC
R5
(1)
One-Shot Capacitor, C1
–VCC
11
10
–15V
This capacitor determines the duration of the one-shot pulse.
From equation (9) the nominal value is
Offset Adj.
C1
One-shot
capacitor
9
8
NC
NC
NC
One-
shot
VIN
C1 NOM
=
+VPU
7.5 R1 fOUT
(11)
R2
fOUT
For the usual 25% duty at fMAX = VIN/R1 = 0.25mA there is
approximately 15pF of residual capacitance so that the
design value is
Pin numbers in squares
refer to DIP package.
NOTE: (1) Bypass with 0.01µF
33 x 106
FIGURE 6. Connection Diagram for V/F Conversion,
Positive Input Voltages.
C1(pF) =
– 15
fFS
(12)
®
6
VFC320
where fFS is the full scale output frequency in Hz. The
temperature drift of C1 is critical since it will add directly to
the errors of the transfer function. An NPO ceramic type is
recommended. Every effort should be made to minimize
stray capacitance associated with C1. It should be mounted
as close to the VFC320 as possible. Figure 8 shows pulse
width and full scale frequency for various values of C1 at
DFS = 25%.
OFFSET AND GAIN ADJUSTMENT PROCEDURES
To null errors to zero, follow this procedure:
1. Apply an input voltage that should produce an output
frequency of 0.001 X full scale.
2. Adjust R5 for proper output.
3. Apply the full scale input voltage.
4. Adjust R3 for proper output.
5. Repeat stems 1 through 4.
If nulling is unnecessary for the application, delete R4 and
R5, and replace R3 with a short circuit.
10,000
1000
100
106
105
104
Full Scale Frequency
POWER SUPPLY CONSIDERATIONS
The power supply rejection ratio of the VFC320 is 0.015%
of FSR/% max. To maintain ±0.015% conversion, power
supplies which are stable to within ±1% are recommended.
These supplies should be bypassed as close as possible to the
converter with 0.01µF capacitors.
Pulse Width
10
1
103
102
Internal circuitry causes some current to flow in the common
connection (pin 11 on DIP package). Current flowing into
the fOUT pin (logic sink current) will also contribute to this
current. It is advisable to separate this common lead ground
from the analog ground associated with the integrator input
to avoid errors produced by these currents flowing through
any ground return impedance.
101
102
103
104
105
Capacitance C1(pF)
FIGURE 8. Output Pulse Width (DFS = 0.25) and Full Scale
Frequency vs External One-shot Capacitance.
Integrating Capacitor, C2
DESIGN EXAMPLE
Since C2 does not occur in the V/F transfer function equation
(9), its tolerance and temperature stability are not important;
however, leakage current in C2 causes a gain error. A
ceramic type is sufficient for most applications. The value of
C2 determines the amplitude of VOUT. Input amplifier satu-
ration, noise levels for the comparators and slew rate limit-
ing of the integrator determine a range of acceptable values,
Given a full scale input of +10V, select the values of R1, R2,
R3, C1, and C2 for a 25% duty cycle at 100kHz maximum
operation into one TTL load. See Figure 6.
Selecting C1 (DFS = 0.25)
C1 = [(33 X 106)/fMAX] – 15
[(66 X 106)/fMAX] – 15
100/fFS; if fFS ≤ 100kHz
C2 (µF) = 0.001; if 100kHz < fFS ≤ 500kHz
0.0005; if fFS > 500kHz
(13)
if DFS = 0.5
= [(33 X 106)/100kHz] – 15
= 315pF
Choose a 300pF NPO ceramic capacitor with 1% to 10%
tolerance.
Output Pull Up Resistor R2
The open collector output can sink up to 8mA and still be
TTL-compatible. Select R2 according to this equation:
Selecting R1 and R3 (DRS = 0.25)
R2 min (Ω) VPULLUP/(8mA – ILOAD
)
R1 + R3 = VIN max/0.25mA
VIN max/0.5mA
if DFS = 0.5
A 10% carbon film resistor is suitable for use as R2.
= 10V/0.25mA
Trimming Components R3, R4, R5
= 40kΩ
R5 nulls the offset voltage of the input amplifier. It should
have a series resistance between 10kΩ and 100kΩ and a
temperature coefficient less than 100ppm/°C. R4 can be a
10% carbon film resistor with a value of 10MΩ.
Choose 32.4kΩ metal film resistor with 1% tolerance and
R3 = 10kΩ cermet potentiometer.
R3 nulls the gain errors of the converter and compensates for
initial tolerances of R1 and C1. Its total resistance should be
at least 20% of R1, if R1 is selected 10% low. Its temperature
coefficient should be no greater than five times that of R1 to
maintain a low drift of the R3 - R1 series combination.
Selecting C2
C2 = 102/FMAX
= 102/100kHz
= 0.001µF
Choose a 0.001µF capacitor with ±5% tolerance.
®
7
VFC320
Selecting R2
pin 10 should be biased closer to zero to insure that the input
signal at pin 10 crosses the zero threshold.
R2 = VPULLUP/(8mA – ILOAD
)
Errors are nulled using 0.001 X full scale frequency to null
offset, and full scale frequency to null the gain error. The
procedure is given on this page. Use equations from V/F
calculations to find R1, R3, R4, C1 and C2.
=5V/(8mA – 1.6mA), one TTL-load = 1.6mA
=781Ω
Choose a 750Ω 1/4-watt carbon compensation resistor with
±5% tolerance.
TYPICAL APPLICATIONS
FREQUENCY-TO-VOLTAGE CONVERSION
To operate the VFC320 as a frequency-to-voltage converter,
connect the unit as shown in Figure 9. To interface with
TTL-logic, the input should be coupled through a capacitor,
and the input to pin 10 biased near +2.5V. The converter will
detect the falling edges of the input pulse train as the voltage
at pin 10 crosses zero. Choose C3 to make t = 0.1t (see
Figure 9). For input signals with amplitudes less than 5V,
Excellent linearity, wide dynamic range, and compatible
TTL, DTL, and CMOS digital output make the VFC320
ideal for a variety of VFC applications. High accuracy
allows the VFC320 to be used where absolute or exact
readings must be made. It is also suitable for systems
requiring high resolution up to 14 bits
Figures 10-14 show typical applications of the VFC320.
R1
R3
C2
Integrator Capacitor
+15V
R4
R5
1
2
3
4
5
6
7
14
T
13
12
11
10
9
NC
VOUT
(1)
–15V
+VCC
Input
Amp
NC
+1V
0V
12kΩ
(1)
R6
–VCC
C3
One-shot
Capacitor
(t)
2.5V
fIN
C1
0.001µF
R7
2.2kΩ
NC
NC
NC
One-
shot
fOUT
8
Pin numbers in squares
refer to DIP package.
FFS = 100kHz
NOTE: (1) Bypass with 0.01µF
FIGURE 9. Connection Diagram for F/V Conversion.
+
fOUT
VIN
Counter
Sensor
INA101
VFC320
Parallel
Data
–
High Noise
Immunity
Computer
Instrumentation
Amp
Clock
FIGURE 10. Inexpensive A/D with Two-Wire Digital Transmission Over Twisted Pair.
VIN
e1
e2
fOUT
Differential
Input
BDC
Counter
VFC320
Driver/Display
Clock
FIGURE 11. Inexpensive Digital Panel Meter.
®
8
VFC320
fIN
VOUT
VFC320
F/V
Analog
Output
Digital
Output
VIN
fOUT
VFC320
V/F
BCD
Counter
INA101
Transducer
FOT
FOR
0.005% Linearity
Precision DC
levels down to
10mV full scale
Driver
Instrumentation
Amp
Clock
Display
FIGURE 12. Remote Transducer Readout via Fiber Optic Link (Analog and Digital Output).
R1
R2
R3
+15V
11kΩ
100kΩ
40.2kΩ
Gain Adjust
Integrator
Current
0.01µF
D1
IN4154
C2
+10V to –10V
Input
0.01µF
30kΩ
R4
+15V
–
fOUT
8
7
12
2kΩ
VIN
VFC320
3510B
8.66kΩ
6
1
1
10
13
e1
+
10V
20kΩ
20kΩ
Bipolar
Input
Q1
VFC320
REF101
5
11
14
7
5
C1
3270pF
2N2222
0 to
10kHz
Output
Sign Bit
Out
4
3
4.7kΩ
4.7kΩ
3300pF
–15V
+VCC
FIGURE 13. Bipolar input is accomplished by offsetting the
input to the VFC with a reference voltage.
Accurately matched resistors in the REF101
provide a stable half-scale output frequency at
zero volts input.
FIGURE 14. Absolute value circuit with the VFC320. Op
amp, D1 and Q1 (its base-emitter junction
functioning as a diode) provide full-wave
rectification of bipolar input voltages. VFC
output frequency is proportional to | e1 |. The
sign bit output provides indication of the input
polarity.
®
9
VFC320
相关型号：
©2020 ICPDF网 联系我们和版权申明