XTR111AIDRCRG4 [BB]
Precision Voltage-to-Current Converter/Transmitter; 精密电压 - 电流转换器/发送器
| 型号： | XTR111AIDRCRG4 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Precision Voltage-to-Current Converter/Transmitter |
| 文件： | 总27页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X
R
T
1
XTR111
1
1
SBOS375 − NOVEMBER 2006
Precision Voltage-to-Current
Converter/Transmitter
FD EATURES
DESCRIPTION
The XTR111 is a precision voltage-to-current converter
designed for the standard 0mA−20mA or 4mA−20mA
analog signals, and can source up to 36mA. The ratio
between input voltage and output current is set by the
single resistor RSET. The circuit can also be modified for
voltage output.
EASY-TO-DESIGN INPUT/OUTPUT RANGES:
0mA−20mA, 4mA−20mA, 5mA−25mA
AND VOLTAGE OUTPUTS
D
D
D
D
D
D
D
D
NONLINEARITY: 0.002%
LOW OFFSET DRIFT: 1µV/5C
ACCURACY: 0.015%
An external P-MOSFET transistor ensures high output
resistance and a broad compliance voltage range
extending from 2V below the supply voltage, VVSP, to
voltages well below GND.
SINGLE-SUPPLY OPERATION
WIDE SUPPLY RANGE: 7V TO 44V
OUTPUT ERROR FLAG (EF)
OUTPUT DISABLE (OD)
The adjustable 3V to 15V sub-regulator output provides
the supply voltage for additional circuitry.
ADJUSTABLE VOLTAGE REGULATOR:
3V TO 15V
The XTR111 is available in a DFN surface-mount package.
AD PPLICATIONS
UNIVERSAL VOLTAGE-CONTROLLED
CURRENT SOURCE
24V
1
9
VSP
XTR111
OD
EF
Output Disable
Output Failure
D
CURRENT OR VOLTAGE OUTPUT FOR
3-WIRE SENSOR SYSTEMS
8
REGF
REGS
I−Mirror
5
Regulator
Out
IS
2
D
PLC OUTPUT PROGRAMMABLE DRIVER
CURRENT-MODE SENSOR EXCITATION
D
4
VG
3
G
S
D
3V
IOUT
ISET
Signal
Input
Load
0mA to 20mA
4mA to 20mA
6
VIN
(
Load Ground)
GND
SET
10
7
VVIN
IOUT = 10
RSET
(R )
SET
IOUT =10• ISET
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All other trademarks are the property of their respective owners.
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ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2006, Texas Instruments Incorporated
www.ti.com
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SBOS375 − NOVEMBER 2006
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
ABSOLUTE MAXIMUM RATINGS(1)(2)
Power Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . +44V
handledwith appropriate precautions. Failure to observe
VSP
Voltage at SET(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +14V
proper handling and installation procedures can cause damage.
Voltage at IS(3, 5) . . . . . . . . . . . . . . (V
) − 5.5V to (V
) + 0.5V
) + 0.5V
) + 0.5V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
VSP
VSP
VSP
VSP
Voltage at REGS, REGF, VIN, OD, EF . . −0.5V to (V
Voltage at REGF, VG . . . . . . . . . . . . . . . . . −0.5V to (V
Current into any pin(3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
Output Short-Circuit Duration(5)
:
VG . . . . . . . . . . . . . . . . . . . . . Continuous to common and V
REGF . . . . . . . . . . . . . . . . . . . Continuous to common and V
VSP
PACKAGE/ORDERING INFORMATION(1)
VSP
PACKAGE
DESIGNATOR MARKING
PACKAGE
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C
Electrostatic Discharge Rating (HBM) . . . . . . . . . . . . . . . . . 2000V
PRODUCT PACKAGE-LEAD
XTR111 DFN-10
(1)
DRC BSV
(1)
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
PIN DESCRIPTIONS
(2)
(3)
Refer to the Package Option Addendum at the end of this
documentfor lead temperature ratings.
PIN
1
NAME
VSP
IS
FUNCTION
Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails must be current limited.
Positive Supply
2
Source Connection
Gate Drive
3
VG
(4)
(5)
The IS pin can source up to the output current-limit under normal
operatingconditions.
4
REGS
REGF
VIN
Regulator Sense
Regulator Force
Input Voltage
5
See text in Application Section regarding safe voltage ranges
and currents.
6
7
SET
EF
Transconductance Set
Error Flag (Active Low)
Output Disable (Active High)
Negative Supply
8
9
OD
10
GND
Exposed Thermal Pad must be connected
to GND
Pad
Pad
PIN CONFIGURATIONS
TOP VIEW
DFN
1
2
3
4
5
10 GND
VSP
IS
Exposed
Thermal
Die Pad
on
Underside.
(Must be
connected
to GND)
9
8
7
6
OD
EF
VG
SET
VIN
REGS
REGF
DFN−10
Pad
2
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SBOS375 − NOVEMBER 2006
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at T = +25°C, V
= +24V, R
= 2.0kΩ; REGF connected to REGS; OD = Low, External FET connected, unless otherwise noted.
A
SET
VSP
XTR111
TYP
PARAMETER
MIN
MAX
CONDITION
UNITS
TRANSMITTER
Transfer Function
I
= 10 • V
/R
OUT
VIN SET
(1)
Specified Output Current
I
Specified Performance
0.1
25
mA
mA
OUT
(2)
Derated Performance
0 to 36
42
Current Limit for Output Current
(2, 3)
6
mA
Nonlinearity, I
/I
SET
0.1 to 25mA
0.002
0.004
0.002
0.0002
0.0001
0.015
5
0.02
% of Span
% of Span
% of Span
% of Span/°C
% of Span/V
% of Span
ppm/°C
% of Span/V
GΩ
OUT
0.1 to 36mA
(1)
= 4mA
OUT
Offset Current
vs Temperature
vs Supply, V
I
I
0.02
0.001
0.005
0.1
OS
8 to 40V Supply
VSP
(2)
Span Error, I
/I
0.1mA to 25mA
(1)
OUT SET
(2)
vs Temperature
vs Supply
(1)
0.0001
> 1
(4)
Output Resistance
Output Leakage
From Drain of Q
EXT
OD = high
< 1
µA
Input Impedance (VIN)
Input Bias Current (VIN)
2.4/30
15
GΩ/pF
nA
I
B
25
(2)
Input Offset Voltage
V
OS
V
VIN
= 20mV
0.3
1.5
mV
vs Temperature
1
µV/°C
V
(5)
Input Voltage Range
V
VIN
0 to 12
2.5
(2)
Noise, Referred to Input
Dynamic Response
0.1Hz to 10Hz; I
= 4mA
µV
PP
OUT
See Dynamic Performance Section
V-Regulator Output (REGF)
(2)
Voltage Reference
R
= 5kΩ
2.85
3.0
30
3.15
V
ppm/5C
mV/V
µA
mV/mA
mV/V
mA
LOAD
(2)
vs Temperature
(2)
vs Supply
0.1
0.8
3
(2)
Bias Current into REGS
Load Regulation
0.6mA to 5mA
= 5kΩ
5
(2)
Supply Regulation
R
LOAD
0.01
Output Current
5
Short-Circuit Output Current
21
mA
DIGITAL INPUT (OD)
V
V
Low-Level Threshold
High-Level Threshold
0.6
V
V
IL
1.8
IH
Internal Pull-up Current
V
OD
< 5.5V
4
µA
DIGITAL OUTPUT (EF)
I
Leakage Current (Open Drain)
Low-Level Output Voltage
1
2
µA
V
OH
V
I
= 2.2mA
= 400mV
EF
0.8
OL
EF
I
Current to 400mV Level
V
mA
OL
POWER SUPPLY
Specified Voltage Range
Operating Voltage
+8
+40
550
V
V
+7 to +44
450
(2)
Quiescent Current
I
Q
I = 0mA
OUT
µA
TEMPERATURE RANGE
Specified Range
−40
−55
+85
°C
°C
Operating Range
+125
Package Thermal Impedance, q
DFN
JA
70
°C/W
(1)
(2)
(3)
(4)
(5)
Includes input amplifier, but excludes R
See Typical Characteristics.
tolerance.
SET
Span is the change in output current resulting from a full−scale change in input voltage.
Within compliance range limited by (+V − 2V) +V required for linear operation of Q .
EXT
VSP
DS
See Application Information, Input Voltage section.
3
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
QUIESCENT CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
700
650
600
550
500
450
400
350
300
550
530
510
490
470
450
430
410
390
370
350
−
−
−
25
75
50
0
25
50
75
100
125
5
10
15
20
25
30
35
40
45
_
Temperature ( C)
Supply Voltage (V)
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
GAIN vs FREQUENCY
140
120
100
80
40
30
20
10
0
Ω
RSET = 2k , No Bypass Cap
See Applications Information,
Dynamic Performance
Ω
Ω
RSET = 2k , RLOAD = 2k
Ω
Ω
RSET = 2k , RLOAD = 600
Ω
Ω
RSET = 2k , RLOAD = 200
60
−
−
−
−
10
20
30
40
40
20
Gain = VLOAD/VVIN
0
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
0.1Hz to 10Hz NOISE, RTI
INPUT−REFERRED NOISE SPECTRUM
OUT = 2mA
µ
µ
µ
100
10
1
IOUT = 4mA
I
100n
10n
1s/div
1
10
100
1k
10k
100k
Frequency (Hz)
4
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SBOS375 − NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
NONLINEARITY DISTRIBUTION
GAIN ERROR DISTRIBUTION
Gain Error (%)
Nonlinearity (%)
NONLINEARITY DRIFT DISTRIBUTION
−
_
_
(IOUT = 0.1mA to 25mA; T = 55 C to +125 C)
NONLINEARITY vs TEMPERATURE
0.03
0.02
0.01
0
0.1mA to 25mA
4mA to 20mA
−
−
−
0.01
0.02
0.03
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−
−
−
25
75
50
0
25
50
75
100
125
_
Temperature ( C)
_
Nonlinearity Drift (ppm/ C)
GAIN ERROR DRIFT DISTRIBUTION
−
_
_
(IOUT = 0.1mA to 25mA; T = 55 C to +125 C)
GAIN ERROR vs TEMPERATURE
0.15
0.10
0.05
0
4mA to 20mA
−
0.05
0.10
0.15
0.1mA to 25mA
−
−
−
−
−
−
−
−
−
−
−
−
1
10
9
8
7
6
5
4
3
2
0
−
−
−
25
75
50
0
25
50
75
100
125
_
_
Gain Error Drift (ppm/ C)
Temperature ( C)
5
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
TYPICAL NONLINEARITY
(2pt Calibration at 0.1mA and 25mA)
TYPICAL NONLINEARITY
(2pt Calibration at 4mA and 20mA)
0.0020
0.0015
0.0010
0.0005
0.000
0.0020
0.0015
0.0010
0.0005
0.000
−
−
−
−
0.0005
0.0010
0.0015
0.0020
−
−
−
−
0.0005
0.0010
0.0015
0.0020
0
5
10
15
20
25
4
8
12
16
20
40
40
I
OUT (mA)
I
OUT (mA)
TYPICAL NONLINEARITY
(2pt Calibration at 0.1mA and 36mA)
INPUT VOLTAGE RANGE LIMIT TO THE
POSITIVE SUPPLY vs TEMPERATURE
0.010
0.008
0.006
0.004
0.002
0.000
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
Seven Typical Units Shown
VVSP = 12V
−
0.002
0.004
0.006
0.008
0.010
−
−
−
−
0
5
10
15
20
25
30
35
−
−
−
25
75
50
0
25
50
75
100
125
I
OUT (mA)
_
Temperature ( C)
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)
vs OUTPUT CURRENT
OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)
vs TEMPERATURE
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
20mA
10mA
4mA
−
−
−
25
0
5
10
15
20
25
30
35
75
50
0
25
50
75
100
125
_
Output Current (mA)
Temperature ( C)
6
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
INPUT OFFSET VOLTAGE DISTRIBUTION
INPUT OFFSET VOLTAGE DRIFT DISTRIBUTION
−
−
−
−
−
1
5
4
3
2
0
1
2
3
4
5
6
µ
_
VOS Drift ( V/ C)
Input Offset Voltage (mV)
INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE
AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE
100
80
60
40
20
0
30
28
26
24
22
20
18
16
14
12
10
−
−
−
−
20
40
60
80
−
100
−
−
−
25
0
10
20
30
40
50
75
50
0
25
50
75
100
125
_
Supply Voltage (V)
Temperature ( C)
OUTPUT CURRENT LIMIT DISTRIBUTION
OUTPUT CURRENT LIMIT vs TEMPERATURE
50
49
48
47
46
45
44
43
42
41
40
−
−
−
25
75
50
0
25
50
75
100
125
Current Limit (mA)
_
Temperature ( C)
7
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
REGULATOR VOLTAGE DISTRIBUTION
ILOAD = 0.6mA
REGULATOR VOLTAGE DRIFT DISTRIBUTION
ILOAD = 0.6mA
0
10
20
30
40
50
60
70
80 More
_
Regulator Voltage Drift (ppm/ C)
Regulator Voltage (V)
REGULATOR INPUT BIAS CURRENT DISTRIBUTION
(Current into REGS Pin)
REGULATOR INPUT BIAS CURRENT
DRIFT DISTRIBUTION (Drift of Current into REGS Pin)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
_
VREGS Input Bias Current Drift (nA/ C)
µ
VREGS Input Bias Current ( A)
REGULATOR VOLTAGE vs SUPPLY VOLTAGE
ILOAD = 0.6mA
REGULATOR VOLTAGE vs TEMPERATURE
ILOAD = 0.6mA
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
−
−
−
25
0
5
10
15
20
25
30
35
40
45
50
75
50
0
25
50
75
100
125
_
Supply Voltage (V)
Temperature ( C)
8
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C and V
= +24V, unless otherwise noted.
A
VSP
Ω
Ω
Ω
Ω
STEP RESPONSE: VFS = 4V, RSET = 2k , RLD = 600
STEP RESPONSE: VFS = 2.5V, RSET = 1.25k , RLD = 600
(Rising Edge Depends on C
at VG Pin)
(Rising Edge Depends on CGATE at VG Pin)
GATE
Photo taken with CGATE = 130pF
Photo taken with CGATE = 130pF
5V/div
5V/div
10V/div
2V/div
µ
µ
10 s/div
10 s/div
REGULATOR LOAD TRANSIENT
(VREG Gain = 4V, VREGF = 12V, CL = 470nF,
ILOAD = 3mA 0.3mA)
REGULATOR LOAD TRANSIENT
(VREG Gain = 1V, VREGF = 3V, CL = 470nF
ILOAD = 3mA 0.3mA)
2V/div
10mV/div
1V/div
10mV/div
µ
40 s/div
µ
40 s/div
MAXIMUM REGULATOR CURRENT vs TEMPERATURE
29
27
25
23
21
19
17
15
−
−
−
25
75
50
0
25
50
75
100
125
_
Temperature ( C)
9
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The output disable (OD) provided can be used during pow-
er-on, multiplexing and other conditions where the output
should present no current. It has an internal pull-up that
causes the XTR111 to come up in output disable mode un-
less the OD pin is tied low.
APPLICATION INFORMATION
The XTR111 is a voltage-controlled current source capa-
ble of delivering currents from 0mA to 36mA. The primary
intent of the device is to source the commonly-used indus-
trial current ranges of 0mA−20mA or 4mA−20mA. The per-
formance is specified for a supply voltage of up to 40V. The
maximum supply voltage is 44V. The voltage-to-current ra-
tio is defined by an external resistor, RSET; therefore, the in-
put voltage range can be freely set in accordance with the
application requirement. The output current is cascoded
by an external P-Channel MOSFET transistor for large
voltage compliance extending below ground, and for easy
power dissipation. This arrangement ensures excellent
suppression of typical interference signals from the indus-
trial environment because of the extremely high output im-
pedance and wide voltage compliance.
The onboard voltage regulator can be adjusted between
3V to 15V and delivers up to 5mA load current. It is in-
tended to supply signal conditioning and sensor excitation
in 3-wire sensor systems. Voltages above 3V can be set
by a resistive divider.
Figure 1 shows a basic connection for the XTR111. The in-
put voltage VVIN reappears across RSET and controls 1/10
of the output current. The I-Mirror has a precise current
gain of 10. This configuration leads to the transfer function:
IOUT = 10 • (VVIN/RSET)
The output of the voltage regulator can be set over the
range of 3V to 12V by selecting R1 and R2 using the follow-
ing equation.
An error detection circuit activates a logic output (error
flag) in case the output current cannot correctly flow. It indi-
cates a wire break, high load resistor, or loss of headroom
for the current output to the positive supply.
VREGF = 3V • (R1 + R2)/R2
VVSP = 24V Supply
C1
1
9
8
VSP
OD
EF
(Pull Low for Normal Operation)
REGF
5
I−Mirror
IS
2
3
R1
Ω
5.6k
VG
REGS
S
QEXT
P−Channel
MOSFET
G
4
D
0mA or 4mA to 20mA
3V
VOUT
R2
Ω
8.2k
IOUT
5V
6
Load
VIN
Signal
(
Load Ground)
Source
(Sensor or
DAC, for
example)
GND
SET
10
7
VVIN
RSET
IOUT = 10
(R )
SET
Figure 1. Basic Connection for 0mA to 20mA Related to 0V to 5V Signal Input. The Voltage Regulator is
Set to 5V Output.
10
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REGF: The output of the regulator buffer can source up to
5mA current, but has very limited (less than 50µA) sinking
capability. The maximum short-circuit current is in the
range of 15mA to 25mA, changing over temperature.
EXPLANATION OF PIN FUNCTIONS
VIN: This input is a conventional, noninverting, high-
impedance input of the internal operational amplifier
(OPA). The internal circuitry is protected by clamp diodes
to supplies. An additional clamp connected to
approximately 18V protects internal circuitry. Place a small
resistor in series with the input to limit the current into the
protection if voltage can be present without the XTR111
being powered. Consider a resistor value equal to RSET for
bias current cancellation.
REGS: This pin is the sense input of the voltage regulator.
It is referenced to an internal 3V reference circuit. The input
bias current can be up to 2µA. Avoid capacitive loading of
REGS that may compromise the loop stability of the
voltage regulator.
VSP: The supply voltage of up to a maximum of 44V allows
operation in harsh industrial environment and provides
headroom for easy protection against over-voltage. Use a
large enough bypass capacitor (> 100nF) and eventually
a damping inductor or a small resistor (5Ω) to decouple the
XTR111 supply from the noise typically found on the 24V
supplies.
SET: The total resistance connected between this pin and
VIN reference sets the transconductance. Additional
series resistance can degrade accuracy and drift. The
voltage on this pin must not exceed 14V because this pin
is not protected to voltages above this level.
IS: This output pin is connected to the transistor source of
the external FET. The accuracy of the output current to IS
is achieved by dynamic error correction in the current
mirror. This pin should never be pulled more than 6.5V
below the positive supply. An internal clamp is provided to
protect the circuit, but it must be current-limited externally
to less than 25mA.
EF: The active low error flag (logic output) is intended for
use with an external pull-up to logic-high for reliable
operation when this output is used. However, it has a weak
internal pull-up to 5V and can be left unconnected if not
used.
OD: This control input has a 4µA internal pull-up disabling
the output. A pull-down or short to GND is required to
activate the output. Controlling OD reduces output glitches
during power-on and power-off. This logic input controls
the output. If not used, connect to GND.
VG: The gate drive for the external FET is protected
against shorts to the supply and GND. The circuit is
clamped so that it will not drive more than 18V below the
positive supply. The external FET should be protected if its
gate could be externally pulled beyond its ratings.
The regulator is not affected by OD.
11
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to IS; however, this compensation may slow the output
down.
EXTERNAL MOSFET
The XTR 111 delivers the precise output current to the IS
pin. The voltage at this pin is normally 1.4V below VVSP. It
must not fall more than 5.5V below VVSP
The drain-to-source breakdown voltage should be se-
lected high enough for the application. Surge voltage
protection might be required for negative over-voltages.
For positive over-voltages, a clamp diode to the 24V sup-
ply is recommended, protecting the FET from reversing.
.
This output requires an external transistor (QEXT) that
forms a cascode for the current output. The resistor must
be rated for the maximum possible voltage on VOUT and
must dissipate the power generated by the current and the
voltage across it.
The gate drive (VG) can drive from close to the positive
supply rail to 16V below the positive supply voltage (VVSP).
Most modern MOSFETs accept a maximum VGS of 20V. A
protection clamp is only required if a large drain gate ca-
pacitance can pulse the gate beyond the rating of the
MOSFET. Pulling the OD pin high disables the gate driver
and closes a switch connecting an internal 3kΩ resistor
from the VSP pin to the VG pin. This resistor discharges
the gate of the external FET and closes the channel; see
Figure 2.
VSP
OD
Switch
16V
Ω
3k
VG
GND
Table 1 lists some example devices in SO-compatible
packages, but other devices can be used as well. Avoid ex-
ternal capacitance from IS. This capacitance could be
compensated by adding additional capacitance from VG
Figure 2. Equivalent Circuit for Gate Drive and
Disable Switch
(1)
Table 1. P-Channel MOSFET (Examples)
MANUFACTURER
Infineon
PART NO.
BSP170P
IRFL9014
2SJ326-Z
NTF2955
TP2510
BREAKDOWN VGS
PACKAGE
SOT-223
SOT-223
Spec.
C-GATE
328pF
270pF
320pF
492pF
80pF
−60V
−60V
−60V
−60V
−100V
International Rectifier
NEC
ON Semiconductor
Supertex Inc.
SOT-223
TO-243AA
(1)
Data from published product data sheet; not ensured.
12
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SBOS375 − NOVEMBER 2006
100µs. Figure 3 shows an example of the ripple generated
from the individual current source values that average to
the specified accuracy over the full cycle.
DYNAMIC PERFORMANCE
The rise time of the output current is dominated by the gate
capacitance of the external FET.
The output glitch magnitude depends on the mismatch of
the internal current sources. It is approximately
proportional to the output current level and scales directly
with the load resistor value. It will slightly differ from part to
part.
The accuracy of the current mirror relies on the dynamic
matching of multiple individual current sources. Settling to
full resolution may require a complete cycle lasting around
External FET
No Filter
Ω
500
µ
20 s/div
Figure 3. Output Noise without Filter into 500Ω
External FET
Load Capacitor
CF
10nF
Ω
500
µ
20 s/div
Figure 4. Output with 10nF Parallel to 500Ω
External FET
Typical Filter
RF
Ω
10k
NOTE: Scale has been changed
from Figure 3 and Figure 4.
CF
10nF
Ω
500
µ
20 s/div
Figure 5. Output with Additional Filter
13
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SBOS375 − NOVEMBER 2006
Do not drive the input negative (referred to GND) more
than 300mV. Higher negative voltages turn on the internal
protection diodes. Insert a resistor in series with the input
if negative signals can occur eventually during power-on
or -off or during other transient conditions. Select a resistor
value limiting the possible current to 0.3mA. Higher
currents are non-destructive (see Absolute Maximum
Ratings), but they can produce output current glitches
unless in disable mode.
OUTPUT ERROR FLAG AND DISABLE INPUT
The XTR111 has additional internal circuitry to detect an
error in the output current. In case the controlled output
current cannot flow due to a wire break, high load
resistance or the output voltage level approaching the
positive supply, the error flag (EF), an open drain logic
output, pulls low. When used, this digital output requires
external pull-up to logic high (the internal pull-up current is
2µA).
More protection against negative input signals is provided
using a standard diode and a 2.2kΩ resistor, as shown in
Figure 6.
The output disable (OD) is a logic input with approximately
4µA of internal pull-up to 5V. The XTR111 comes up with
the output disabled until the OD pin is pulled low. Logic
high disables the output to zero output current. It can be
used for calibration, power-on and power-off glitch
reduction and for output multiplexing with other outputs
connected to the same terminal pin.
Ω
2.2k
V−Signal
VIN
1N4148
Power-on while the output is disabled (OD = high) cannot
fully suppress output glitching. While the supply voltage
passes through the range of 3V to 4V, internal circuits turn
on. Additional capacitance between pins VG and IS can
suppress the glitch. The smallest glitch energy appears
with the OD pin left open; for practical use, however, this
pin can be driven high through a 10kΩ resistor before the
24V supply is applied, if logic voltage is available earlier.
Alternatively, an open drain driver can control this pin using
the internal pull-up current. Pull-up to the internal regulator
tends to increase the energy because of the delay of the
regulator voltage increase, again depending on the supply
voltage rise time for the first few volts.
Figure 6. Enhanced Protection Against Negative
Overload of V
IN
4mA−20mA OUTPUT
The XTR111 does not provide internal circuits to generate
4mA with 0V input signal. The most common way to shift
the input signal is a two resistor network connected to a
voltage reference and the signal source, as shown in
Figure 7. This arrangement allows easy adjustment for
over-and under-range. The example assumes a 5V
reference (VREF) that equals the full-scale signal voltage
INPUT VOLTAGE
The input voltage range for a given output current span is
set by RSET according to the transfer function. Select a
precise and low drift resistor for best performance,
because resistor drift directly converts into drift of the
output current. Careful layout must also minimize any
series resistance with RSET and the VIN reference point.
and a signal span of 0V to 5V for 4mA to 20mA (IMIN to IMAX
output.
)
R1
Reference
Voltage
5V
Ω
40k
The input voltage is referred to the grounding point of RSET
.
VIN
Therefore, this point should not be distorted from other
currents. Assuming a 5V full-scale input signal for a 20mA
output current, RSET is 2.5kΩ. A resistance uncertainty of
just 2.5Ω already degrades the accuracy to below 0.1%.
1V to 5V
R2
Ω
10k
Input Voltage
0V to 5V
The linear input voltage range extends from 0V to 12V, or
2.3V below the positive supply voltage (whichever is
smaller). The lowest rated supply voltage accomodates
an input voltage range of up to 5V. Potential clipping is not
detected by an error signal; therefore, safe design guard
banding is recommended.
Figure 7. Resistive Divider for I
to I
Output
MAX
MIN
(4mA to 20mA) with 0 to V Signal Source
FS
The voltage regulator output or a more precise reference
can be used as VREF. Observe the potential drift added by
the drift of the resistors and the voltage reference.
14
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Table 2 provides example values for the regulator
adjustment resistors.
LEVEL SHIFT OF 0V INPUT AND
TRANSCONDUCTANCE TRIM
Table 2. Examples for the Resistor Values Setting
the Regulator Voltage
The XTR111 offers low offset voltage error at the input,
which normally does not require cancellation. If the signal
source cannot deliver 0V in a single-supply circuit, an
additional resistor from the SET pin to a positive reference
voltage or the regulator output (Figure 8) can shift the zero
level for the input (VIN) to a positive voltage. Therefore, the
signal source can drive this value within a positive voltage
range. The example shows a +100mV (102.04mV) offset
generated to the signal input. The larger this offset,
however, the more influence of its drift and inaccuracy is
seen in the output signal. The voltage at SET should not
be larger than 12V for linear operation
(1)
VREGF
R1
0
R2
3V
3.3V
3.3kΩ
5.6kΩ
27kΩ
33kΩ
8.2kΩ
8.6kΩ
5V
12.4V
(1)
Values have been rounded.
XTR111
I−V Amp
Transconductance (the input voltage to output current
ratio) is set by RSET. The desired resistor value may be
found by choosing a combination of two resistors.
VIN
VOLTAGE REGULATOR
SET
Ω
120k
5V
Reference
+100mV
Offset
The externally adjustable voltage regulator provides up to
5mA of current. It offers drive (REGF) and sense (REGS)
to allow external setting of the output voltage as shown in
Figure 9. The sense input (REGS) is referenced to 3.0V
representing the lowest adjustable voltage level. An
RSET
Ω
2k
external resistor divider sets VREGF
.
Figure 8. Input Voltage Level Shift for 0mA
Output Current
V
REGF = VREGS • (R1 + R2)/R2
REGF
REGF
3V
VREG
R1
5.6k
470nF
REGS
REG
Ω
REGS
470nF
R2
8.2kΩ
3V
3V
(a)
(b)
VSP
220Ω
Ω
1k
REGF
REGF
REGS
R3
Ω
1k
Ω
47k
5V
Source
VREG
R1
5.6k
470nF
Ω
REGS
3V
R2
8.2kΩ
3V
(c)
(d)
Figure 9. Basic Connections of the Voltage Regulator
15
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SBOS375 − NOVEMBER 2006
The voltage at REGF is limited by the supply voltage. If the
supply voltage drops close to the set voltage, the driver
output saturates and follows the supply with a voltage drop
of less than 1V (depending on load current and
temperature).
The REGF output cannot sink current. In case of supply
voltage loss, the output is protected against the discharge
currents from load capacitors by internal protection
diodes; the peak current should not exceed 25mA.
If the voltage regulator output is not used, connect REGF
to REGS (the 3V mode) loaded with a 2.2nF capacitor.
Alternatively, overdrive the loop pulling REGS high (see
Figure 9d).
For good stability and transient response, use a load
capacitance of 470nF or larger. The bias current into the
sense input (REGS) is typically less than 1µA. This current
should be considered when selecting high resistance
values for the voltage setting because it lowers the voltage
and produces additional temperature dependence.
APPLICATION BLOCK DIAGRAMS
1
VSP
OD
EF
9
8
Current
Mirror
5
4
REGF
REGS
5V
C2
470nF
R1
2k
IS
2
Ω
VG
3
G
S
D
R2
3k
Ω
Q1
3V
R3
Ω
2.5k
12−Bit Digital−to−Analog
Converter
6
VIN
Digital I/O
DAC7551
GND
10
SET
7
0mA to 20mA or
0V to 5V Output
SW1
CLOAD
RLOAD
RSET
Ω
2.5k
Switch for current
or voltage output
Figure 10. Current or Voltage Output (SW1) Using 0V to 5V Input from a 12-Bit Digital-to-Analog
Converter DAC7551
16
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SBOS375 − NOVEMBER 2006
1
VSP
OD
EF
9
8
Current
Mirror
5
4
REGF
REGS
5V
C2
470nF
R1
2k
IS
2
Ω
REF3040
4096mV
Voltage Reference
VG
3
G
S
D
R2
3k
Ω
Q1
3V
R3
Ω
2k
16−Bit Digital−to−Analog
Converter
6
VIN
Digital I/O
DAC8551
SET
GND
10
0mA to 20mA output
for 10mV to 4096mV input
or a code of 160b to 65536b
7
Load
CLOAD
R4
817.2k
Ω
RLOAD
RSET
NOTE: Calculate RSET for R4 Parallel to RSET
.
Ω
2k
Ω
(1.995k
)
Figure 11. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for
Zero Adjustment Range
1
VSP
OD
EF
IS
9
8
Current
Mirror
5
4
REGF
REGS
2
VG
3
G
S
D
Q1
3V
6
VIN
0V to 10V
Signal Input
GND
10
SET
7
Load
CLOAD
SW1
RLOAD
RSET
Ω
5k
Current (open) or
Voltage (close) Output
Figure 12. 0V to 10V or 0mA to 20mA Output Selected by Jumper (SW1)
17
ꢠ ꢆ ꢁ ꢡꢡꢡ
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SBOS375 − NOVEMBER 2006
1
VSP
OD
EF
IS
9
8
Current
Mirror
5
4
REGF
REGS
3V Supply
Output
2
GI
VG
3
G
S
D
Q1
2−Wire
3V
4mA to 20mA
R5
Ω
20k
6
VIN
0.4V to 2V
Input
R4
Ω
10k
GND
10
SET
7
RSET
Ω
50.251
GI
NOTE: The input voltage contains the signal offset: for example 0.4V to 2V input
signal. The input signal and supply output are referenced to GND (pin10).
Figure 13. 2-Wire 4mA to 20mA Current Loop Driver with Adjustable Voltage Regulator
1
VSP
OD
EF
9
8
Current
Mirror
5
4
REGF
REGS
3V Supply
IS
2
GI
VG
3
S
D
G
Q1
2−Wire
4mA to 20mA
Output
R4
150k
3V
Ω
R3
Ω
25k
6
VIN
0V to 2V
Input
GI
R5
SET
GND
10
Ω
10k
7
RSET
50.251
Ω
GI
NOTE: Input voltage range is set by the four external resistors. Q1 can be a FET or a PNP transistor. Internal GND reference is GI.
Figure 14. 2-Wire 4mA to 20mA Current Loop Driver for 0V to 2V Signal Input
18
ꢠ ꢆꢁ ꢡꢡꢡ
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SBOS375 − NOVEMBER 2006
(1)
R4
(a)
(b)
Ω
100
+24V
Q2
NPN
Q2
NPN
R3
R3
Ω
1k
Ω
1k
REGF
REGS
REGF
REGS
R1
Ω
10k
3V
6V
C2
470nF
C2
470nF
R2
10k
Ω
NOTE: (1) Resistor R4 can be calculated to protect Q2
from overcurrent in fault conditions.
Figure 15. Voltage Regulator Current Boost Using a Standard NPN Transistor
Component population, layout of traces, layers, and air
flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to
ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature
well below +125°C.
PACKAGE AND HEAT SINKING
The dominant portion of power dissipation for the current
output is in the external FET.
The XTR111 only generates heat from the supply voltage
with the quiescent current, the internal signal current that
is 1/10 of the output current and the current and internal
voltage drop of the regulator.
LAYOUT GUIDELINES
The exposed thermal pad on the bottom of the XTR111
package allows excellent heat dissipation of the device
into the printed circuit board (PCB).
The leadframe die pad should be soldered to a thermal pad
on the PCB. A mechanical data sheet showing an example
layout is attached at the end of this data sheet.
Refinements to this layout may be required based on
assembly process requirements. Mechanical drawings
located at the end of this data sheet list the physical
dimensions for the package and pad. The five holes in the
landing pattern are optional, and are intended for use with
thermal vias that connect the leadframe die pad to the
heatsink area on the PCB.
THERMAL PAD
The thermal pad must be connected to the same voltage
potential as the device GND pin.
Packages with an exposed thermal pad are specifically
designed to provide excellent power dissipation, but board
layout greatly influences overall heat dissipation. The
thermal resistance from junction-to-ambient (TJA) is
specified for the packages with the exposed thermal pad
soldered to a normalized PCB, as described in Technical
Brief SLMA002, PowerPAD Thermally-Enhanced
Package. See also EIA/JEDEC Specifications JESD51-0
to 7, QFN/SON PCB Attachment (SLUA271), and Quad
Flatpack No-Lead Logic Packages (SCBA017). These
documents are available for download at www.ti.com.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests. Even
with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
NOTE: All thermal models have an accuracy 20%.
19
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
XTR111AIDRCR
XTR111AIDRCRG4
XTR111AIDRCT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
10
10
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
SON
SON
DRC
DRC
DRC
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
XTR111AIDRCTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
3.3
B0 (mm)
3.3
K0 (mm)
1.1
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
XTR111AIDRCR
XTR111AIDRCT
DRC
DRC
10
10
330
12
8
8
12 PKGORN
T2TR-MS
P
180
12
3.3
3.3
1.1
12 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
XTR111AIDRCR
XTR111AIDRCT
DRC
DRC
10
10
MLA
MLA
346.0
190.0
346.0
212.7
29.0
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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相关型号：
XTR112/XTR114
XTR112. XTR114 - 4-20mA CURRENT TRANSMITTERS with Sensor Excitation and Linearization
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