BG3020-9D [BEL]
DC-DC Regulated Power Supply Module, 3 Output, 25W, Hybrid;
| 型号： | BG3020-9D |
| 厂家： | 
BEL FUSE INC. |
| 描述： | DC-DC Regulated Power Supply Module, 3 Output, 25W, Hybrid 输出元件 |
| 文件： | 总16页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Board Mountable
DC-DC Converters
G Series
25 Watt DC-DC Converters
G Series
Input voltage ranges up to 75 V DC
3 outputs 5...15 V DC
1500 V DC I/O electric strength test voltage
• Very high efficiency, typ. 87%
• Operating case temperature range –25...95°C
• Flex power (flexible load distribution on all outputs)
• Excellent dynamic response (magnetic feedback)
• Active current sharing for operation in parallel
• Outputs overload, no-load and short-circuit proof
• Serial 8 bit status communication interface
10.5
0.41"
43
1.69"
53
2.1"
• Thermal protection with pre-warning prior to shut-
down
• Very compact (chip and wire technology)
• High reliability
MTBF >700'000 h (Ground benign, 40°C)
Safety according to IEC/EN 60950, UL 1950
Summary
The G series of 25 Watt DC-DC converters represents a
versalite range of board mountable power supplies for use
in advanced electronic systems of centralized or decentral-
ized structure. Features include very high efficiency com-
bined with compact size, high reliability (MTBF), wide input
voltage ranges, transient voltage and surge protection, low
output ripple and noise and excellent dynamic response to
load and line changes.
The design is based on an advanced zero-voltage switch-
ing topology, optimised circuitry and high grade compo-
nents including the latest integration technologies.
Main application areas are telecom, avionics, industrial and
mobile applications where outstanding electrical perform-
ance and reliability are required.
Optionally the converters are available with an output volt-
age monitor with diagnostic results obtainable via an 8bit
serial interface and reset/shut-down signals for micro con-
troller applications.
Available with three outputs electrically isolated from the in-
put the converters deliver 25 Watt output power with flexible
load distribution between all outputs without provoking un-
acceptable voltage deviations.
Two different aluminium cases are available either for sim-
ple board mounting or with an additional mounting-flange.
The G series is designed as a hybrid circuit comprising pro-
prietary control ASICs and chip and wire technology.
Table of Contents
Page
Page
Summary .......................................................................... 1
Type Survey and Key Data .............................................. 2
Type Key .......................................................................... 2
Functional Description...................................................... 3
Electrical Input Data ......................................................... 4
Electrical Output Data ...................................................... 5
Auxiliary Functions ........................................................... 8
Electromagnetic Compatibility (EMC) ............................ 10
Immunity to Environmental Conditions........................... 11
Mechanical Data ............................................................ 12
Safety and Installation Instructions ................................ 12
Description of Options .................................................... 14
Edition 1/06.2002
1/16
Board Mountable
DC-DC Converters
G Series
Type Survey and Key Data
Table 1: Type survey
Output 1
Output 2
Output 3
Output
power
[A] Po nom [W]
Input voltage Effic. 2
range
Type
designation
Opt.
1
1
1
Uo1 nom Io1 nom Io1 max Uo2 nom Io2 nom Io2 max Uo3 nom Io3 nom Io3 max
[V DC]
5.05
5.05
5.05
5.05
[A]
2
[A]
5
[V DC]
12.6
12.6
15.4
15.4
[A]
0.6
0.6
0.5
0.5
[A]
2
[V DC]
[A]
[V DC]
14...36
36...75
14...36
36...75
h
typ [%]
–12.6 –0.6
–12.6 –0.6
–15.4 –0.5
–15.4 –0.5
–2
–2
25
25
25
25
87
BG 3020-9
CG 3020-9
BG 3040-9
CG 3040-9
D
B
2
5
2
86
2
5
1.6
1.6
–1.6
–1.6
87
2
5
86
1 Flexible load distribution on triple output units. Maximum current available from one output with all other outputs in no-load condition.
The total output power may not exceed the sum of the nominal output power of all outputs.
2 Efficiency at Ui nom and Io nom
.
Type Key
Type Key
B G 3 0 40 -9 D B
Input voltage range Ui
14...36 V DC ................................................B
36...75 V DC ............................................... C
Series .............................................................................. G
Number of outputs............................................................ 3
Output 1, Uo1 nom
5 V .......................................................... 0...1
other voltages ......................................... 7...8
Output 2 and 3, Uo2 nom, Uo3 nom
12 V .................................................... 20...39
15 V .................................................... 40...59
Operational ambient temperature range TA
–40…71°C (option) ..................................... -9
Options:
Output voltage monitor, reset sequencer .... D
Case with additional fixing holes.................. B
Edition 1/06.2002
2/16
Board Mountable
DC-DC Converters
G Series
Functional Description
The input voltage is fed via the Vi+ and the Vi– pins and an
input π-filter to a zero-voltage switching (ZVS) flyback con-
verter. The controlled resonant switching of the transistors
keeps the EMI noise low.
minimum load is required at any of the outputs and no out-
put voltage will drift under no-load condition.
An optional voltage monitor and signal sequencer on the
secondary side generates shut-down and reset signals dur-
ing the power-up and power-down sequence for a control-
led turn-on and turn-off of a microprocessor or another cir-
cuit. The monitor circuit checks for proper converter func-
tion and monitors all output voltages wether they remain
within an upper and lower limit.
On the secondary side, depending upon the converter type,
two or three output voltages are available, all referenced to
common ground (Go). Each output has an individual filter
for further noise reduction designed without any restriction
to the dynamic behaviour.
The control circuit on the secondary side senses the main
output voltage Uo1 and generates a control signal which is
transmitted via a pulse transformer to the primary control
circuit. The primary control circuit transforms this signal with
respect to the maximum admissible output power into a
second control signal for the switching transistors.
Any failure will be indicated by a /FAIL signal and may be
identified if necessary by an 8 bit diagnostic information.
Efficiency
Thanks to the latest integration methods, optimised zero-
voltage switching topology with synchronous rectifier on all
outputs and a unique control philosophy a very high effi-
ciency over the whole input voltage range is achieved. The
benefits are minimized heat dissipation and increased sys-
tem reliability.
The regulation for the second and third output voltages re-
lies on the close magnetic coupling of the transformer
windings and the circuit symmetry. Thanks to the unique
control philosophy of the flyback converter topology no
03005
5
6
7
8
9
Vo3–
Vo2+
Go
Case 1
Output Filter
Output Filter
0
ZVS
Flyback
Converter
Vi–
Go
4
3
Input Filter
and TVS
Vi+
Vo1+
2 × 22 nF
1000 V
2
1
TMON
17
18
Go
R
Primary
Controller
Secondary
Controller
19 T
16
i
Uo OK or CT2
12 /PDW
Uo1
Option D
/SDW
/RST
CT1
13
14
15
Uo2
Uo3
Supervisory
Circuit
10
11
1 Pin not fitted with option B
2 Uo OK without option D, CT2 if with option D
/FAIL /SRQ
Fig. 1
Block diagram
Edition 1/06.2002
3/16
Board Mountable
DC-DC Converters
G Series
Electrical Input Data
General conditions:
– TA = 25°C, unless TC is specified.
– Connector pins i (inhibit) and Vi– interconnected unless Uinh is specified.
– R input not connected.
Table 2: Input data
Input
BG
CG
Characteristics
Conditions
min
14
typ
max
36
min
36
typ
max
75
Unit
Ui
Input voltage range
TC min…TC max
V DC
Ui nom Nominal input voltage Io = 0...Io nom
24
10
2
48
25
2
Ui uv
Pi 0
Undervoltage lock-out
No-load input power
Ui nom, Io = 0
W
Ii inh
Input current when
inhibited
Uinh > 2.4 V
Ui min...Ui max
16
10
mA
1
Iinr p
Ci
Peak inrush current
Ui nom
11
9
3
2
A
Input capacitance
µF
fs
Switching frequency 2 Ui nom, Io nom
1 Source impedance according to prETS 300132-2 (Ver. 4.3).
2 The switching frequency varies with input voltage and output load (see: Typical performance curves).
Input Transient Voltage Protection
Reverse Polarity Protection at Input
A suppressor diode at the input together with the input filter
provides an effective protection against input transients
which may be caused for example by short circuits accross
the input lines where the network inductance may generate
high energy pulses.
The suppressor diode at the input also provides for reverse
polarity protection by conducting current in the reverse di-
rection, thus protecting the unit. An external fuse is required
to limit reverse current:
– for BG units a fast 3 A (F3A) fuse is required.
– for CG units a fast 1.25 A (F1.25A) fuse is required.
Table 3: Built-in transient voltage suppressor
Type
Breakdown
voltage (1 mA)
Peak power
at 1 ms
Peak pulse
current
IP [A]
Filter recommendations for compliance with
EN 55022, level B
V
BR min [V]
PP [W]
Electromagnetic emission requirements according to
EN 55022, level B can be achieved by adding an external
filter to the input of the converter. (tbd)
BG 1
CG 1
43
600
600
8.6
4.1
90
1 To achieve higher input transient ratings an additional inductor
and capacitor should be provided externally.
Inrush current
The inrush current has been kept as low as possible by
choosing a small internal input capacitance.
2 A/Div.
Steady state
input current
0
50 µs/Div.
Fig. 2
Typical inrush current at Ui nom, Po nom versus time
(BG 3040) measured according prETS 300132-2 (Ver. 4.3).
Edition 1/06.2002
4/16
Board Mountable
DC-DC Converters
G Series
Electrical Output Data
General conditions:
– TA = 25°C, unless TC is specified.
– Connector pins i (inhibit) and Vi– interconnected
– R input not connected.
Table 4a: Output data for dual output modules BG...CG 3020-7
Output
BG...CG 3020-7
Output 1
Output 2
Output 3
typ
Characteristics
Uo Output voltage
Static output voltage
Conditions
min
typ
max
5.1
min
typ
max
min
max
Unit
Ui nom, Io nom
5.0 5.05
5
12.15 12.6 12.85 –12.85 –12.6 –12.15
TC min...TC max
Ui nom
Io = 0...Io max
5.1
11.95
13.25 –13.25
–11.95
1
Io nom Output current
Io max
Ui nom
2
0.6
–0.6
A
only one output
loaded
5
2
–2
uo
Output
voltage
noise
Switching freq. Ui nom, Io nom
IEC/EN 61204 2
25
50
50
50
mV
pp
Total
100
100
BW = 20 MHz
uo d
t d
Dynamic3 Voltage limits
Ui min...Ui max
4.8
5.25
100
11.35
13.85 –13.85
–11.35
V
1
load
Io nom ↔ /
2
Io nom
Recovery time
100
100
µs
regulation
IEC/EN 61204
Uo adj Output voltage
adjustment range
Uo nom setting
via R input
60...110
60...110
60..100
% of
Uo nom
Table 4b: Output data for dual output modules BG...CG 3040-7
Output
BG...CG 3040-7
Output 1
Output 2
Output 3
typ
Characteristics
Uo Output voltage
Static output voltage
Conditions
min
typ
max
5.1
min
typ
max
min
max
Unit
V
Ui nom, Io nom
5.0 5.05
5
15.0 15.4 15.7
–15.7 –15.4 –15.0
TC min...TC max
Ui nom
Io = 0...Io max
5.1
14.6
16.2
–16.2
–14.6
1
Io nom Output current
Io max
Ui nom
2
0.5
–0.5
A
only one output
loaded
5
1.6
–1.6
uo
Output
voltage
noise
Switching freq. Ui nom, Io nom
IEC/EN 61204 2
25
50
50
50
mV
pp
Total
100
100
BW = 20 MHz
uo d
t d
Dynamic3 Voltage limits
Ui min...Ui max
4.8
5.25
100
13.8
17.0
100
–17.0
–13.8
V
1
load
Io nom ↔ /
2
Io nom
Recovery time
100
µs
regulation
IEC/EN 61204
Uo adj Output voltage
adjustment range
Uo nom setting
via R input
60...110
60...110
60..100
% of
Uo nom
1 Power difference between one auxiliary output and main output <12 W. Total output power ≤Po nom
.
2 See: Technical Information: Measuring and Testing.
3 Load current change for specific output. Other outputs loaded with Io nom
.
Output Current Limitation
Output Overvoltage Protection
The G series modules have a current limitation allowing
free choice of load distribution between all outputs, up to a
total current:
The outputs of the unit are protected against overvoltages
by a second fully independent control loop which disables
the unit. The unit tries to restart after a short time (5 ms).
The main purpose of this second control loop is to protect
against possible overvoltages which could occur due to a
failure in the normal feedback control loop. The second con-
trol loop does not protect the unit against externally applied
overvoltages.
Uo2 nom
Io1 + ––––––– • Io2 + ––––––– • Io3 ≤ Io1 max
Uo1 nom Uo1 nom
Uo3 nom
In overload all output voltages are simultaneously reduced.
Edition 1/06.2002
5/16
Board Mountable
DC-DC Converters
G Series
Output Voltage Regulation of Multi Output Modules
Under normal operating conditions the main ouput voltage
Uo1 is regulated to Uo1 nom. The regulation of the second and
third output voltages relies on the close magnetic coupling
of the transformer windings and the circuit symmetry. The
applied control philosophy to the power train necessitates
no minimum load at any of the outputs for correct operation
and no output voltage will drift under no-load condition. For
triple output units the output voltages of the two auxiliary
outputs (Uo2, Uo3) will remain within ±5% (Ui > Ui nom) if the
output power difference between one auxiliary output (Uo2,
Uo3) and the main output (Uo1) is less than 12 W.
Typical Performance Curves (measured with a BG 3040-7)
General conditions:
– TA = 25°C, unless TC is specified.
– Nominal loads (Io1 nom, Io2 nom, Io3 nom), unless otherwise specified.
– Connector pins i (inhibit) and Vi– interconnected.
– R input not connected.
– Input voltage = Ui nom unless otherwise specified.
Uox
Uox nom
1.08
Uox
Uox nom
1.08
1.06
1.04
1.02
1
1.06
1.04
1.02
1
+5%
+5%
Uo2
Uo3
+1%
+1%
Uo1
Uo1
Uo3
–1%
–1%
0.98
0.96
0.94
0.98
0.96
0.94
Uo2
–5%
–5%
Po1 [W]
25
Po2 [W]
25
0.92
0
0.92
0
5
10
15
20
5
10
15
20
Fig. 3
Fig. 4
Cross load regulation with load variation from 0...100% on
output 1. Zero load condition on output 2 and 3.
Cross load regulation with load variation from 0...100% on
output 2. Zero load condition on output 1 and 3.
η [%]
90
η [%]
90
85
89
88
87
86
80
Ui min
Ui nom
Ui max
75
70
Io nom [%]
100
65
Ui [V]
85
20
30
40
50
60
70
80
90
14 16 18 20 22 24 26 28 30 32 34 36
Fig. 6
Fig. 5
Efficiency versus load and input voltage with currents on
outputs equally rated.
Efficiency versus input voltage at Io nom
.
∆Uo [%]
0.6
∆η [%]
3
0.4
0.2
2
1
Uo2
0
–0.2
0
Uo3
–0.4
–1
–2
–3
Uo1
–0.6
–0.8
TC [°C]
–1
–60 –40 –20
TC [°C]
100
0
20
40
60
80 100
–60 –40 –20
0
20
40
60
80
Fig. 8
Output voltage deviation versus case temperature.
Fig. 7
∆ Efficiency versus case temperature at Io nom
.
Edition 1/06.2002
6/16
Board Mountable
DC-DC Converters
G Series
Io2
Io1
(1 A/Div.)
(200 mA/Div.)
Uo1
(100 mV/Div.)
Uo1
(100 mV/Div.)
Uo2
(200 mV/Div.)
Uo2
(200 mV/Div.)
Uo3
(200 mV/Div.)
Uo3
(200 mV/Div.)
(50 µs/Div.)
(50 µs/Div.)
Fig. 10
Fig. 9
Load transient response (Io2 = 50% to 100% of Io2 nom).
Load transient response (Io1 = 50% to 100% of Io1 nom).
06023
06024
Ui
Inhibit
(10 V/Div.)
(20 V/Div.)
Uo1
(1 V/Div.)
Uo1
(1 V/Div.)
Uo2
(5 V/Div.)
Uo2
(5 V/Div.)
Uo3
(5 V/Div.)
Uo3
(5 V/Div.)
(200 µs/Div.)
(200 µs/Div.)
Fig. 11
Fig. 12
Turn-on into full load.
Turn-on into full load after inhibit release.
Ui [V]
14
Power-up
13
Ui
(5 V/Div.)
Power-down
12
Uo1
(50 mV/Div.)
11
Uo2
(50 mV/Div.)
Po [%]
10 20 30 40 50 60 70 80 90 100
10
0
Fig. 13
Low line drop-out versus total load (at Uo1 1% drop).
Uo3
(50 mV/Div.)
(50 µs/Div.)
Fig. 14
Input line transient response (Ui rise from 20 to 30 V).
Edition 1/06.2002
7/16
Board Mountable
DC-DC Converters
G Series
fs [kHz]
700
Zo [dBΩ]
10
0
–10
–20
–30
600
50% Po nom
Uo2
Uo3
500
100% Po nom
Uo1
400
300
–40
f [kHz]
1000
–50
0.01
Ui [V]
14 16 18 20 22 24 26 28 30 32 34 36
0.1
1
10
100
Fig. 16
Output impedance versus frequency.
Fig. 15
Switching frequency versus input voltage and load.
Ui/Uo Attenuation [dB]
–20
–30
–40
–50
–60
–70
–80
–90
–100
f [Hz]
100000
10
100
1000
10000
Fig. 17
Audio rejection Ui to Uo1.
Auxiliary Functions
Connection in Parallel
Uo OK Output (only for units without option D)
(Current sharing T referenced to Go)
Uo OK, referenced to Go
The outputs of several units with equal nominal output
voltages can be connected in parallel. To ensure that the
output currents are approximately shared between the
units for lower stress and further improved reliability the T
pins of all converters need to be interconnected. In spite of
the T connection the load leads should have equal length
and cross section. If output voltage adjustment is requested
it is recommended to adjust the output voltages individually
to within a tolerance of 1...2% prior to paralleling or to con-
nect the R pins together. No more than 3 units should be
connected in parallel.
The Uo OK output is an open collector output without inter-
nal pull-up resistor indicating wether the main feedback
loop is in regulation or not. In overload condition the output
voltage feedback loop will go into saturation and Uo OK will
go to low state. The external pull-up resistor needs to be
connected to a supply voltage less than 5.5 V (e.g. Vo1+
output).
Table 5: Uo OK output
Feedback Loop
In regulation
Uo OK
open circuit
Note: – Parallel connection of auxiliary outputs without in-
Out of regulation
≤0.5 V at IUo OK sink ≤2.5 mA
volving their main outputs should be avoided.
– Parallel connection of units can slightly enlarge
the output voltage noise.
Important: Pull-up voltages higher than 5.5 V may
damage the unit.
– If units are connected in parallel using decoupling
diodes as e.g. for redundant systems the T pins
should not be interconnected.
Edition 1/06.2002
8/16
Board Mountable
DC-DC Converters
G Series
Temperature Monitor
R Control for Output Voltage Adjustment
R input, referenced to Go
TMON, referenced to Vi–
The TMON output warns the user of possible overheating of
the converter prior to shutting down the outputs should the
maximum operating temperature be exceeded. This feature
allows for instance a connected microprocessor system to
take measures (for example to save data or to activate a
cooling fan).
As a standard feature, the G converters offer adjustable
output voltages in the range 60% to 110% of Uo nom by us-
ing the R input. If the R pin is left open circuit the output volt-
age is set to Uo nom. The voltages at outputs 2 and 3 are al-
tered in the same ratio as the main output (Uo1). An internal
limitation will not admit to adjust the output voltages below
60% ±2% of Uo nom or above 110% ±2% of Uo nom. In spite
of this limitation the current into or out of the R pin must be
limited to ±0.5 mA in order to prevent damage of the inter-
nal circuits.
The TMON signal will become high (UTMON >2.4 V) if the in-
ternal temperature of the converter is above 110°C. The
TMON signal does not disable the converter.
The converter protects itself from overheating by shutting
down at an internal temperature of 115°C and will auto-
matically restart at an internal temperature of 110°C.
The R control pin is referenced to the secondary side of the
converter (Go). Adjustment of the output voltages is possi-
ble by means of either an external resistor or a voltage
source.
The TMON pin is connected to an internal open collector
with a pull-up current source of typ. 50 µA
a) Adjustment by means of an external resistor Rext
Table 6: Temperature monitor
Depending upon the value of the required output voltage,
the resistor shall be connected
Internal Temperature
<110°C
UTMON
either: Between the R pin and Go to achieve an output
voltage adjustment range of approximately
≤0.5 V at ITMON sink <1 mA
>2.4 V at ITMON source ≤30 µA
>110°C
Uo = 60...100% Uo nom
.
Uo
Important: An additional external pull-up resistor at
TMON needs to be connected to a supply voltage less
than 8 V and referenced to Vi–, otherwise the unit may
be damaged.
R
ext 1 ≈ ––––––––– • 4 kΩ
Uo nom – Uo
or: Between the R pin and Vo1+ to achieve an output
voltage range of approximately Uo = 100...110% Uo nom
.
Uo – 2.5 V
Inhibit Function
R'ext 2 ≈ –––––––––––––––––– • 4 kΩ
2.5 V • (Uo /Uo nom – 1)
Inhibit, referenced to Vi–
b) Adjustment by means of an external voltage Uext be-
tween the R pin and Go pins.
The outputs of the converter may be enabled or disabled by
means of a logic signal applied to the inhibit pin. If the inhibit
input is low (Uinh ≤0.8 V) the outputs are enabled. If the in-
hibit input is high (Uinh ≥2.4 V) or floating the outputs are
disabled. (Input current see table: Electrical input data.)
The control voltage range is 1.5...2.75 V and allows for
an adjustment in the range of approximately 60...110%
of Uo nom
.
2.5 V
ext ≈ –––––– • Uo
Uo nom
Table 7: Inhibit function
U
Uinh min...Uinh max
–0.3...0.8 V
2.4...8 V
Outputs
Enabled
Disabled
Vo1+
R
Rext 2
The inhibit input has an internal pull-up resistor of >50 kΩ
connected to an internal 8 V source.
Limiter
and
control
circuit
4 kΩ
+
Important:
Rext 1
Uext
– If the inhibit function is not required, the i pin must be
connected to Vi– to enable the outputs.
2.5 V
–
Go
– Voltages higher than 8 V or lower than –0.3 V at the
inhibit input may damage the unit.
Fig. 18
Output voltage control by means of R input.
Edition 1/06.2002
9/16
Board Mountable
DC-DC Converters
G Series
Electromagnetic Compatibility (EMC)
A suppressor diode together with an input filter form an effective protection against high input transient voltages which typi-
cally occur in many installations, but especially in battery driven mobile applications.
Electromagnetic Immunity
Table 8: Immunity type tests
Phenomenon
Standard 1
Class
Level
Coupling
mode 2
Value
applied
Waveform
Source
Imped.
Test
procedure
In
Per-
oper. form. 3
Electrostatic
discharge
IEC/EN
61000-4-2
2
3
2
2
contact discharge 4000 Vp
to case
1/50 ns
330 Ω
10 positive and
10 negative
discharges
yes
B 4
air discharge
to case
8000 Vp
Electromagnetic IEC/EN
field
antenna
3 V/m
AM 80%
1 kHz
26…1000 MHz
900 ±5 MHz
yes
yes
A
A
61000-4-3
Electromagnetic ENV 50204
field, pulse
50% duty cycle
200 Hz
modulated
repetition frequ.
Electrical fast
transient/burst
IEC/EN
61000-4-4
2
direct +i/–i
1000 Vp bursts of 5/50 ns 50 Ω
5 kHz rep. rate
1 min positive
1 min negative
transients per
coupling mode
yes
B
capacitive o/c
transients with
15 ms burst
duration and a
300 ms period
Surge
IEC/EN
61000-4-5
2
+i/c, –i/c
+i/–i
1000 Vp
500 Vp
tbd
1.2/50 µs
12 Ω
2 Ω
5 pos. and 5 neg.
impulses
yes
yes
B 4 5
tbd
Conducted
disturbancies
IEC/EN
61000-4-6
tbd
+i/–i
AM 80%
1 kHz
50 Ω
1 For related and previous standards see: Technical Information: Safety & EMC.
2 i = input, o = output, c = case.
3 A = Normal operation, no deviation from specifications, B = Normal operation, temporary deviation from specs possible.
4 Test in progress.
5 Additional external components required.
Electromagnetic Emission
[dBµV]
90
07003
[dB (pW)]
80
80
EN 55022 A
70
70
60
50
EN 55022 B
EN 55014
60
50
40
30
20
10
0
40
30
20
10
0
[MHz]
MHz
150
30
100
200
250
300
Fig. 19
Fig. 20
Typical disturbance voltage (quasi-peak) at the input ac-
cording to EN 55011/22, measured at Ui nom and Io nom
Output leads 0.1 m, twisted, case connected to protective
earth. (BG 3040-9)
Typical radiated electromagnetic power (peak) according
to EN 55014, measured at Ui nom, Io nom. Output leads
0.1 m, twisted. (BG 3040-9)
.
Edition 1/06.2002
10/16
Board Mountable
DC-DC Converters
G Series
Immunity to Environmental Conditions
Table 9: Mechanical stress
Test Method
Standard
Test Conditions
Status
Ca
Ea
Eb
Fc
Damp heat
steady state
IEC/DIN IEC 60068-2-3
MIL-STD-810D section 507.2 Relative humidity:
Duration:
Temperature:
40 ±2 °C
%
56 days
Unit not
operating
93 +2/-3
Shock
(half-sinusoidal)
IEC/EN/DIN EN 60068-2-27
MIL-STD-810D section 516.3 Bump duration:
Number of bumps:
Acceleration amplitude:
100 gn = 981 m/s2
6 ms
18 (3 each direction)
Unit
operating
Bump
(half-sinusoidal)
IEC/EN/DIN EN 60068-2-29
MIL-STD-810D section 516.3 Bump duration:
Number of bumps:
Acceleration amplitude:
40 gn = 392 m/s2
6 ms
6000 (1000 each direction)
Unit
operating
Vibration
(sinusoidal)
IEC/EN/DIN EN 60068-2-6
MIL-STD-810D section 514.3
Acceleration amplitude:
0.35 mm (10...60 Hz)
5 gn = 49 m/s2 (60...2000 Hz) operating
10...2000 Hz
Unit
Frequency (1 Oct/min):
Test duration:
7.5 h (2.5 h each axis)
Fda Random vibration IEC 60068-2-35
Acceleration spectral density: 0.05 gn2/Hz
Unit
wide band
Reproducibility
high
DIN 40046 part 23
Frequency band:
Acceleration magnitude:
Test duration:
20...500 Hz
4.9 gn rms
3 h (1 h each axis)
operating
Table 10: Temperature specifications, valid for an air pressure of 800...1200 hPa (800...1200 mbar)
Characteristics
-9
Unit
min
max
71 1
71 1
95
TA
Ambient temperature range, operational
Ambient temperature range, start-up
Case temperature range, operational
Case temperature range, start-up
–40
–55
–40
–55
–55
°C
TAs
TC
TCs
TS
95
Storage temperature range, not operational 2
105
±10
dTC/dt Case temperature gradient
K/min
1 The upper ambient temperature limit depends on system configuration:
– space between pcb’s in a rack
– heat dissipation of neighbouring electronic circuits
– air flow
In any case the user must assure a case temperature of the module below 95°C.
2 Storage at high temperatures may cause an acceleration of aging.
Table 11: Ambient pressure
Characteristics
min
max
Unit
ft
PA
Ambient pressure corresponding to altitude
–1000
45000
dPA/dt Maximum decompression (8000 ft to 40000 ft in 15 sec)
128000
ft/min
Table 12: MTBF and device hours
Ratings at specified
Case Temperature
Modules Ground Benign Ground Fixed Ground Fixed Ground Mobile Device Hours 1 Unit
40°C
40°C
70°C
42'000
42'000
50°C
45'000
45'000
770'000
770'000
122'000
122'000
MTBF acc. to
MIL-HDBK-217F-N2
BG 3020
BG 3040
n.a.
h
1 Statistical values, based on an average of 4300 working hours per year and in general field use, over 2 years
Edition 1/06.2002
11/16
Board Mountable
DC-DC Converters
G Series
Mechanical Data
Dimensions in mm. Tolerances ±0.3 mm unless otherwise indicated.
European
Projection
0
Pin Ø 1.05 mm
4 × M3
5
9
4
5
9
4
2.54
2.54
10
18
10
18
11
11
1
1
19
19
10.5 3.8
48.26
53
48.26
54.9
10.5 3.8
Fig. 22
Fig. 21
Standard case, weight <45 g
Case option B, weight <50 g
Safety and Installation Instructions
Installation Instruction
Cleaning Agents
Installation of the DC-DC converters must strictly follow the
national safety regulations in compliance with the enclo-
sure, mounting, creepage, clearance, casualty, markings
and segregation requirements of the end-use application.
In order to avoid possible damage, any penetration of
cleaning fluids is to be prevented, since the power supplies
are not hermetically sealed.
Standards and approvals
Connection to the system shall be made via a printed circuit
board with hole diameters of 1.4 mm ±0.1 mm for the pins.
Due to a patented design of flexible pins the units can di-
rectly be soldered into the pcb regardless of different ther-
mal expansion coefficients of the unit and the pcb. Option B
case needs to be screwed to the pcb prior to soldering.
All DC-DC converters are designed to meet UL 1950, CAN/
CSA C22.2 N0. 950-95 and IEC/EN 60950 standards.
The DC-DC converters have been evaluated for:
– Building in
– Functional insulation from input to output and input/out-
put to case
The units should be connected to a secondary circuit.
Check for hazardous voltages before altering any connec-
tions.
– The use in a pollution degree 2 environment.
– Connecting the input to a secondary circuit which is sub-
ject to a maximum transient rating of 1500 V.
Do not open the module.
Ensure that a unit failure (e.g. by an internal short-circuit)
does not result in a hazardous condition. See also: Safety
of operator accessible output circuit.
The DC-DC converters are subject to manufacturing sur-
veillance in accordance with ISO 9001 standard.
Table 13: Pin allocation
Pin No.
Pin No.
11
0
1
2
i
/SRQ 1
/PDW1
/SDW1
/RST 1
CT1 1
4
3
5
6
7
8
9
TMON
Vi+
12
3
13
Bottom view
4
Vi–
14
10
12
14
16
18
5
Vo3–
Vo2+
Go
15
11
13
15
17
19
6
16
CT2 1, Uo OK 2
Go
2
1
7
17
8
Go
18
R
9
Vo1+
/FAIL 1
19
T
Fig. 23
Pin allocation
10
0
Case 3
1 Only with option D
2 Without option D
3 Only with standard case (without option B)
Edition 1/06.2002
12/16
Board Mountable
DC-DC Converters
G Series
Isolation
Protection Degree
The electric strength test is performed as factory test in ac-
cordance with IEC/EN 60950 and UL 1950 and should not
be repeated in the field. Power-One will not honour any
guarantee claims resulting from electric strength field tests.
The protection degree of the DC-DC converters is IP 40.
Safety of operator accessible output circuit
If the output circuit of a DC-DC converter is operator acces-
sible, it shall be an SELV circuit according to IEC/EN 60950
related safety standards
Table 14: Electric strength test voltages
Characteristic
Input to Input to Output to Unit
The following table shows some possible installation con-
figurations, compliance with which causes the output circuit
of the DC-DC converter to be an SELV circuit according to
IEC/EN 60950 up to a configured output voltage of 40 V.
output
case
1.1
1.5
-
case
1.1
1.5
-
Electric strength test
voltage 1 s
1.1
kVrms
kV DC
nF
1.5
However, it is the sole responsibility of the installer to as-
sure the compliance with the relevant and applicable safety
regulations. More information is given in: Technical Infor-
mation: Safety.
Coupling capacitance
≈11
Insulation resistance
at 500 V DC
>100
-
-
MΩ
Table 15: Safety concept leading to an SELV output circuit
Conditions Front end
DC-DC converter
Result
Supply
voltage
Minimum required grade
of isolation, to be provided DC output status of the front end
by the AC-DC front end,
including mains supplied from the
Maximum Minimum required safety
Measures to achieve the
specified safety status of the
output circuit
Safety status of
the DC-DC
converter output
circuit
voltage
output circuit
battery charger
front end 1
Mains
≤250 V AC
Basic
≤60 V
Earthed SELV circuit 2
ELV circuit
Operational insulation (provi-
ded by the DC-DC converter)
SELV circuit
Input fuse 3, output suppressor Earthed SELV
diodes 4, earthed output
circuit 2 and earthed 2 or non
user accessible case 5
circuit
>60 V
Hazardous voltage
secondary circuit
Double or reinforced
≤60 V
SELV circuit
Operational insulation (provi-
ded by the DC-DC converter)
SELV circuit
>60 V
Double or reinforced insu- Input fuse 3, output suppressor
lated unearthed hazardous diodes 4 and non user
voltage secondary circuit 5 accessible case 5
1 The front end output voltage should match the specified input voltage range of the DC-DC converter.
2 The earth connection has to be provided by the installer according to the relevant safety standard, e.g. IEC/EN 60950.
3 The installer shall provide an approved fuse (type with the lowest rating suitable for the application) in a non-earthed input conductor
directly at the input of the DC-DC converter (see fig.: Schematic safety concept). For UL’s purpose, the fuse needs to be UL-listed.
4 Each suppressor diode should be dimensioned in such a way, that in the case of an insulation fault the diode is able to limit the output
voltage to SELV (<60 V) until the input fuse blows (see fig.: Schematic safety concept).
5 Has to be insulated from earth by double or reinforced insulation according to the relevant safety standard, based on the maximum
output voltage from the front end.
10004
Fuse
+
~
Mains
Suppressor
diode
AC-DC
front
DC-DC
con-
Battery
SELV
end
verter
–
~
Earth
connection
Earth
connection
Fig. 24
Schematic safety concept. Use fuse, diode and earth con-
nection as per table: Safety concept leading to an SELV
output circuit.
Edition 1/06.2002
13/16
Board Mountable
DC-DC Converters
G Series
Description of Options
D
Voltage monitor and reset sequencer including
– Generation of start-up and reset control signals
CT1, CT2 Timing control
(/PWD, /SDW, /RST, CT1, CT2)
The delays t1 and t2 can be defined by capacitors con-
nected between CT1 and CT2 to Go according to the for-
mula:
– Output voltage monitor with diagnostics
/FAIL, /SRQ)
t1 = k0 + k1 • CT1; t2 = k0 + k1 • CT2
Start-up and reset control signals
These control signals can be used in micro controller, micro
processor or sequencer applications where start-up and
shut-down sequences need to be adapted to the status of
their supply voltage. The pins allocated to this option are:
The /PDW (power down) input, e.g. the AC-fail signal of a
front-end, the /SDW (shut-down) and the /RST (reset) out-
puts, the CT1 and CT2 adjustment pins.
Table 16: Parameters for t1 and t2
Parameter
k0
min.
10
95
0
typ.
20
max.
30
Units
µs
k1
100
105
2500
µs/nF
nF
CT1; CT2
All secondary inputs and outputs are electrically isolated
from the input circuitry and referenced to Go. In applications
where this isolation is essential, opto-couplers are recom-
mended to provide the signal link between primary and sec-
ondary side.
Table 17: Timing tolerance for t3 and t4
Delay
min.
25
max.
27.5
220
Units
ms
t3
t4
200
+
/SDW (/shut down), /RST (/reset)
Open collector outputs with internal pull-up resistors of
4.7 k typ. connected to Vo1.
–
G-family
DC-DC
Converter
Front-End
AC-DC
Converter
≈
Micro-
processor
/SDW
/RST
/PDW
/PDW (/power down)
+
–
Digital input with internal pull-up resistor of 6.8 kΩ typ. con-
nected to Vo1+.
AC-Fail signal
Opto-coupler
Table 18: Input/output data of /PDW, /SDW, /RST
Fig. 25
Example of system architecture
Parameter Condition
min.
max.
48
Units
Isink /SDW
Isink /RST
U/PDW High
U/PDW Low
U/SDW <0.6 V
U/RST <0.6 V
mA
Example of a system configuration: A central AC-DC con-
verter delivers a main DC bus voltage. On local electronic
boards, decentralized DC-DC converters stabilize and con-
dition the main DC voltage to one or several specific DC
voltages.
48
0.7 • Uo1
0.3 • Uo1
If the AC mains fails and the AC-DC converter delivers an
AC fail signal, it can be used to trigger a predefined signal
sequence between the G series DC-DC converter and the
microprocessor (or other circuitry).
Important: No voltage higher than Uo1 should be applied
to /PDW, /SDW and /RST otherwise the unit may be
damaged.
Functional description
After the detection of a mains failure (/PDW) a routine to
save volatile memory can be started by /SDW after the time
t1, before the microprocessor is reset by /RST, after t2.
The /SDW and the /RST outputs are not only controlled by
the /PDW input, but also by the voltage of the main output. If
Uo1 falls below 4.58 V ±2% /SDW, /RST are immediately
taken low independently of the status of the /PDW. At start-
up the /SDW, /RST signals will only be released if Uo1 is
higher than 4.58 V ±2%.
At start-up /SDW will be released before /RST goes high (t3,
t4). Both delays, t1 and t2, can individually be adjusted by a
capacitor in the range of 20 µs to 250 ms. The delays t3 and
t4 are fixed and can not be adjusted.
In any case a /SDW will be followed by an /RST.
t1 < t/PDW < t1 + t2
t/PDW
t
/PDW < t1
Uo1 < 4.58 V
4.58 V
11024
t/PDW > t1 + t2
t/PDW
Uo1
t/PDW
/PDW
/SDW
/RST
t1
t2 t3 t4
t1
t2
t3
t4
t3
t4
Fig. 26
Timing of the control signals
Edition 1/06.2002
14/16
Board Mountable
DC-DC Converters
G Series
Output Voltage Monitor
Table 20: Bit Code of Failure Identification Register (FIR)
Option D also includes an extended monitoring and diag-
nostic circuitry which continuously monitors all output
voltages and compares them with their high and low thresh-
old values. The circuit can also be used to check the con-
verter for correct function prior to e.g. a general system
check-up in avionic applications or for identification of pos-
sible failures.
Bit State
Conditions
Limit min.
Limit max.
[% of Uo ref]
1
1
[% of Uo ref
]
Bit 0 = 0
Bit 1 = 0
Bit 2 = 0
Bit 3 = 0
Bit 4 = 0
Bit 5 = 0
Uo1 < limit
Uo1 > limit
Uo2 < limit
Uo2 > limit
Uo3 < limit
Uo3 > limit
90
105
85
110
115
90
95
110
90
115
110
85
The /FAIL output is a failure indicator which can deliver ei-
ther a boolean type or a serial type message. The type of
serial message that will be generated depends upon the
level and chronology applied to /SRQ and /FAIL. The serial
link is asynchronous, with one start bit (low level), 8 data
bits and one stop bit (high level), transmitting at 9600 bauds
±2%.
Bit 6 = 0
Bit 7 = 0
overload condition
malfunction of the converter
1 The limits won't track the output voltages if adjusted by means
of the R pin. Uo ref = 5 V resp. 12.5 V resp. 15 V.
Transmission of Failure Identification Register (FIR)
The contents of the Failure Identification Register will be
transmitted to the user whenever the /SRQ is pulsed low.
/FAIL
The /FAIL signal is an open collector input/output allowing
bidirectional communication. It has an internal pull-up resis-
tor of 4.7 kΩ typ. connected to Vo1+.
/SRQ needs to be kept low for at least T2 (see figure: Trans-
mission of FIR). After T1 /FAIL will change to high state.
When /SRQ is taken high, the transmission of the FIR starts
after T3. Its content is the one which at the time /SRQ was
taken low. The bits are coded according to table: Bit Code
of FIR. After the transmission of the FIR the circuit returns
/SRQ
The /SRQ signal is a Schmitt-Trigger input with an internal
pull-up resistor of 6.8 kΩ typ. connected to Vo1+.
Table 19: Input/output data of /FAIL and /SRQ
to idle state.
11015
Parameter Conditions
min.
max.
48
Units
mA
V
/FAIL
ST B0 B1 B2 B3 B4 B5 B6 B7
S
Isink /FAIL
U/FAIL <0.6 V
/FAIL = Input
U/FAIL High
U/FAIL Low
U/SRQ High
U/SRQ Low
0.7 • Uo1
/SRQ
T1
0.3 • Uo1
0.3 • Uo1
T1 = max 10 µs
T2 = min 20 µs
T3 = max 10 µs
0.7 • Uo1
T2
T3
Fig. 27
Transmission of FIR
Important: No voltage higher than Uo1 should be applied
to /FAIL and /SRQ otherwise the unit may be damaged.
Transmission of Self Test Results
The diagnostic circuit has the capability to perform a self
test on its own diagnostic functions in order to increase the
detected failure rate. All possible defined failures will be in-
ternally simulated. The user can check the recognition of
the failures by the setting of the bits in the serial message.
All bits should be in the high state for correct functioning of
the circuit. (See table: Bit Code of FIR.)
There are 4 possible modes for the monitoring circuit/
serial link.
– Idle state (/FAIL = static failure indicator)
– Transmission of Failure Identification Register (FIR)
– Transmission of Self Test Result
– Programming of the Failure Reporting Mask (FRM)
To enter the self test routine the user should take the /SRQ
signal low and force the /FAIL signal to low state for at least
T5. The self test result is transmitted at a time T7 after the
/SRQ was taken high.
Idle State (/SRQ high)
In the idle state the /FAIL output is a static failure indicator
with the possibility to mask reported failures. (See: Pro-
gramming of the FRM.)
forced to low by user
If one of the monitored output voltages goes outside of its
threshold values or in the case of an overload or malfunc-
tion of the converter, the corresponding bit (according to
table Bit Code of FIR) is cleared in the Failure Identification
Register (FIR). If the corresponding bit in the Failure Re-
porting Mask (FRM) is programmed for reporting, the
/FAIL output is set to low.
11016
/FAIL
/SRQ
ST B0 B1 B2 B3 B4 B5 B6 B7
S
T4 = min –10 µs 1
T5 = min 20 µs
T6 = min 10 µs
T7 = max 10 µs
T4
T7
T6
T5
All bits which are cleared in the FIR and have the corre-
sponding bit programmed in the FRM will be erased 25 ms
after the disappearance of the last failure with reporting
enabled or last continuous idle state, whichever occurs last.
This will result in /FAIL going high. The bits of the FIR whose
corresponding bits in the FRM are at a low level (no report-
ing) will remain unchanged.
1 The negative value of T4 means that /FAIL can be
forced low latest 10 µs after /SRQ was forced low.
Fig. 28
Self test
After the transmission of the self test the circuit returns into
idle state. If the self test routine detects any failure which is
programmed in the FRM for being reported then /FAIL will
remain low in idle state until the next self test routine is
started.
Edition 1/06.2002
15/16
Board Mountable
DC-DC Converters
G Series
Programming of the Failure Reporting Mask
Should some failures not need to be reported to the /FAIL
line the user can send a serial message to the converter to
program a new Failure Report Mask (FRM).
newly programmed FRM. Should the converter consider
the reception incorrect the last valid FRM remains valid and
is returned to the user when /SRQ is taken high.
To enter the programming mode the user should force
/SRQ to low state for at least T8 before sending the appro-
priate message (as e.g. according to figure: Programming
of the FRM and table Bit code for programming the FRM),
by forcing /FAIL to low whenever needed whilst /SRQ is
kept low. The parameters for the serial reception are the
same as for transmission; (Baud rate 9600), one start bit
(low level), 8 data bits, one stop bit (high level). During the
whole transmission /SRQ needs to be kept low. The new
FRM will be used when /SRQ goes high.
When the system is powered-up all bits of the FRM are high
(all failures reported).
Table 21: Bit code for programming the FRM
Bit
Failure reporting inhibited for
B0 = 0 Uo1 < low limit
B1 = 0 Uo1 > high limit
B2 = 0 Uo2 < low limit
B3 = 0 Uo2 > high limit
B4 = 0 Uo3 < low limit
B5 = 0 Uo3 > high limit
B6 = 0 overload condition
B7 = 0 malfunction of the converter
After reception the converter will automatically send the
new FRM to the /FAIL line enabling the user to check the
11017
S
/FAIL
/SRQ
ST B0 B1 B2 B3 B4 B5 B6 B7
S
ST B0 B1 B2 B3 B4 B5 B6 B7
T1
Sending FRM by user
T9
T3
Acknowledgement by converter
T8
T1 = max 10 µs
T3 = max 10 µs
T8 = min 20 µs
T9 = min 10 µs
Fig. 29
Programming of the FRM.
B
Fixing Holes
Case with fixing holes for extremely high vibration environ-
ments. (See: Mechanical Data.)
Edition 1/06.2002
16/16
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