PFE1500-12-054NA [BEL]
AC-DC FRONT-END POWER SUPPLIES;
| 型号： | PFE1500-12-054NA |
| 厂家： | 
BEL FUSE INC. |
| 描述： | AC-DC FRONT-END POWER SUPPLIES |
| 文件： | 总27页 (文件大小：2143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The PFE1500 is a 1500 W AC to DC power-factor-corrected (PFC)
power supply that converts standard AC or HVDC power into a main
output of 12 VDC for powering intermediate bus architectures (IBA) in
high performance and reliability servers, routers, and network
switches.
The PFE1500 Series meets international safety standards and displays
the CE-Mark for the European Low Voltage Directive (LVD).
High Efficiency, typ. 94% efficiency at half load
Universal input voltage range: 90-264 VAC
High voltage DC input: 180-350 VDC (Option for 400 VDC)
AC input with power factor correction
•
•
•
•
•
Always-On standby output (model dependent):
o
o
Programmable 3.3 V / 5 V (16.5 W)
12 V @ 3 A (36 W)
Hot-plug capable
•
•
•
•
•
•
Parallel operation with active digital current sharing
Digital controls for improved performance
High density design: 35 W/in3
Small form factor: 54.5(W) x 40.0(H) x 321.5(L) mm
I2C communication interface for control, programming and monitoring
with PMBus® protocol and PSMI Protocol
Over temperature, output over voltage and overcurrent protection
256 Bytes of EEPROM for user information
2 Status LEDs: OK and FAIL with fault signaling
•
•
•
High Performance Servers
Routers
Switches
•
•
•
Disclaimer: PMBus is a registered trademark of SMIF, Inc.
2
PFE1500 Series
Product Family
Power Level
Dash
V1 Output
Dash
Width
Airflow
Input 3
A: C14 Socket
AC: C16 Socket
AH: HVDC Socket
N: Normal 1
R: Reverse 2
PFE Front-Ends
1500 W
12 V
54 mm
1
“N” Normal Airflow from Output connector to Input AC socket
Ordering PN: PFE1500-12-054NA for C14 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12-054NAC for C16 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12-054NAH for both AC and HVDC (RF-203-D-1.0) input connector, input range is 180 ~ 400 VDC and 90 ~ 264 VAC
“R” Reverse Airflow from Input AC socket to Output connector
2
Ordering PN: PFE1500-12-054RA for C14 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12-054RAC for C16 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12-054RAH for both AC and HVDC (RF-203-D-1.0) input connector, input range is 180 ~ 400 VDC and 90 ~ 264 VAC
For difference of the AC socket and mechanical outline refer to section 13.
3
S412
Product Family
Power Level
Dash
V1 Output
Airflow
Input 5
VSB Output
A: C14 Socket
AC: C16 Socket
AH: HVDC Socket
PFE Front-Ends
1500 W
12 V
N: Normal 4
12VSB
4
“N” Normal Airflow from Output connector to Input AC socket
Ordering PN: PFE1500-12NAS412 for C14 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12NACS412 for C16 AC input connector, input range is 180 VDC ~ 350 VDC and 90 VAC ~ 264 VAC
Ordering PN: PFE1500-12NAHS412 for both AC and HVDC (RF-203-D-1.0) input connector, input range is 180 VDC ~ 400 VDC
and 90 VAC ~ 264 VAC
For difference of the AC socket and mechanical outline refer to section 13.
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PFE1500 Series
The PFE1500 Series AC/DC power supply is combination of analog and DSP control, highly efficient front-end power supply. It
incorporates resonance-soft-switching technology and interleaved power trains to reduce component stresses, providing increased
system reliability and very high efficiency. With a wide input operational voltage range and minimal derating of output power with
input voltage and temperature, the PFE1500 power supply maximizes power availability in demanding server, network, and other
high availability applications. The supply is fan cooled and ideally suited for integration with a matching airflow paths. The PFC stage
is an analogue solution; MCU is used to communicate with DSP chip on secondary side. The DC/DC stage uses soft switching
resonant techniques in conjunction with synchronous rectification. An active OR-ing device on the output ensures no reverse load
current and renders the supply ideally suited for operation in redundant power systems. The always-on standby output, provides
power to external power distribution and management controllers. It is protected with an active OR-ing device for maximum
reliability. Status information is provided with front-panel LEDs.
In addition, the power supply can be controlled and the fan speed set via the I2C bus. The I2C bus allows full monitoring of the
supply, including input and output voltage, current, power, and inside temperatures. The fan speed is adjusted automatically
depending on the actual power demand and supply temperature and can be overridden through the I2C bus.
Figure 1. PFE1500 Series Block Diagram
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliability, and
cause permanent damage to the supply.
Vi maxc
Maximum Input
Continuous
264
VAC
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PFE1500 Series
General Condition: TA = 0… 45°C unless otherwise specified.
100
200
90
240
3501
264
350
180
15
VAC
VDC
VAC
VDC
VAC
Arms
Ap
Vi nom
Nominal Input Voltage
Vi
Input Voltage Ranges
Normal operating (Vi min to Vi max
See Figure 7A and Figure 7B
)
180
90
Vi red
Ii max
Ii p
Derating Input Voltage Range
Max Input Current
Inrush Current Limitation
Input Frequency
Vi min to Vi max, TNTC = 25°C (Figure 4)
40
Fi
47
0.96
80
50/60
64
Hz
PF
Power Factor
Vi nom, 50 Hz, > 0.3 I1 nom
Ramping up
W/VA
VAC
VDC
VAC
VDC
84
174
80
89
180
85
Turn-on Input Voltage2
Vi on
169
75
Vi off
Turn-off Input Voltage
Ramping down
166
171
90
176
Vi nom, 0.1∙Ix nom, Vx nom, TA = 25°C
Vi nom, 0.2∙Ix nom, Vx nom, TA = 25°C
Vi nom, 0.5∙Ix nom, Vx nom, TA = 25°C
Vi nom, Ix nom, Vx nom, TA = 25°C
92
Efficiency without Fan at AC
input
94
92
η
%
Vi nom=336VDC, 0.1∙Ix nom, Vx nom, TA = 25°C
Vi nom=336VDC, 0.2∙Ix nom, Vx nom, TA = 25°C
Vi nom=336VDC, 0.5∙Ix nom, Vx nom, TA = 25°C
Vi nom=336VDC, Ix nom, Vx nom, TA = 25°C
89
92
Efficiency without Fan at DC
input
93.5
92
After last AC zero point to V1 ≥ 10.8 V, VSB within
regulation, Vi = 230 VAC, Px nom
Thold
Hold-up Time
10
ms
4.1 INPUT FUSE
Quick-acting 16 A input fuse (5 x 20 mm) in series the L line inside the power supply protect against severe defects. The fuses
are not accessible from the outside and are therefore not serviceable parts.
4.2 INRUSH CURRENT
The AC-DC power supply exhibits an X-capacitance of only 3.2 µF, resulting in a low and short peak current, when the supply
is connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current.
NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in-rush current limiting device (NTC) may
not sufficiently cool down and excessive inrush current or component failure(s) may result.
1
For PFE1500-12-054NAH, PFE1500-12-054RAH and PFE1500-12NAHS412, normal DC operation input range is 200 VDC to 380 VDC
and Input range is 180 VDC to 400 VDC; input AC range is 90 VAC ~ 264 VAC.
The Front-End is provided with a minimum hysteresis of 3 V during turn-on and turn-off within the ranges.
2
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PFE1500 Series
4.3 INPUT UNDER-VOLTAGE
If the sinusoidal input voltage stays below the input under voltage lockout threshold Vi on, the supply will be inhibited. Once the
input voltage returns within the normal operating range, the supply will return to normal operation again.
4.4 POWER FACTOR CORRECTION
Power factor correction (PFC) is achieved by controlling the input current waveform synchronously with the input voltage. An
analog controller is implemented giving outstanding PFC results over a wide input voltage and load ranges. The input current
will follow the shape of the input voltage.
4.5 EFFICIENCY
High efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft-transition
topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the losses
in the high current output path. The speed of the fan is digitally controlled to keep all components at an optimal operating
temperature regardless of the ambient temperature and load conditions.
Figure 3. Power factor vs. Load current
Figure 2. Efficiency vs. Load current (ratio metric loading)
Figure 4. Inrush current, Vin = 264 VAC, 90°, CH1: Vin (200V/div), CH2: Iin (10A/div)
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PFE1500 Series
General Condition: Ta = 0… 45°C unless otherwise specified.
Main Output V1
V1 nom Nominal Output Voltage
V1 set
12.0
VDC
% V1 nom
% V1 nom
W
0.5 ∙I1 nom, Tamb = 25 °C
Output Setpoint
Accuracy
-0.5
-2
+0.5
+2
dV1 tot
P1 nom
Total Regulation
Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max
264 VAC > Vin ≥ 180 VAC, V1 = 12 VDC
400 VDC > Vin ≥180 VDC, V1 = 12 VDC
Nominal Output Power
1500
1000
125
Refer to Figure 7 for
derating curve
180 VAC > Vin ≥ 90 VAC, V1 = 12 VDC
W
264 VAC > Vin ≥180 VAC, V1 = 12 VDC
400 VDC > Vin ≥180 VDC, V1 = 12 VDC
I1 nom
Nominal Output Current
ADC
ADC
Refer to Figure 7 for
derating curves
180 VAC > Vin ≥ 90 VAC, V1 = 12 VDC
83.4
v1 pp
Output Ripple Voltage
Load Regulation
Line Regulation
V1 nom, I1 nom, 20 MHz BW (See Section 5.1)
Vi = Vi nom, 0 - 100 % I1 nom
150
mVpp
mV
mV
A
dV1 Load
dV1 Line
dIshare
80
40
Vi =Vi min…Vi max
Current Sharing
Deviation from I1 tot / N, I1 > 10%
-3
+3
ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom
dI1/dt = 1A/μs
ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom
,
,
dVdyn
Trec
Dynamic Load Regulation
Recovery Time
-0.6
0.6
V
1
ms
dI1/dt = 1A/μs, recovery within 1% of V1 nom
tAC V1
tV1 rise
CLoad
Start-up Time from AC
Rise Time
2
sec
ms
μF
V1 = 10…90% V1 nom
0.5
10
Capacitive Loading
Ta = 25°C
30000
3.3/5 VSB Standby Output
VSB nom Nominal Output Voltage
VSB_SEL = 1
3.3
5.0
VDC
VDC
0.5 ∙ISB nom, Tamb = 25°C
VSB_SEL = 0
Output Setpoint
Accuracy
VSB set
dVSB tot
PSB nom
VSB_SEL = 0 / 1
-0.5
-3
+0.5
+3
%V1nom
%VSBnom
Total Regulation
Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max
VSB = 3.3 VDC,
16.5
16.5
5
Nominal Output Power
W
VSB = 5.0 VDC,
VSB = 3.3 VDC,
ISB nom
VSB pp
dVSB
Nominal Output Current
Output Ripple Voltage
Droop
ADC
mVpp
mV
VSB = 5.0 VDC,
3.3
VSB nom, ISB nom, 20 MHz BW (See Section 5.1)
100
VSB_SEL = 1
VSB_SEL = 0
67
44
0 - 100 % ISB nom
VSB_SEL = 1,
VSB_SEL = 0,
5.25
3.45
-3
6
4.3
3
ISB max
Current Limitation
ADC
dVSBdyn
Trec
Dynamic Load Regulation
Recovery Time
%VSBnom
μs
ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom
dIo/dt = 0.5 A/μs, recovery within 1% of V1 nom
,
250
2
tAC VSB
tVSB rise
CLoad
Start-up Time from AC
Rise Time
VSB = 90% VSB nom
VSB = 10…90% VSB nom
Tamb = 25°C
sec
0.5
30
ms
μF
Capacitive Loading
10000
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PFE1500 Series
12 VSB Standby Output
VSB nom
VSB set
dVSB tot
PSB nom
ISB nom
VSB pp
dVSB
Nominal Output Voltage
Output Setpoint Accuracy
Total Regulation
12
VDC
0.5 ∙ISB nom, Tamb = 25°C
-1
-3
+1
+3
%VSB nom
Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max
VSB = 12 VDC
%VSB nom
Nominal Output Power
Nominal Output Current
Output Ripple Voltage
Droop
36
3
W
A
VSB = 12 VDC
VSB nom, ISB nom, 20 MHz BW (See Section 5.1)
0 - 100 % ISB nom
60
270
120
mVpp
mV
V
dVSBdyn
Trec
Dynamic Load Regulation
Recovery Time
-0.6
0.6
0.5
2
ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom
dIo/dt = 1 A/μs, recovery within 1% of V1 nom
,
ms
s
tAC VSB
tVSB rise
CLoad
Start-up Time from AC
Rise Time
VSB = 90% VSB nom
VSB = 10…90% VSB nom
Tamb = 25°C
20
ms
μF
Capacitive Loading
1,500
5.1 OUTPUT VOLTAGE RIPPLE
Internal capacitance at the 12 V output (behind the OR-ing circuitry) is minimized to prevent disturbances during hot plug. In
order to provide low output ripple voltage in the application, external capacitors (a parallel combination of 10 µF tantalum
capacitor in parallel with 0.1 µF ceramic capacitors) should be added close to the power supply output.
The setup of Figure 5 has been used to evaluate suitable capacitor types. The capacitor combinations of Table 1 and Table 2
should be used to reduce the output ripple voltage. The ripple voltage is measured with 20 MHz BWL, close to the external
capacitors.
Figure 5. Output ripple test setup
NOTE: Care must be taken when using ceramic capacitors with a total capacitance of 1 µF to 50 µF on output V1, due to their
high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects.
EXTERNAL CAPACITOR V1
DV1MAX
UNIT
EXTERNAL CAPACITOR VSB
DV1MAX
UNIT
Standard test condition:
1 Pc 10 µF / 63 V Electrolytic Capacitor
1 pc 0.1 uF / 100 V ceramic capacitor
Standard test condition:
1 pc 10 µF / 63 V Electrolytic Capacitor
1 pc 0.1 uF / 100 V ceramic capacitor
150
mVpp
100
mVpp
1Pcs 1000µF/16V/Low ESR Aluminum/ø10x20
120
100
90
mVpp
mVpp
mVpp
Add 1 pc 10µF/16 V/X5R/1206
50
40
mVpp
mVpp
2Pcs 47µF/16V/X5R/1210
Add 2 pcs 10µF/1V/X5R/1206
2Pcs 47µF/16V/X5R/1210 plus
1Pcs 1000µF Low ESR AlCap
Table 2. Suitable capacitors for 3.3VSB and 5VSB
Table 1. Suitable capacitors for V1
The output ripple voltage on VSB is influenced by the main output V1. Evaluating VSB output ripple must be done when maximum
load is applied to V1.
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PFE1500 Series
PARAMETER
DESCRIPTION / CONDITION
MIN
13.3
110
NOM
MAX
UNIT
A
F
Input Fuse (L)
Not user accessible, quick-acting (F)
16
V1 OV
tOV V1
VSB OV
tOV VSB
OV Threshold V1
14.5
1
VDC
ms
OV Latch Off Time V1
OV Threshold VSB
120
% VSB
ms
OV Latch Off Time VSB
1
Vi > 180 VAC, Ta < 45°C
Vi > 90 VAC, Ta < 45°C
Ta < 45°C for 12 VSB
Ta < 45°C for 5 VSB
Ta < 45°C for 3.3 VSB
V1 < 3 V
128
93
3.3
140
110
3.6
4.5
6.2
200
IV1 lim
Over Current Limitation V1
Over Current Limitation VSB
A
IVSB lim
A
A
A
A
3.45
5.25
IV1 SC
tV1 SC
TSD
Max Short Circuit Current V1
Short Circuit Regulation Time
Over Temperature on Heat Sinks
V1 < 3 V, time until IV1 is limited to < IV1 sc
Automatic shut-down
2
ms
°C
115
120
6.1 OVERVOLTAGE PROTECTION
The PFE front-ends provide a fixed threshold overvoltage (OV) protection implemented with a HW comparator. Once an OV
condition has been triggered, the supply will shut down and latch the fault condition. The latch can be unlocked by
disconnecting the supply from the AC mains or by toggling the PSON_L input.
6.2 VSB UNDERVOLTAGE DETECTION
Both main and standby outputs are monitored.
3.3 / 5 VSB
LED and PWOK_H pin signal if the output voltage exceeds ±5% of its nominal voltage. Output under voltage protection is
provided on the standby output only. When VSB falls below 75% of its nominal voltage, the main output V1 is inhibited.
12 VSB
LED and PWOK_L pin signal if the output voltage exceeds ±7% of its nominal voltage. Output under voltage protection is
provided on both outputs. When either V1 or VSB falls below 93% of its nominal voltage, the output is inhibited.
6.3 CURRENT LIMITATION
6.3.1 MAIN OUTPUT
When main output runs in current limitation mode its output will turn OFF below 2 V but will retry to recover every 1 s interval.
If current limitation mode is still present after the unit retry, output will continuously perform this routine until current is below
the current limitation point. The supply will go through soft start every time it retries from current limitation mode.
Figure 6. Current Limitation on V1 (Vi = 230 VAC)
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PFE1500 Series
The main output current limitation will decrease if the ambient (inlet) temperature increases beyond 45°C or if the AC input
voltage below 180 VAC (see Figure 7 and Figure 8) for power supply applied in Canada and United States of America and other
district respectively).
Note that the actual over current protection on V1 will begin at a current level approximately 5 A higher, see Figure 9. (See also
Chapter 9 Temperature and Fan Control for additional information.)
Figure 7. Iout Derating Curves for application in Canada and the USA at 45°C ambient
Figure 8. Iout Derating Curves for application in districts other than Canada and the USA at 45°C ambient
Figure 9. OCP Derating Curve with Vinac and Ambient Temperature for PFE1500 Series
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PFE1500 Series
6.3.2 STANDBY OUTPUT
3.3 / 5 VSB
The standby output exhibits a substantially rectangular output characteristic down to 0 V (no hiccup mode / latch off). If it runs
in current limitation and its output voltage drops below the UV threshold, then the main output will be inhibited (standby remains
on). The current limitation of the standby output is independent of the AC input voltage.
5
4
3
2
VSB=3.3V
1
0
VSB=5V
0
2
4
6
8
Standby Output Current [A]
Figure 10. Current Limitation and Temperature Derating on 3.3 / 5 VSB
12 VSB
On the standby output, a hiccup type over current protection is implemented. This protection will shut down the standby output
immediately when standby current reaches or exceeds IVSB lim. After an off-time of 1 s the output automatically tries to restart. If
the overload condition is removed the output voltage will reach again its nominal value. At continuous overload condition the
output will repeatedly trying to restart with 1s intervals. A failure on the Standby output will shut down both Main and Standby
outputs.
12
10
8
6
4
2
0
0
1
2
3
4
5
Standby Output Current [A]
Figure 11. Current Limitation on 12 VSB
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PFE1500 Series
PARAMETER
Vi mon
DESCRIPTION / CONDITION
MIN
-2.5
-5
NOM
MAX
+2.5
+5
UNIT
Input RMS Voltage
Input RMS Current
True Input Power
V1 Voltage
V
i min ≤ Vi ≤ Vi max
%
%
%
%
%
A
Ii mon
Ii > 2 Arms
Ii > 2 Arms
Pi mon
-5
+5
V1 mon
-2
+2
I1 > 25 A
-2
+2
I1 mon
V1 Current
I1 ≤ 25 A
-1
+1
Po > 120 W
Po ≤ 120 W
-5
+5
%
W
Po nom
Total Output Power
-12
+12
3.3 / 5 VSB Models
12 VSB Models
3.3 / 5 VSB Models
12 VSB Models
-0.2
-0.5
-0.5
-0.5
+0.2
+0.5
+0.5
+0.5
VSB mon
ISB mon
Standby Voltage
Standby Current
V
A
ISB ≤ ISB nom
8.1 ELECTRICAL CHARACTERISTICS
PARAMETER
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
PSKILL_H / PSON_L / VSB_SEL / HOTSTANDBYEN_H Inputs
VIL
Input Low Level Voltage
-0.2
2.4
0
0.8
3.5
1
V
V
VIH
Input High Level Voltage
IIL, H
Maximum Input Sink or Source Current
Internal Pull Up Resistor on PSKILL_H
Internal Pull Up Resistor on PSON_L
Internal Pull Up Resistor on VSB_SEL
Internal Pull Up Resistor on HOTSTANDBYEN_H
Resistance Pin to SGND for Low Level
Resistance Pin to SGND for High Level
mA
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
RpuPSKILL_H
RpuPSON_L
RpuVSB_SEL
RpuHOTSTANDBYEN_H
RLOW
100
10
10
10
0
1
RHIGH
50
PWOK_H Output
VOL
Output Low Level Voltage
Isink < 4 mA
Isource < 0.5 mA
0
0.4
3.5
V
V
VOH
Output High Level Voltage
2.6
kΩ
RpuPWOK_H
ACOK_H Output
VOL
Internal Pull Up Resistor on PWOK_H
1
Output Low Level Voltage
Isink < 2 mA
0
0.4
3.5
V
V
VOH
Output High Level Voltage
Isource < 50 µA
2.6
kΩ
RpuACOK_H
Internal Pull Up Resistor on ACOK_H
10
SMB_ALERT_L Output
Vext
VOL
IOH
Maximum External Pull Up Voltage
12
0.4
10
V
V
Output Low Level Voltage
Isource < 4 mA
0
Maximum High Level Leakage Current
µA
Internal Pull Up Resistor on
SMB_ALERT_L
kΩ
RpuSMB_ALERT_L
None
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PFE1500 Series
8.2 INTERFACING WITH SIGNALS
All signal pins have protection diodes implemented to protect internal circuits. When the power supply is not powered, the
protection devices start clamping at signal pin voltages exceeding ±0.5 V. Therefore, all input signals should be driven only by
an open collector/drain to prevent back feeding inputs when the power supply is switched off. If interconnecting of signal pins
of several power supplies is required, then this should be done by decoupling with small signal schottky diodes as shown in
examples in (Figure 12) except for SMB_ALERT_L, ISHARE and I2C pins. SMB_ALERT_L pins can be interconnected without
decoupling diodes, since these pins have no internal pull up resistor and use a 15 V zener diode as protection device against
positive voltage on pins. ISHARE pins must be interconnected without any additional components. This in-/output is
disconnected from internal circuits when the power supply is switched off.
PSU 1 PDU
PSU 1 PDU
3.3V
3.3V
PWOK
VSB_SEL
PSU 2
PSU 2
3.3V
3.3V
PWOK
VSB_SEL
Figure 12. Interconnection of Signal Pins
8.3 FRONT LEDS
There will be 2 separate LED indicators, one green and one amber to indicate the power supply status. There will be a (slow)
blinking green POWER LED (OK) to indicate that AC is applied to the PSU and the Standby Voltage is available. This same LED
shall go steady to indicate that all the Power Outputs are available. This same LED or separate one will blink (slow) or be solid
ON amber to indicate that the power supply has failed or reached a warning status and therefore a replacement of the unit
is/maybe necessary. The LED are visible on the power supply’s exterior face. The LED location meets ESD Requirements.
POWER SUPPLY CONDITION
GREEN (OK) LED STATUS
AMBER (FAIL) LED STATUS
No AC power to all power supplies
OFF
OFF
Power Supply Failure (includes over voltage, over current, over
temperature and fan failure)
Power Supply Warning events where the power supply continues to
operate (high temperature, high power and slow fan)
OFF
OFF
ON
Blinking
AC Present/ 12VSB on (PSU OFF)
Blinking
ON
OFF
OFF
Power Supply ON and OK
Table 3. LED Status
8.4 PRESENT_L
This signaling pin is recessed within the connector and will contact only once all other connector contacts are closed. This
active-low pin is used to indicate to a power distribution unit controller that a supply is plugged in. The maximum current on
PRESENT_L pin should not exceed 10 mA.
PFE
PDU
V1
VSB
0V
PRESENT_L
Figure 13. PRESENT_L signal pin
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PFE1500 Series
8.5 PSKILL_H INPUT
The PSKILL_H input is active-high and is located on a recessed pin on the connector and is used to disconnect the main output
as soon as the power supply is being plugged out. This pin should be connected to SGND in the power distribution unit. The
standby output will remain on regardless of the PSKILL_H input state.
8.6 AC TURN-ON / DROP-OUTS / ACOK_H
The power supply will automatically turn-on when connected to the AC line under the condition that the PSON_L signal is
pulled low and the AC line is within range. The ACOK_H signal is active-high. The timing diagram is shown in Figure 14 and
referenced in Table 4.
OPERATING CONDITION
MIN MAX UNIT
tAC VSB
AC Line to 90% VVSB
2
2
sec
sec
ms
ms
ms
ms
ms
ms
ms
ms
sec
sec
tAC V1
AC Line to 90% V1
AC
Input
tACOK_H on1
tACOK_H on2
tACOK_H off
tVSB V1 del
tV1 holdup
tVSB holdup
tACOK_H V1
tACOK_H VSB
tV1 off
ACOK_H signal on delay (start-up)
ACOK_H signal on delay (dips)
ACOK_H signal off delay
VSB to V1 delay
2000
100
5
VSB
tV1 rise
10
10
20
7
500
tVSB rise
tAC VSB
Effective V1 holdup time
Effective VSB holdup time
ACOK_H to V1 holdup
ACOK_H to VSB holdup
Minimum V1 off time
V1
tVSB V1 del
tAC V1
PSON_L
ACOK_H
PWOK_H
15
1
tACOK_H on1
2
2
tPWOK_H del
tVSB off
Minimum VSB off time
1
NOTE: AC short dips means below 10 ms;
AC long dips means 10 ms to 100 ms
Figure 14. AC turn-on timing
Table 4. AC Turn-on / Dip Timing
AC
Input
tVSB holdup
tVSB off
VSB
tV1 holdup
tV1 off
V1
tACOK_H V1
tACOK_H off
PSON_L
ACOK_H
PWOK_H
tACOK_H VSB
tPWOK_H warn
Figure 15. AC short dips
Figure 16. AC long dips
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8.7 PSON_L INPUT
The PSON_L is an internally pulled-up (3.3 V) input signal to enable/disable the main output V1 of the front-end. This active-low
pin is also used to clear any latched fault condition. The timing diagram is given in Figure 27 and the parameters in Table 5.
OPERATING CONDITION
MIN
2
MAX
20
UNIT
ms
tPSON_L V1on
tPSON_L V1off
tPSON_L H min
PSON_L to V1 delay (on)
PSON_L to V1 delay (off)
2
20
ms
PSON_L minimum High time
10
ms
Table 5. PSON_L timing
8.8 PWOK_H SIGNAL
The PWOK_H is an open drain output with an internal pull-up to 3.3 V indicating whether both VSB and V1 outputs are within
regulation. This pin is active-low. The timing diagram is shown in Figure 17 and referenced in the Table 6.
OPERATING CONDITION
MIN MAX UNIT
AC
Input
tPWOK_H del
PWOK_H to V1 delay (on)
100 500 ms
PWOK_H to V1 delay (off) caused by:
PSKILL_H
0
1
ms
ms
VSB
PSON_L, OT, Fan Failure
ACOK_H (time change with loading
condition)
0.5
2.5
0.5 100 ms
*
tPWOK_H warn
tV1 rise
tPSON_L V1off
tPSON_L V1on
V1
UV and OV on VSB
1
-11
-1
30
0
ms
ms
ms
ms
OC on V1 (Software trigger)
OC on V1 (Hardware trigger)
OV on V1
tPSON_L H min
PSON_L
ACOK_H
PWOK_H
0
-3
0
tPWOK_H
del
tPWOK_H warn
A positive value means a warning time, a negative value a delay
*
(after fact).
Table 6. PWOK_H timing
Figure 17. PSON_L and PWOK_H turn-on/off timing
8.9 CURRENT SHARE
The PFE front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be
interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will disconnect
its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases.
The current share function uses a digital bi-directional data exchange on a recessive bus configuration to transmit and receive
current share information. The controller implements a Master/Slave current share function. The power supply providing the
largest current among the group is automatically the Master. The other supplies will operate as Slaves and increase their output
current to a value close to the Master by slightly increasing their output voltage. The voltage increase is limited to +250 mV.
The standby output uses a passive current share method (droop output voltage characteristic).
8.10
SENSE INPUTS
Both main and standby outputs have sense lines implemented to compensate for voltage drop on load wires (no sense lines
for 12VSB). The maximum allowed voltage drop is 200 mV on the positive rail and 100 mV on the PGND rail.
With open sense inputs the main output voltage will rise by 270 mV and the standby output by 50 mV. Therefore, if not used,
these inputs should be connected to the power output and PGND close to the power supply connector. The sense inputs are
protected against short circuit. In this case the power supply will shut down.
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PFE1500 Series
8.11
HOT-STANDBY OPERATION
The hot-standby operation is an operating mode allowing to further increase efficiency at light load conditions in a redundant
power supply system. Under specific conditions one of the power supplies is allowed to disable its DC/DC stage. This will save
the power losses associated with this power supply and at the same time the other power supply will operate in a load range
having a better efficiency. In order to enable the hot standby operation, the HOTSTANDBYEN_H and the ISHARE pins need to
be interconnected. A power supply will only be allowed to enter the hot-standby mode, when the HOTSTANDBYEN_H pin is
high, the load current is low (see Figure 18) and the supply was allowed to enter the hot-standby mode by the system controller
via the appropriate I2C command (by default disabled). The system controller needs to ensure that only one of the power
supplies is allowed to enter the hot-standby mode.
If a power supply is in a fault condition, it will pull low its active-high HOTSTANDBYEN_H pin which indicates to the other
power supply that it is not allowed to enter the hot-standby mode or that it needs to return to normal operation should it already
have been in the hot-standby mode.
NOTE: The system controller needs to ensure that only one of the power supplies is allowed to enter the hot-standby model.
Figure 19 shows the achievable power loss savings when using the hot-standby mode operation. A total power loss reduction
of 5 W is achievable.
Figure 18. Hot-standby enable/disable current thresholds
Figure 19. PSU power losses with/without hot-standby mode
PSU 1
VSB
PSU 2
3 x 3k3
VSB
CS
CS
HOTSTANDBYEN
PRESENT_L
HOTSTANDBYEN
PRESENT_L
Figure 20. Recommended hot-standby configuration
In order to prevent voltage dips when the active power supply is unplugged while the other is in hot-standby mode, it is strongly
recommended to add the external circuit as shown in Figure 20. If the PRESENT_L pin status needs also to be read by the
system controller, it is recommended to exchange the bipolar transistors with small signal MOS transistors or with digital
transistors.
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PFE1500 Series
8.12
I2C / SMBUS COMMUNICATION
The interface driver in the PFE supply is referenced to the V1 Return. The PFE supply is a communication Slave device only; it
never initiates messages on the I2C/SMBus by itself. The communication bus voltage and timing is defined in Table 7 further
characterized through:
3.3/5V
•
•
•
•
•
There are no internal pull-up resistors
The SDA/SCL IOs are 3.3/5 V tolerant
Full SMBus clock speed of 100 kbps
Clock stretching limited to 1 ms
SCL low time-out of >25 ms with recovery
within 10 ms
RX
TX
Rpull-up
SDA/SCL
•
Recognizes any time Start/Stop bus conditions
Figure 21. Physical layer of communication interface
The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate.
This is a logical OR of the Shutdown and Warning events. The power supply responds to a read command on the general
SMB_ALERT_L call address 25(0x19) by sending its status register.
Communication to the DSP or the EEPROM will be possible as long as the input AC voltage is provided. If no AC is present,
communication to the unit is possible as long as it is connected to a life V1 output (provided e.g. by the redundant unit). If only
VSB is provided, communication is not possible.
PARAMETER
DESCRIPTION / CONDITION
Input low voltage
MIN
-0.5
NOM
MAX
1.0
UNIT
V
ViL
ViH
Input high voltage
2.3
5.5
V
Vhys
VoL
Input hysteresis
0.15
V
Output low voltage
3 mA sink current
0
0.4
V
tr
Rise time for SDA and SCL
Output fall time ViHmin ViLmax
Input current SCL/SDA
20+0.1Cb3
20+0.1Cb3
-10
300
Ns
Ns
μA
pF
kHz
Ω
tof
10 pF < Cb3 < 400 pF
0.1 VDD < Vi < 0.9 VDD
250
Ii
10
50
Ci
Internal Capacitance for each SCL/SDA
SCL clock frequency
fSCL
Rpu
0
100
External pull-up resistor
Hold time (repeated) START
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START
Data hold time
f
f
f
f
f
f
f
f
f
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
SCL ≤ 100 kHz
1000 ns / Cb
μs
μs
μs
μs
μs
ns
μs
ms
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
4.0
4.7
4.0
4.7
0
3.45
Data setup time
250
4.0
5
Setup time for STOP condition
Bus free time between STOP and START
Table 7. I2C / SMBus Specification
3
Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF
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PFE1500 Series
tof
tLOW
tHIGH
tLOW
tr
SCL
tSUSTA
tHDSTA
tHDDAT tSUDAT
tSUSTO
tBUF
SDA
Figure 22. I2C / SMBus Timing
8.13
ADDRESS / PROTOCOL SELECTION (APS)
The APS pin provides the possibility to select the address by connecting a resistor to V1 return (0 V). A fixed addressing offset
exists between the Controller and the EEPROM.
NOTE:
- If the APS pin is left open, the supply will operate with the PMBus® protocol at controller / EEPROM addresses 0xB6 / 0xA6.
- The APS pin is only read at start-up of the power supply. Therefore, it is not possible to change address dynamically.
I2C Address 5
3.3V
12k
RAPS (Ω) 4
Protocol
Controller
EEPROM
0xA0
820
2700
5600
0xB0
0xB2
0xB4
0xB6
0xB0
0xB2
0xB4
0xB6
0xA2
0xA4
APS
PMBus®
ADC
8200
0xA6
0xA0
RAPS
15000
27000
56000
180000
0xA2
0xA4
PSMI
0xA6
Figure 23. I2C address and protocol setting
8.14
CONTROLER AND EEPROM ACCESS
The controller and the EEPROM in the power supply share the same I2C bus physical layer (see Figure 24). An I2C driver device
assures logic level shifting (3.3/5 V) and a glitch-free clock stretching. The driver also pulls the SDA/SCL line to nearly 0 V when
driven low by the DSP or the EEPROM providing maximum flexibility when additional external bus repeaters are needed. Such
repeaters usually encode the low state with different voltage levels depending on the transmission direction.
The DSP will automatically set the I2C address of the EEPROM with the necessary offset when its own address is changed /
set. In order to write to the EEPROM, first the write protection needs to be disabled by sending the appropriate command to
the DSP. By default, the write protection is on.
The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply.
Address & Protocol Selection
APS
SDAi
SDA
DSP
SCLi
SCL
WP
EEPROM
Protection
Addr
Figure 24. I2C Bus to DPS and EEPROM
4
E12 resistor values, use max 5% resistors, see also Figure 22
The LSB of the address byte is the R/W bit
5
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PFE1500 Series
8.15
EEPROM PROTOCOL
The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read
commands are defined, it is recommended to use the single byte write / read commands.
WRITE
The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte
with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus
should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.
S
Address
W
A
Data Address
A
Data
A
P
READ
The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data
address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the
data byte at the specified location.
S
Address
W
A
Data Address
A
S
Address
R
A
Data
nA
P
8.16
PMBus® PROTOCOL
The Power Management Bus (PMBus®) is an open standard protocol that defines means of communicating with power
conversion and other devices. For more information, please see the System Management Interface Forum web site at
www.powerSIG.org.
PMBus® command codes are not register addresses. They describe a specific command to be executed.
The PFE1500 supply supports the following basic command structures:
•
•
•
Clock stretching limited to 1 ms
SCL low time-out of >25 ms with recovery within 10 ms
Recognized any time Start/Stop bus conditions
WRITE
The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte
or after the first data byte (Byte command) or then after sending 2 data bytes (Word command).
S
Address
W
A
Command
A
Data Low Byte1)
A
Data High Byte1)
A
P
1) Optional
In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual
for further information.
S
Address
W
A
Command
A
Byte Count
A
Byte 1
A
Byte N
A
P
READ
The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word.
S
Address
W
A
Command
A
Byte Count
A
Byte 1
A
Byte N
A
P
In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual
BCA.00006 for further information.
S
Address
W
A
Command
A
S
Address
R
A
Byte Count
A
Byte 1
A
Byte N
nA P
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PFE1500 Series
8.17
PSMI PROTOCOL
New power management features in computer systems require the system to communicate with the power supply to access
current, voltage, fan speed, and temperature information. Current measurements provide data to the system for determining
potential system configuration limitations and provide actual system power consumption for facility planning. Temperature and
fan monitoring allow the system to better manage fan speeds and temperatures for optimizing system acoustics. Voltage
monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. The Power Supply
Management Interface (PSMI) supports diagnostic capabilities and allows managing of redundant power supplies. The
communication method is SMBus. The current design guideline is version 2.12.
The communication protocol is register based and defines a read and write communication protocol to read / write to a single
register address. All registers are accessed via the same basic command given below. No PEC (Packet Error Code) is used.
WRITE
The write protocol used is the SMBus 2.0 Write Word protocol. All writes are 16-bit words; byte reads are not supported nor
allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming
Manual for further information.
S
Address
W
A
Register ID
A
Data Low Byte
A
Data High Byte
A
P
READ
The read protocol used is the SMBus 2.0 Read Word protocol. All reads are 16-bit words; byte reads are not supported nor
allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming
Manual for further information.
S
Address
W
A
Register ID
A
S
Address
R
A
Data Low Byte
A
Data High Byte nA P
8.18
GRAPHICAL USER INTERFACE
Bel Power Solutions provides with its “Bel Power Solutions I2C Utility” a Windows® XP/Vista/Win7 compatible graphical user
interface allowing the programming and monitoring of the PFE1500-12-054 Front-End. The utility can be downloaded on:
belfuse.com/power-solutions and supports PMBus® protocols.
The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation
tree. In the monitoring view the power supply can be controlled and monitored.
If the GUI is used in conjunction with the SNP-OP-BOARD-01 or YTM.G1Q01.0 Evaluation Kit it is also possible to control
the PSON_L pin(s) of the power supply.
Further there is a button to disable the internal fan for approximately 10 seconds. This allows the user to take input power
measurements without fan consumptions to check efficiency compliance to the Climate Saver Computing Platinum
specification.
The monitoring screen also allows to enable the hot-standby mode on the power supply. The mode status is monitored and
by changing the load current it can be monitored when the power supply is being disabled for further energy savings. This
obviously requires 2 power supplies being operated as a redundant system (as in the evaluation kit).
NOTE: The user of the GUI needs to ensure that only one of the power supplies have the hot-standby mode enabled.
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PFE1500 Series
Figure 25. Monitoring dialog of the I2C Utility
To achieve best cooling results sufficient airflow through the supply must be ensured. Do not block or obstruct the airflow at the rear
of the supply by placing large objects directly at the output connector. The PFE1500-12-054NA, PFE1500-12-054NAC and
PFE1500-12-054NAH are provided with normal airflow, which means the air enters through the DC-output of the supply and leaves
at the AC-inlet. PFE supplies have been designed for horizontal operation.
The fan inside of the supply is controlled by a microprocessor. The RPM of the fan is adjusted to ensure optimal supply cooling and
is a function of output power and the inlet temperature.
For the normal airflow version additional constraints apply because of the AC-connector. In a normal airflow unit, the hot air is exiting
the power supply unit at the AC-inlet.
The IEC connector on the unit is rated 105°C. If 70°C mating connector is used then end user must derated the input power to meet
a maximum 70°C temperature at the front, see Figure 7 in above section.
NOTE: It is the responsibility of the user to check the front temperature in such cases. The unit is not limiting its power automatically
to meet such a temperature limitation.
Normal Airflow
Reverse Airflow
Normal Airflow
Reverse Airflow
Figure 26. Airflow direction
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21
PFE1500 Series
Figure 27. Fan speed vs. main output load
10.1
IMMUNITY
NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003.
IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point
ESD Contact Discharge
ESD Air Discharge
A
A
A
(metallic case, LEDs, connector body)
IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point
(non-metallic user accessible surfaces)
IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation,
1 µs Pulse Modulation, 10 kHz…2 GHz
IEC / EN 61000-4-4, level 3
Radiated Electromagnetic Field
Burst
AC port ±2 kV, 1 minute
A
DC port ±1 kV, 1 minute
IEC / EN 61000-4-5
Surge
Line to earth: level 3, ±2 kV
Line to line: level 2, ±1 kV
A
A
RF Conducted Immunity
IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz
IEC/EN 61000-4-11
1: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 10 ms
2: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 20 ms
3: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration >20 ms
A
VSB: A, V1: B
B
Voltage Dips and Interruptions
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PFE1500 Series
10.2
EMISSION
EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG,
single unit
EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG,
2 units in rack system
EN55022 / CISPR 22: 30 MHz … 1 GHz, QP,
single unit
EN55022 / CISPR 22: 30 MHz … 1 GHz, QP,
2 units in rack system
Class A
Class A
Class A
Class A
Conducted Emission
Radiated Emission
Harmonic Emissions
AC Flicker
IEC61000-3-2, Vin = 115 VAC / 60 Hz, & Vin = 230VAC/ 50 Hz, 100% Load
Class A
Pass
IEC61000-3-3, Vin = 230 VAC / 60 Hz, 100% Load
Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output electric
strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims resulting from electric
strength field tests.
PARAMETER
Agency Approvals
DESCRIPTION / CONDITION
MIN
NOM
MAX
UNIT
UL 60950-1 Second Edition
CAN/CSA-C22.2 No. 60950-1-07 Second Edition
IEC 60950-1:2005
Approved by
independent body
(see CE Declaration)
EN 60950-1:2006
Input (L/N) to case (PE)
Input (L/N) to output
Output to case (PE)
Basic
Isolation Strength
Reinforced
Functional
Primary (L/N) to protective earth (PE)
Primary to secondary
Input to case
According to
safety standard
dC
Creepage / Clearance
Electrical Strength Test
mm
According to
safety standard
Input to output
kVAC
Output and Signals to case
PARAMETER
DESCRIPTION / CONDITION
Vi min to Vi max, I1 nom, ISB nom below 5000 feet Altitude
Vi min to Vi max, I1 nom, ISB nom below 10,000 feet Altitude
Derating output
MIN
NOM
MAX
+45
UNIT
°C
TA
Ambient Temperature
0
0
+40
°C
TAext
TS
Extended Temp. Range
Storage Temperature
Altitude
+46
-20
-
+60
°C
Non-operational
+70
°C
Operational, above Sea Level, refer derating to Ta
Vi nom, 50% Io nom, TA = 25°C
10,000
Feet
dBA
Na
Audible Noise
60
Width
Height
Depth
54.5
Dimensions
Weight
40.0
mm
kg
321.5
M
1.13
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PFE1500 Series
Normal Air Flow
NOTE: A 3D step file of the power supply casing is available on request.
Figure 28 Side View 1
Figure 29. Top View
Figure 30. Side View 2
Figure 31. Front and Rear View
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PFE1500 Series
Normal Air Flow
NOTE: A 3D step file of the power supply casing is available on request.
Figure 32. Side View 1
Figure 33. Top View
Figure 34. Side View 2
Figure 35. Front and Rear View
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PFE1500 Series
Normal Air Flow
NOTE: A 3D step file of the power supply casing is available on request.
Figure 36. Side View 1
Figure 37. Top View
Figure 38. Side View 2
Figure 39. Front and Rear View
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PFE1500 Series
AC INPUT CONNECTOR:
PFE1500-12-054NA/RA: Power supplier connector: IEC320 C14 type
PFE1500-12-054NAC/RAC: Power supplier connector: IEC320 C16 type
PFE1500-12-054NAH/RAH: Power supplier connector: RongFeng P/N RF-203-D-1.0
Mating connector:
BizLink, type: BC-326, http://www.bizlinktech.com/
LongWell, type: LS-26, http://www.longwell.com/cn/
LINETEK, type: LS-24, http://w3.linetek.com.tw/html/F2_E.htm
DC OUTPUT CONNECTOR:
Power Supply Connector: Tyco Electronics P/N 2-1926736-3 (NOTE: Column 5 is recessed (short pins))
Mating Connector:
Tyco Electronics P/N 2-1926739-5 or FCI 10108888-R10253SLF
PIN
NAME
V1
DESCRIPTION
Output
6, 7, 8, 9, 10
+12 VDC main output
Power ground (return)
1, 2, 3, 4, 5
PGND
Control Pins
A1
VSB
Standby positive output (+3.3/5 VSB or 12 VSB
Standby positive output (+3.3/5 VSB or 12 VSB
Standby positive output (+3.3/5 VSB or 12 VSB
Standby positive output (+3.3/5 VSB or 12 VSB
Standby positive output (+3.3/5 VSB or 12 VSB
Signal ground (return)
)
)
)
)
)
B1
VSB
C1
VSB
D1
VSB
E1
VSB
A2
SGND
B2
SGND
Signal ground (return)
C2
HOTSTANDBYEN_H
VSB_SENSE_R
VSB_SENSE
APS
Hot standby enable signal: active-high
D2
Standby output negative sense (Not used for 12 VSB model)
Standby output positive sense (Not used for 12 VSB model)
I2C address and protocol selection (select by a pull down resistor)
Reserved
E2
A3
B3
N/C
C3
SDA
I2C data signal line
D3
V1_SENSE_R
V1_SENSE
SCL
Main output negative sense
E3
Main output positive sense
I2C clock signal line
A4
B4
PSON_L
SMB_ALERT_L
N/C
Power supply on input (connect to A2/B2 to turn unit on): active-low
SMB Alert signal output: active-low
C4
D4
Reserved
E4
ACOK_H
PSKILL_H
ISHARE
PWOK_H
VSB_SEL
PRESENT_L
AC input OK signal: active-high
A5
Power supply kill (lagging pin): active-high
Current share bus (lagging pin)
B5
C5
Power OK signal output (lagging pin): active-high
Standby voltage selection (lagging pin) (Not used for 12 VSB model)
Power supply present (lagging pin): active-low
D5
E5
tech.support@psbel.com
27
PFE1500 Series
Bel Power Solutions I2C Utility
Windows XP/Vista/7 compatible GUI to
program, control and monitor PFE Front-Ends
(and other I2C units)
belfuse.com/power-solutions
N/A
Dual Connector Board
Connector board to operate 2 PFE units in
parallel. Includes an on-board USB to I2C
converter (use Bel Power Solutions I2C Utility as
desktop software).
SNP-OP-BOARD-01 or
YTM.G1Q01.0
belfuse.com/power-solutions
Latch Lock
Optional latch lock to prevent accidental
removal of the power supply from the system
while the AC plug is engaged.
XSL.00019.0
Bel Power Solutions
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support
systems, equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change
depending on the date manufactured. Specifications are subject to change without notice.
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BCD.00733_AE
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