STM54-1V0M050-8EBX [BEL]
48V-to-PoL isolated DC-DC converters;
| 型号： | STM54-1V0M050-8EBX |
| 厂家： | 
BEL FUSE INC. |
| 描述： | 48V-to-PoL isolated DC-DC converters |
| 文件： | 总30页 (文件大小：1847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAIN AND SATELLITE POWER STAMP
48V-to-PoL isolated DC-DC converters
The MAIN and SATELLITE Power Stamp are isolated DC-DC converters
that converts a 48V or 54V bus voltage into a low voltage suitable for
typical server’s motherboard subsystems.
Key Features and Benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Over 94% efficiency at 1.8Vout
Over 91% efficiency at 1.0Vut
Up to 140W continuout power / 200W peak
Up to 70A continuous outut current / 100A peak
Wide 40V to 60V voltage range
Power density exceding 300W/in3
Parallelable with automatic phase shedding
Flat efficiency curve over wide load ranges
ource and sink mode for fast transient response
Isolated power train
Secndary side fully digital control
PMBUs with configurable AVS or Intel SVID interface
Industry standard SMT package
Reference designs for selected applications
Applications
• Direct conversion from 48V or 54V bus
• High performance computing
• Servers, storage and data processing equipment
• Communication systems
• Intel VR13 HC CPUs
• DDR4 memory
• Low voltage, high current ASICs and FPGAs
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STM48-MAIN
STM48-SATELLITE
Model Selection
Input Voltage Output Voltage* Output Current Output Current
Efficiency
(typical)
Part Number
[V]
[V]
[A]
[A peak]
MAIN Power Stamps
STM48-1V8M070-xxx
STM48-1V2M070-xxx
STM48-1V0M070-xxx
SATELLITE Power Stamps
STM48-1V8S070-xxx
STM48-1V2S070-xxx
STM48-1V0S070-xxx
Controller IC
40 – 60
40 – 60
40 – 60
1.6 – 2.0
1.16 – 1.26
0.9 – 1.1
70
70
70
100
100
100
94%
91.6%
91%
40 – 60
40 – 60
40 – 60
1.6 – 2.0
1.16 – 1.26
0.9 – 1.1
70
70
70
100
10
100
94%
91.6%
91%
STPSA60
-
-
-
-
-
* Contact factory for NVM configuration files for different output voltage settings
Order Information
Product
Family
STM
Input
Voltage
48
-
-
Output Voltage
1V8
Module style
M
Output Current
070
-
-
Options
xxx
0 – 9= custom
Z= RoHS
G= Tray pkg.
EBx= Eval. Bd.
(x= number of
populated
050= 50A
060= 60A
070= 70A
080= 80A
090= 90A
100= 100A
Power
Stamp form
factor
1V8= 1.8V
1V2= 1.215V
1V0= 1.0V
48= 40 – 60V
54= 46 – 59V
M= MAIN
S= SATELLITE
-
-
stamps)
Rev. 1.0 – 21/02/2018
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Page 2 of 30
STM48-MAIN
STM48-SATELLITE
Typical Intel VR13 HC CPU and DDR4 Memory Application
12V
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
54V BUS
54V BUS
12V BUS
54V BUS
1.215V
100A
VDDQ
MAIN
SATELLITE
V
niPoL
VPP
niPoL
SATELLITE
MAIN
1.8V
VccIN
400A
VccIO
VR13 HC
CPU
SATELLITE
SATELLITE
VccSA
VccANA
Vcc1P8
12V BUS
niPoL
RBC
niPoL
niPoL
niPoL
CPU and DDR rails
>10W power rails
<10W power rails
12V
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
DDR4 DIMM
54V BUS
12V BUS
1.215V
100A
VDDQ
MAIN
SATELLITE
Vtt
niPoL
VPP
niPoL
Rev. 1.0 – 21/02/2018
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Page 3 of 30
STM48-MAIN
STM48-SATELLITE
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings
only and functional operation of the device at these conditions is not implied. Operating outside maximum
recommended conditions for extended periods may affect product reliability and result in device failures.
Symbol
Parameter
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
Max
76
TBD
14
Units
V
V
+IN to -IN
Vout to GND
VDD
Non-operating continuous input voltage
Continuous output voltage
Primary auxiliary bias voltage
Secondary auxiliary bias voltage
V
V
VCC
7
PWM_X, PWM_Y
PWM_S, START
START
(2)
(3)
6.65
7
V
V
(3)
7
V
TMN, TMP
CSP, CSN
CSP, CSN
All other pins
Tmax
(3)
(3) (4)
(3) (4)
(3)
Ambient temperature
Storage temperature
7
V
V
V
V
°C
°C
2.5
2.5
7
+85
+100
Tstg
-40
Notes:
1) All voltages referenced to GND unless otherwise specified
2) Need to be lower than VDD nder any condition
3) Need to be lower than VCC under any condition
4) Max differential voltae to be limited within 100mV
Specifications
Specifications are typical and apply for the conditions: VDD= 5V, VCC= 5V, Tamb= 25°C unless otherwise noted.
Input Specificat– All models
Parameter
Symbol
Min
Typ
Max
Units
Input voltage
VIN
40
48
60
V
Continuous; VDD, VCC applied
Maximum input current
VIN= 40V – 60V, IO = IO_max
Input quiescent current
VIN= 48V, IO = 0A, enabled
Input stand by current
VIN= 48V, disabled
IIN_max
IIN_NL
-
-
4
A
TBD
TBD
mA
IIN_stdby
I2t
mA
A2s
Inrush transient
Input reflected ripple current
IIN_rr
TBD
mAp-p
5Hz to 20MHz, 1μH source impedance; VIN= 40V to 60V, IO= IO_max
Input ripple rejection
Internal input capacitance
PSRR
CIN
TBD
TBD
dB
µF
Rev. 1.0 – 21/02/2018
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Page 4 of 30
STM48-MAIN
STM48-SATELLITE
Output Specifications – 1.8V
Parameter
Symbol
Min
Typ
Max
Units
Output voltage setpoint
Output voltage trim range
Trim VID resolution
Output Regulation
VOUT
VOUT_adj
1.820
1.6
1.83
1.839
2.0
V
V
mV
10
Line (VIN= VIN_min to VIN_max
Load (IOUT= IOUTmin to IOUTmax
Temperature (Tref= Tamb_min to Tamb_max
)
-
-
-
8
10
TBD
mV
mV
%VOUT_nom
)
)
Total regulation band
-
-
44
20
mVp-p
mVp-p
AC, IOUT= IOUT_min to IOUT_max
Output voltage ripple and noise
VIN= 48V and IOUT= IOUT_min to IOUT_max
Vr
5Hz to 20 MHz bandwidth, nominal output capacitance
Output capacitance
ESR > 0.15mΩ
ESR > 10mΩ
-
-
TBD
TBD
COUT
µF
Continuous output current
in either source or sink mode
Peak output current
TBD, in either source or sink mode
Output current limit
TBD
IOUT
0
70
A
IOU_peak
IUT_CL
IOUT_SC
-
100
180
TBD
Apeak
150
% IOUT_max
ARMS
Output short circuit current
TBD
Efficiency
VIN= 48V, Tamb= 25°C
IOUT= 50% of IOUT_max , VOUT= VOUT_nom
Switching frequency
94.0
200
94.1
450
%
η
fSW
600
kHz
Rev. 1.0 – 21/02/2018
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Page 5 of 30
STM48-MAIN
STM48-SATELLITE
Output Specifications – 1.2V
Parameter
Symbol
Min
Typ
Max
Units
Output voltage setpoint
Output voltage trim range
Trim VID resolution
Output Regulation
VOUT
VOUT_adj
1.194
1.16
1.2
1.206
1.26
V
V
mV
5
Line (VIN= VIN_min to VIN_max
Load (IOUT= IOUTmin to IOUTmax
Temperature (Tref= Tamb_min to Tamb_max
)
-
-
-
2
8
TBD
mV
mV
%VOUT_nom
)
)
Total regulation band
-
-
-
mVp-p
mVp-p
AC, IOUT= IOUT_min to IOUT_max
Output voltage ripple and noise
VIN= 48V and IOUT= IOUT_min to IOUT_max
Vr
12
5Hz to 20 MHz bandwidth, nominal output capacitance
Output capacitance
ESR > 0.15mΩ
ESR > 10mΩ
-
-
TBD
TBD
COUT
µF
Continuous output current
in either source or sink mode
Peak output current
TBD, in either source or sink mode
Output current limit
TBD
IOUT
0
70
A
IOU_peak
IUT_CL
IOUT_SC
-
100
180
TBD
Apeak
150
% IOUT_max
ARMS
Output short circuit current
TBD
Efficiency
VIN= 48V, Tamb= 25°C
IOUT= 50% of IOUT_max , VOUT= VOUT_nom
Switching frequency
91.3
200
91.6
450
%
η
fSW
600
kHz
Rev. 1.0 – 21/02/2018
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Page 6 of 30
STM48-MAIN
STM48-SATELLITE
Output Specifications – 1.0V
Parameter
Symbol
Min
Typ
Max
Units
Output voltage setpoint
Output voltage trim range
Trim VID resolution
Output Regulation
VOUT
VOUT_adj
0.995
0.9
1.0
1.005
1.1
V
V
mV
5
Line (VIN= VIN_min to VIN_max
Load (IOUT= IOUTmin to IOUTmax
Temperature (Tref= Tamb_min to Tamb_max
)
-
-
-
TBD
TBD
TBD
mV
mV
%VOUT_nom
)
)
Total regulation band
180
-
mVp-p
mVp-p
AC, IOUT= IOUT_min to IOUT_max
Output voltage ripple and noise
VIN= 48V and IOUT= IOUT_min to IOUT_max
Vr
TBD
5Hz to 20 MHz bandwidth, nominal output capacitance
Output capacitance
ESR > 0.15mΩ
ESR > 10mΩ
-
-
TBD
TBD
COUT
µF
Continuous output current
in either source or sink mode
Peak output current
TBD, in either source or sink mode
Output current limit
TBD
IOUT
0
70
A
IOU_peak
IUT_CL
IOUT_SC
-
100
180
TBD
Apeak
150
% IOUT_max
ARMS
Output short circuit current
TBD
Efficiency
VIN= 48V, Tamb= 25°C
IOUT= 50% of IOUT_max , VOUT= VOUT_nom
Switching frequency
91.0
200
91.3
450
%
η
fSW
600
kHz
Feature Specificatio
Pin or Pad
Supply pins
meter
Min
4.5
Typ
Max
Units
VDD supply voltage
VDD supply current
VCC supply voltage
VCC supply current
Not used
5
-
5.5
150
5.5
V
VDD
VCC
mA
V
4.5
5
-
150
mA
VREG
VCTRL
-
Not used
-
Under Voltage Lock Out
VDD rising threshold
Hysteresis
4.2
4.3
V
VDD
500
mV
Output Enable
Input HIGH, rising
Input LOW, falling
Leakage, VEN= 1.1V
0.7
1
mV
mV
µA
0.4
Rev. 1.0 – 21/02/2018
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Page 7 of 30
STM48-MAIN
STM48-SATELLITE
Protections
+S
Feedback disconnection
Feedback disconnection
Peak protection
700
500
mV
mV
V
-S
VRSMON
3.045
PMBus Interface
Input HIGH, rising
Input LOW, falling
1.8
V
V
SDA
SCL
1.4
13
SDA
SALERT
Output pull down, ISINK= 5mA
Ω
SADDR
RDOWN resistor (see PMBus Address section)
10
kΩ
SVID / AVS Interface
Input HIGH, rising
Input LOW, falling
0.65
V
V
SVDAT / AVSMDAT
SVCLK / AVSCLK
0.45
13
SVDAT / AVSMDAT
SV_ALRT / AVSSDAT
Output pull down, ISINK= 5mA
Ω
CPU Link Interface
VR_HOT#
13
13
45
Ω
Ω
VR_RDY
Output pull down, ISINK= 5mA
FAULT#
Ω
Input HIGH, rising
1.7
V
VCCIO_OK
Input LOW, falling
1.5
13
V
PFAULT_IN#
PIN_ALERT#
Pull up current
10
µA
Ω
Output pull down, ISINK= 5mA
Primary uController Interface
Input HIGH, rising
1.7
V
V
PUCCS, PUCCK
PUCDTI
Input LOW, falling
1.5
Output HIGH voltage, ISOURC= 1mA
Output LOW voltage, ISINK= 5mA
4.5V
PUCDTO
125
250
mV
Output Pins
Output Hvoltag, ISOUCE= 1mA
Outpoltage, ISINK= 1mA
Active h impedance (HiZ)
4.90
4.95
25
V
mV
V
PWMx
STARTx
50
STARTx
1.55.
1.60
1.65
General Specifictions
Parameter
Symbol
Min
Typ
Max
Units
Relative humidity
Operating, non-condensing
Altitude
RH
10
90
%
-500
4000
ft.
Calculated MTBF
Calculated Per Telcordia SR-332, Issue2, Method 1, Case 3
VIN= 48 V, VOUT=1.83 V, IOUT= 70 A, Tamb= 40°C , FIT=109/MTBF
Weight
MTBF
TBD
12
Hours
g
Dimensions
L x W x H
30
12.7
18
mm
Rev. 1.0 – 21/02/2018
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Page 8 of 30
STM48-MAIN
STM48-SATELLITE
Performance Characteristics – 1.8V
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Efficiency and Power Dissipation
Thermal DeratiCurves
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Ripple and Noise
Switching Frequency vs. Output Current
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Transient Response – 10% IOUT to 100% IOUT, VIN= 48V
Rev. 1.0 – 21/02/2018
Transient Response – 100% IOUT to 10% IOUT, VIN= 48V
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Page 9 of 30
STM48-MAIN
STM48-SATELLITE
Performance Characteristics – 1.2V
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Efficiency and Power Dissipation
Thermal DeratiCurves
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Ripple and Noise
Switching Frequency vs. Output Current
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Transient Response – 10% IOUT to 100% IOUT, VIN= 48V
Rev. 1.0 – 21/02/2018
Transient Response – 100% IOUT to 10% IOUT, VIN= 48V
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Page 10 of 30
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STM48-MAIN
STM48-SATELLITE
Performance Characteristics – 1.0V
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Efficiency and Power Dissipation
Thermal DeratiCurves
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Ripple and Noise
Switching Frequency vs. Output Current
Please contact Bel Power Solutions for information
about the performance of this product
Please contact Bel Power Solutions for information
about the performance of this product
Transient Response – 10% IOUT to 100% IOUT, VIN= 48V
Rev. 1.0 – 21/02/2018
Transient Response – 100% IOUT to 10% IOUT, VIN= 48V
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Page 11 of 30
STM48-MAIN
STM48-SATELLITE
Block Diagram - MAIN
Primary
Secondary
VDD
+IN
MAIN
PWM_X
VCC
VOUT
t
PWM_Y
-IN
GND
N1
CSP1
PWM1S START1
VCC
MP1
CSN1
= Block pins
= LGA pa ds
+S
-S
PWM1_6Y
Phase 1 ÷ 6
PWM1_6X
TMN
(primary parallel bus)
VC
TM2_6
VCTRL
CSP2_6
CSN2_6
Phase 1 ÷ 6
(secondary parallelbus)
START2_6
STPSA60
VREG
LDO
not used
CPU I/F
SVID I/F
IRQ
SVID /
AVS
Primary uC I/F
PuC
PMBus
PMBus I/F
Rev. 1.0 – 21/02/2018
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Page 12 of 30
STM48-MAIN
STM48-SATELLITE
Package Pinout – MAIN
Land designator per JEP95, SEC. 3, SPP-010 AND SPP-020, Zero orientation with pin 1 in lower left corner
Pin Description – MAIN
Pad #
A1
B1
C1
D1
E1
Pad name
N/A
Panction
present
d present
No Pad present
Primay side fault indicator
Primary side uC data output
Primary side uC data input
PWM signal for Satellite 1
PWM signal for Satellite 2
PWM signal for Satellite 3
PWM signal for Satellite 4
PWM signal for Satellite 5
No Pad present
No Pad present
No Pad present
No Pad present
No Pad present
No Pad present
No Pad present
Feed-forward sensor input
Primary side uC chip select
Primary side u-controller clock
Pad #
A4
B4
C4
D4
E4
Pad name
N/C (-In)
N/C (-In)
N/A
TMP3
CSP3
CSN3
GND
GND
GND
Pad Function
Pad present, N/C, Thermal via
Pad present, N/C, Thermal via
No Pad present
N/A
N/A
PFAUL
PUC
PUCDT
PWM1Y
PWM2Y
PWM3Y
PWM4Y
PWM5Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VSRMON
PUCCS
PUCCK
Temperature sense Satellite 3
Current sense +v Satellite 3
Current sense -v Satellite 3
Secondary side ground
Secondary side ground
Secondary side ground
Secondary side ground
Programmable fault indicator
Start for Satellite 6
F1
F4
G1
H1
J1
K1
L1
M1
N1
P1
R1
A2
B2
C2
D2
E2
G4
H4
J4
K4
L4
M4
N4
P4
R4
A5
B5
C5
D5
E5
GND
FAULT#
START6
START3
GND
Start for Satellite 3
Secondary side ground
Secondary side ground
Pad present, N/C, Thermal via
Pad present, N/C, Thermal via
No Pad present
Temperature sense Satellite 2
Current sense +v Satellite 2
Current sense -v Satellite 2
GND
N/C (-In)
N/C (-In)
N/A
TMP2
CSP2
F2
F5
CSN2
Rev. 1.0 – 21/02/2018
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Page 13 of 30
STM48-MAIN
STM48-SATELLITE
Pad #
G2
H2
J2
K2
L2
M2
N2
P2
R2
A3
B3
C3
D3
E3
Pad name
PWM1X
PWM2X
PWM3X
PWM4X
PWM5X
N/A
N/A
N/A
N/A
N/C (-In)
N/C (-In)
N/A
TMP5
CSP5
Pad Function
Pad #
G5
H5
J5
K5
L5
M5
N5
P5
R5
A6
B6
C6
D6
E6
Pad name
GND
GND
GND
GND
VR_RDY
VREG
START2
GND
Pad Function
PWM signal for Satellite 1
PWM signal for Satellite 2
PWM signal for Satellite 3
PWM signal for Satellite 4
PWM signal for Satellite 5
No Pad present
No Pad present
No Pad present
No Pad present
Secondary side ground
Secondary side ground
Secondary side ground
Secondary side ground
Voltage regulator ready signal
Optional regulator input
Start for Satellite 3
Secondary side ground
Secondary side ground
Pad present, N/C, Thermal via
Pad pesent, N/C, Thermal via
No Papresent
Tempature sense Satellite 4
Current sense +v Satellite 4
Current sense -v Satellite 4
Secondary side ground
Secondary side ground
Secondary side ground
Secondary side ground
Enable signal
GND
Pad present, N/C, Thermal via
Pad present, N/C, Thermal via
No Pad present
N/C (-Vin)
N/C (-Vin)
N/A
TMP4
CSP4
CSN
G
GND
GND
D
EN
VCTRL
START4
GND
GND
N/A
Temperature sense Satellite 5
Current sense +v Satellite 5
Current sense -v Satellite 5
Secondary side ground
Secondary side ground
Secondary side ground
Secondary side ground
PWM signal for Satellite 6
PWM signal for Satellite 6
Start for Satellite 5
Secondary side ground
Secondary side ground
No Pad present
No Pad present
No Pad present
F3
CSN5
GND
GND
GND
F6
G3
H3
J3
K3
L3
M3
N3
P3
R3
A7
B7
C7
G6
H6
J6
K6
L6
M6
N6
P6
R6
A8
B8
C8
GND
PWM6X
PWM6Y
START5
GND
GND
N/A
Controller supply voltage
Start for Satellite 4
Secondary side ground
Secondary side ground
No Pad present
N/A
N/A
N/A
N/A
No Pad present
No Pad present
Temperature sense -v common
for TMN of all Satellites.
Remote sense +v
Remote sense -v
PMBus address setting
PMBus clock
D7
TMP6
Temperature sense Satellie 6
D8
TMN
E7
F7
G7
H7
CSP6
CSN6
SALERT
SDA
Current sense +v Satellite 6
Current sense -v Stellite 6
PMBus Alert
E8
F8
G8
H8
+S
-S
SADDR
SCL
PMBus data
SVDAT /
AVSMDAT
SVCLK /
AVSCLK
SVALRT /
AVSSDAT
J7
K7
L7
SVID data AVS MData
ot
J8
K8
L8
SVID clock / AVS clock
SVID alert / AVS SData
SVI Pad Alert #
VR_HOT#
VCCIO_O
Vfault shutdown – immediate
unit hutdown
PAD_ALERT#
M7
N7
P7
N
N/A
N/A
N/A
No Pad present
No Pad present
No Pad present
No Pad present
M8
N8
P8
N/A
N/A
N/A
N/A
No Pad present
No Pad present
No Pad present
No Pad present
R7
R8
For the description of large pads numbered from 1A1 to 2D5, please refer to the table in: Pin Description – SATELLITE
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STM48-MAIN
STM48-SATELLITE
Block Diagram – SATELLITE (with external STPSA60 Controller)
Primary
Secondary
VDD
+IN
SATELLITE
VCC
VOUT
t
-IN
GND
MN
CSP
PWM_S
TMP
CSN
PWM_X
PWM_Y
START
START1
-S
PWM1Y
TMP1
PWM1
TMN1
CSP1
Phase 1
= Block pins
CSN1
TM2_6
CSP2_6
CSN2_6
START2_6
STPSA60
PWM2_6Y
PWM2_6X
Phase 2 ÷ 6
(secondary parallelbus)
Phase 2 ÷ 6
(primary parallel bus)
IRQ
CPU I/F
SVID I/F
SVID /
AVS
PuC
PMBus
Primary uC I/F
PMBus I/F
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STM48-MAIN
STM48-SATELLITE
Package Pinout – SATELLITE
Land designator per JEP95, SEC. 3, SPP-010 AND SPP-020, Zero orientation with pin 1 in lower left corner
Pin Description – SATELLITE
Pin #
1A1
1A2
1A3
1A4
A1
2A
2B1
2B5
2C1
2C5
2D1
2D2
2D3
2D4
2D5
Pin name
+IN
PWM_Y
VDD
PWM_X
+IN
-IN
Pin Function
Positive input voltage supply
PWM input Y
Primary side auxiliary voltage supply
PWM input X
Positive input voltage supply
Primary side ground
-IN
Primary side ground
START
PWM_S
TMN
VCC
TMP
CSP
GND
VOUT
CSN
VOUT
GND
Synchronous rectifier START signal
Synchronous rectifier PWM signal
Temperature monitor negative output
Secondary side auxiliary voltage supply
Temperature monitor positive output
Current monitor positive output
Secondary side ground
Positive output voltage
Current monitor negative output
Positive output voltage
Secondary side ground
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Page 16 of 30
STM48-MAIN
STM48-SATELLITE
Feature Description - MAIN
The MAIN Power Stamp is a standalone DC-DC PoL converter designed to control multi-phase, interleaved arrays of
SATELLITE Power Stamps. It includes an on-board SATELLITE and an STPSA60 Digital Multi-cell Controller in a single
package. MAIN and SATELLITE are using the same pinout for signals available in both modules. The MAIN module
additionally includes an LGA connector for control signals not present on SATELLITE. A single MAIN can control up to
five SATELLITE for an array of six phases, maximum. Several digital interfaces are included for ease of integration into
complex microprocessor applications.
Primary Microcontroller Interface
The digital multi-cell controller embedded in the MAIN Power Stamp monitors input/outut voltage, power and
current in order to manage OV, UV and OC events and to provide telemetry data tthe CPU and PMBus interfaces.
The Primary Microcontroller Interface (PuC I/F) transmits information about tmetry from the primary side.
Either digital or analog transmission methods are available. A serial interfas conveniently used in isolated
configurations (PUCDTO, PUCDTI, PUCCK and PUCCS pins) with external digital isolators. Non-isolated configurations
can take advantage of the analog VRSMON signal. User can program how when to use such configurations and
telemetry data information. Following standard PMBus implementation, eh protection features a programmable
warning and fault limits and actions. Protections are configurable and useto trigger special outputs of the CPU
interface. Please refer to the STPSA60 Data Sheet and GUI User anual foa list of the specific commands supported.
MAIN
DigitaMulti-cell
Controller
PFA ULT_IN# D1
VR_HOT# K7
FAULT# L4
PUCDTO
E1
VR_RDY L5
VCCIO_OK L7
PIN_ALERT# L8
EPUCS
F1 PUCDTI
F2 PUCCK
IRQ
PuC
I/F
P
CPU I/F
EN L6
CPU Interface
The EN pin is an active-high signal that enables the converter when pulled up to VCC, connect to GND to disable.
Please contact Intel for detailed information regarding the CPU interface and a list of the specific signals supported.
PMBus Interface
The MAIN Power Stamp has a PMBus interface that supports both communication and control. The PMBus Power
Management Protocol Specification can be obtained from www.pmbus.org. The modules support a subset of version
1.2 of the standard and is fully compatible with the PMBus™ specification for read/write access in the byte, word,
block mode. More than 110 commands are implemented, covering all the basic and advanced functions of the device.
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STM48-MAIN
STM48-SATELLITE
Parameters are programmed using PMBus and stored in the embedded Non Volatile Memory as defaults for later use.
Only those specifically identified as capable of being stored are saved. The write protection capability of the device
prevents any unintended writing.
MAIN
VCC
2B5
M6
VCTRL
Digital Multi-cell
Controller
VREG
M5
LDO
SDA H7
SCL H8
PMBus
PMBus I/F
SADDR G8
SALERT G7
SVDAT / AVSMDAT J7
SVCLK / AVSCLK J8
SV_ALRT / AVSSDAT K8
SVID /
AVS
SV/ AVS I/F
The device also supports the SALERT response protocol whereby the module can alert the bus master if it wants to
talk. For more information on the SMBus alert esponse protocol, see the System Management Bus (SMBus)
specification. Please refer to the STPSA60 Data Sheet and GUI User Manual for a list of the specific commands
supported.
PMBus Address
The PMBus slave address is configured at the startup of the device by reading the voltage on the ADDR pin. The proper
resistor divider must be connected from the ADDR pin to the GND and VCC pins. Additional configurations are stored
into the NVM and correspong Sysem Registers. For a list of MAIN unit System Registers please see the STPSA60
data sheet.
RUP (on the host board)
RDOWN (inside the MAIN unit)
Resistor series Resistor value Ω
PMBus Add
Resistor series
Resistor value Ω
OPEN
B8
B4
B2
B0
E8
E4
E2
E0
D8
D4
D2
D0
C8
C4
C2
C0
E12
E12
E12
E12
E24
E96
E12
E12
E48
E48
E96
E48
E96
E96
E48
E96
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
E12
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
220,000
120,000
82,000
62,000
48,700
39,000
33,000
27,400
23,700
20,500
17,800
15,800
13,700
12,100
10,700
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STM48-MAIN
STM48-SATELLITE
SVID / AVS Interface
The MAIN Power Stamp supports alternatively Intel Serial VID interface (SVID) or PMBus Adaptive Voltage Scaling
interface (AVS) for output voltage positioning. The SVID interface communicates with Intel microprocessor through
three wires, SVCLK, SVDAT, and SV_ALRT, and controls the VID code change rate. It is fully compliant with Intel VR13
PWM rev 1.1, document # 544905 and Intel SVID protocol Rev1.7, document # 456098. To guarantee proper device
and CPU operations, refer to these documents for bus design and layout guidelines. Different platforms may require
different pull-up impedance on the bus. Please contact Intel for detailed information regarding the SVID interface.
FPGAs, ASICs, SoCs and non-Intel processors can adaptively change their supply voltages using AVS. The SVID and AVS
interfaces share the same hardware and switching between the two can happen at run time. The corresponding AVS
pin names are AVSCLK, AVSMDAT and AVSSDAT.
Paralleling
The block diagram of the MAIN Power Stamp digital control loop is illustrated in tfigure:
MAIN
Digital Multi-cell Conler
E8 +S
F8 -S
+
-
+
Remote
buffer
ADC
PID
PWM1X G2
PWM1Y G1
PWM2X H2
PWM2Y H1
PWM3X J2
PWM3Y J1
PWM4X K2
PWM4Y K1
PWM5X L2
PWM5Y L1
PWM6X L3
PWM6Y M3
Vref
DAC
+
droop
Digital
COT
control
E5
CSP2
Temp. com
Primary parallel bus
F5 CSN2
E4 CSP3
F4 CSN3
E6 CSP4
DPS
DPWM
Secondary parallel bus
F6
CSN4
E3 CSP5
F3 CSN5
E7 CSP
F7
Digital
current
sharing
N5
START2
START3 N4
START4 N6
START5 N3
START6 M4
Secondary parallel bus
Temperature sensor
Secondary parallel bus
The converter output voltage is differentially sensed by the +S and –S inputs of the remote buffer and compared with
a digitally adjustable voltage reference Vref. The output of the remote buffer is summed to a temperature
compensated (TMP) droop signal for load line generation and converted by the analog to digital converter (ADC) into
digital. Digital PID compensation is then applied before the signal is transmitted to the digital constant on time (COT)
control. Output currents of each individual phase are differentially sensed by the CSN and CSP inputs. A digital current
sharing block drives the digital COT control. Input voltage feedforward is applied to the digital COT control via the
VRSMON signal. Dynamic Phase Shedding (DPS) is computed as a function of the output current conditions and concurs
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STM48-MAIN
STM48-SATELLITE
to determine the switching frequency / duty cycle generated by the digital COT control. The digital PWM (DPWM)
modulator demultiplexes the resulting switching frequency for automatic phase shedding and interleaving.
Primary Parallel Bus
The primary parallel bus carries the PWM signals generated by the digital PWM modulator. Two out-of-phase
signals, PWMX and PWMY, are transmitted to the primary side, either directly or through optional digital isolators,
to drive the two sides of the full bridge power train.
Secondary Parallel Bus
The secondary parallel bus contains multiple input and output signals to/from the digital multi-cell controller. Each
SATELLITE in a parallel array, including the on-board power train of the MAIN converter, rovides output current
information through the differential CSPx and CSNx signals.
SATELLITE
L1
VOUT
Synch.
Rect.
L2
COUT
GND
t°
RTCM
RTCM
CTCM
An NTC sensor is installed in proximity of each output inductor for temperature compensated output current
measurement and the corresponding signal is fed to the digital multi cell controller via the TMPx pins. The TMN pin
provides pseudo-differential transmission of the TMPx signals. The DPWM modulator generates the STARTx signal to
synchronize the operation of the output synchronous rectifier with the PWMX and PWMY signals driving the input full
bridge.
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STM48-MAIN
STM48-SATELLITE
Paralleling – MAIN and SATELLITE Configuration
+IN
VOUT
+IN
VOUT
VCC
+5V
+5V
VDD
SATELLITE #n
STARTn, PWMnS
CSPn, CSNn
TMPn, TMNn
PWMnX
PWMnY
-IN
GND
+IN
VOUT
V
+5V
VDD
Power Train
STARTn, PWMnS
CSPn, Cn
TMPn, TM
PWMnX
PWMnY
-IN
GND
-IN
MAIN
S
Dital Multcell
Cntroller
IRQ
CPU I/F
SVID /
AVS
SVID I/F
PuC I/F
Power
Monitor
MCU
PuC
PMBus
PMBus I/F
Paralleled MAIN and SATEin a non-isolated configuration. The power train of both MAIN and SATELLITE Power
Stamps is inherentlolated; the power path isolation can be shorted on the motherboard in non-isolated
applications. Optiital isolators can provide isolated feedback and isolated input telemetry.
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STM48-MAIN
STM48-SATELLITE
Paralleling – STPSA60 and SATELLITE Configuration
+IN
VOUT
+IN
VOUT
VCC
+5V
+5V
VDD
SATELLITE #n
STARTn, PWMnS
CSPn, CSNn
TMPn, TMNn
PWMnX
PWMnY
-IN
GND
+IN
VO
VC
+5V
VDD
SATELLITE #1
STA1S
N1
TMMN1
PWM1X
PWM1Y
GND
-IN
-IN
GND
S
STPSA60
Controller
IRQ
CPU I/F
SVID /
AVS
SVID I/F
PuC I/F
Power
MCU
PuC
PMBus
Monitor
PMBus I/F
Paralleled SATELLITEs using n external STPSA60 controller installed on the motherboard. Digital isolators provide
isolated feedback oprimary parallel bus and isolated input telemetry via the primary microcontroller interface.
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Page 22 of 30
STM48-MAIN
STM48-SATELLITE
Safety Considerations
For safety agency approval the power module must be installed in compliance with the spacing and separation
requirements of the end-use safety agency standards, i.e. UL 60950-1 2nd, CSA C22.2 No. 60950-1-07, DIN EN 60950-
1:2006 + A11 (VDE0805 Teil 1 + A11):2009-11; EN 60950-1:2006 + A11:2009-03.
For the converter output to meet the requirements of safety extra-low voltage (SELV), the input must meet SELV
requirements as well. The power module has extra-low voltage (ELV) outputs when all inputs are ELV.
The Power Stamp series was tested using an external fast-acting fuse rated at TBD A, TBD VDC in the ungrounded
input.
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STM48-MAIN
STM48-SATELLITE
Mechanical Drawings – MAIN
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STM48-MAIN
STM48-SATELLITE
PCB Pattern Design – MAIN
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STM48-MAIN
STM48-SATELLITE
Mechanical Drawings – SATELLITE
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STM48-MAIN
STM48-SATELLITE
PCB Pattern Design – SATELLITE
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Page 27 of 30
STM48-MAIN
STM48-SATELLITE
Surface Mount Information
Pick and Place
The Power Stamp modules use an open frame construction and are designed for a fully automated assembly process.
The modules are fitted with a label designed to provide a large surface area for pick and place operations. The label
meets all the requirements for surface mount processing, as well as safety standards, and is able to withstand reflow
temperatures of up to 300°C. The label also carries product information such as product code, serial number and the
location of manufacture.
Nozzle Recommendations
The module weight has been kept to a minimum by using open frame construction. Variablesuch as nozzle size, tip
style, vacuum pressure and placement speed should be considered to optimize this process. The minimum
recommended inside nozzle diameter for reliable operation is 3mm. The maximuzle outer diameter, which will
safely fit within the allowable component spacing, is 7 mm.
Bottom Side / First Side Assembly
This module is not recommended for assembly on the bottom side of a tomer board. If such an assembly is
attempted, components may fall off the module during the second reflow prcess.
Lead Free Soldering
The modules are lead-free (Pb-free) and RoHS compliant and fully compatible in a Pb-free soldering process. Failure
to observe the instructions below may result in the failure of or cause damage to the modules and can adversely affect
long-term reliability.
Pb-free Reflow Profile
Power Systems will comply with J-STD-020 Rev. C (Moisture/Reflow Sensitivity Classification for Non-hermetic Solid
State Surface Mount Devices) for both Pb-free solder profiles and MSL classification procedures. This standard
provides a recommended forced-air-convection reflow profile based on the volume and thickness of the package
(table 4-2). The suggested Pb-free solder paste is Sn/Ag/Cu (SAC). The recommended linear reflow profile using
Sn/Ag/Cu solder is shown in the Soldeing Information section. Soldering outside of the recommended profile requires
testing to verify results and rmance.
MSL Rating
The Power Stamp s have a MSL rating of TBD.
Pre-baking
This component has been designed, handled, and packaged ready for Pb-free reflow soldering. If the assembly shop
follows JSTD-033 Rev. A guidelines, no pre-bake of this component is required before being reflowed to a PCB.
However, if the J-STD-033 Rev A guidelines are not followed by the assembler, Bel recommends that the modules
should be pre-baked @ 120~125℃ for a minimum of 4 hours (preferably 24 hours) before reflow soldering.
Storage and Handling
The recommended procedures for moisture-sensitive surface mount packages are detailed in J-STD-033 Rev. A.
Moisture barrier bags (MBB) with desiccant are required for MSL ratings of 2 or greater. These sealed packages should
not be broken until time of use. Once the original package is broken, the floor life of the product at conditions of <
30°C and 60% relative humidity varies according to the MSL rating (see J-STD-033A). The shelf life for dry packed SMT
packages will be a minimum of 12 months from the bag seal date, when stored at the following conditions: < 40° C, <
90% relative humidity.
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STM48-MAIN
STM48-SATELLITE
Soldering Information
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Page 29 of 30
STM48-MAIN
STM48-SATELLITE
The Power Stamp Alliance
The Power Stamp Alliance defines a standard product footprint and functions that provide a multiple-sourced,
standard board-mounted solution for power conversion for 48Vin to low voltage, h current applications.
These 48V direct conversion DC-DC modules - or 'power stamps' - primarily targdevices being used in large data
centers (e.g. CPU, DDR, FPGA, ASIC), many of which are following the principles of the Open Compute Project
(OCP).
Some of the first processor architectures addressed by the Power Stamp Allance are the Intel VR13 Skylake CPUs,
Intel VR13-HC Ice Lake CPUs, DDR4 memories, IBM POWER9 (9) architcture processors and devices using the
PMBus AVS protocol or SVID protocol.
48V single stage power conversion offers Open Compute Project and data center companies a range of business
and technical benefits.
www.powerstamp.org
Revision History
Date
Revisio
Notes
Approved
23/02/2018
0
First release
GM
For more information about these products, please consult tech.support@psbel.com
NUCLEAR AND MEDICAL APPLICATIONS
Products are not designed or intended for use as critical components in life support systems, equipment used in
hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS
The appearance of products, including safety agency certifications pictured on labels, may change depending on the
date of manufacturing. Specifications are subject to change without notice.
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Page 30 of 30
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