ZM7108-T2 [BEL]
DC-DC Regulated Power Supply Module, 1 Output, Hybrid;
| 型号： | ZM7108-T2 |
| 厂家： | 
BEL FUSE INC. |
| 描述： | DC-DC Regulated Power Supply Module, 1 Output, Hybrid |
| 文件： | 总29页 (文件大小：1214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZM7100 Series Digital Power Manager
Data Sheet
Member of the
Family
Features
•
Programs, controls, and manages up to 32
independent Z-series POL converters via the single
line digital Z-OneTM Bus
•
Programs output voltage, protections, optimal voltage
positioning, turn-on and turn-off delays and slew
rates, switching frequency, interleave (phase shift),
and feedback loop compensation of the Z-series POL
converters
User friendly ZIOSTM GUI interface for programming,
monitoring, and performance simulation
•
•
•
•
•
Intermediate bus voltage monitoring and protection
AC Fail input
Up to four programmable interrupt inputs
Ring buffer with programmable refresh rate to store
real time voltage, current, and temperature
measurements for up to 32 Z-POL converters
Applications
•
Non-volatile memory to store system configuration
information and status data
•
•
•
Low voltage, high density systems utilizing
Z-OneTM Digital Intermediate Bus Architectures
•
•
•
1 kbyte of user accessible non-volatile memory
Control of industry standard DC-DC front ends
Broadband, networking, optical, and
communications systems
Desktops, servers, and portable computing
Crowbar output to trigger the optional crowbar
protection
Benefits
•
Four independent OK lines for flexible fault
management and fast fault propagation
•
•
•
Eliminates the need for external power
management components
•
•
•
Small footprint horizontal SMT package: 32x16mm
Low profile of 6.25mm
Communicates with the customer system via the
industry standard I2C communication bus
Compatible with conventional pick-and-place
equipment
Reduces board space, system cost, complexity,
and time to market
•
Wide operating temperature range
Description
The ZM7100 is a fully programmable digital power manager that utilizes the industry-standard I2C communication
bus interface to control, manage, program and monitor up to 32 Z-series POL converters. The ZM7100 completely
eliminates the need for external components for power management and POL converters programming,
monitoring, and reporting. Parameters of the ZM7100 are programmable via the I2C bus and can be changed by a
user at any time during product development and service.
Selection Chart
Part Number
Number of Z-series POLs
that can be controlled
Active POL
Addresses
Number of POL
Groups
Number of
Interrupts
Number of
Parallel Buses
ZM7108
ZM7116
ZM7132
8
00…07
00…15
00…31
2
3
4
2
3
4
4
4
8
16
32
Note: DPMs with other combinations of parameters are available upon request. Contact factory for more details.
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Page 1 of 29
ZM7100 Series Digital Power Manager
Data Sheet
1. Reference Documents
•
•
•
ZY7xxx Point of Load Regulator. Data Sheet
Digital Power Manager. Programming Manual
ZIOSTM Graphical User Interface
2. Ordering Information
Part Number
ZM71xx1-yyyyy2-T1
ZM71xx-yyyyy-T2
ZM71xx-yyyyy-T3
ZM71xx-yyyyy-R1
ZM71xx-yyyyy-Q1
Description
Quantity of ZM71xx
Tape and Reel
Tape and Reel
500
100
50
24
1
Tape and Reel
Tray
Functional sample for evaluation only
One ZM7116 mounted on the
evaluation board
Z-ONE-KIT
Evaluation Kit
One ZM7116 mounted on the
evaluation board
Z-ONE-KIT-HBC3
Evaluation Kit with DC-DC Front End
1 Two digits representing the number of POLs the DPM can control: see the Selection Chart
2 5-digit identifier assigned by Power-One for each unique configuration file
3 Contact factory for other DC-DC Front End options
3. Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect
long-term reliability and cause permanent damage to the device.
Parameter
Ambient Temperature Range
Storage Temperature (Ts)
Input Voltage
Conditions/Description
Min
-40
-40
0
Max
85
Units
°C
100
14.0
3.8
°C
IBV and IBV_S pins
3V3 pin
VDC
VDC
Input Voltage
0
4. Mechanical and Reliability Specifications
Parameter
Conditions/Description
Min
Nom
Max
10
Units
Weight
grams
Calculated Per Telcordia
Technologies SR-332
MTBF
5.64
MHrs
Read-
Write
cycles
-40°C to 85°C ambient
25°C ambient
10,000
100,000
Non-Volatile Memory Endurance
Data Retention
40
years
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ZM7100 Series Digital Power Manager
Data Sheet
5. Electrical Specifications
5.1 Power Specifications
Parameter
Conditions/Description
Continuous, IBV pin
DPM stops operating, IBV pin
IBV pin
Min
4.0
Nom
Max
14.0
3.6
Units
VDC
VDC
mVDC
VDC
VDC
mVDC
mA
High Input Supply Voltage
High Supply Voltage Reset
High Reset Voltage Hysteresis
Low Input Supply Voltage
Low Supply Voltage Reset
Low Reset Voltage Hysteresis
Input Current
3.36
40
Continuous, 3V3 pin
DPM stops operating, 3V3 pin
3V3 pin
3.0
3.6
2.646
2.754
135
42
VIN from 3.0V to 14V
3V3 pin
Output Current
10
mA
5.2 Feature Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
Intermediate Voltage Bus Protections
Overvoltage Protection
Threshold
Undervoltage Protection
Threshold
Turns off all POLs, the Front End and
triggers Crowbar
Programmable
Programmable
Turns off all POLs
Front End Enable (FE_EN) 1
VFE_EN
Isrc
Front End Enable
Source Current
Front End Disable
Sink Current
2.5
2.5
VDD
10
VDC
mA
VFE_EN
Isink
0.5
10
VDC
mA
Crowbar (CB) 1
VCB
Isrc
Crowbar Enable
Source Current
VDD
VDC
mA
ms
10
TCB
Duration of Enabling Pulse
1
________________________
1 At start-up of the DPM, the output is in the high impedance state. To avoid pulling the pin high due to capacitive
coupling, it is recommended to connect a 3.3kOhm resistor between the pin and the Pin 24 GND.
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ZM7100 Series Digital Power Manager
Data Sheet
5.3 Signal Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
VDD
Internal supply voltage
3
3.3
3.6
V
SYNC/DATA Line
ViL_sd
ViH_sd
LOW level input voltage
HIGH level input voltage
-0.5
1.7
0.8
V
V
LOW level output voltage
Isink=8mA
VoL
0
0.4
75
V
SD fall time
Tf_sd
Tr_sd
ns
ns
System requirement 1
SD rise time
250
System requirement 1
Rpu_sd
Freq_sd
Pull-up resistor
Clock frequency
10
kΩ
475
22
525
28
kHz
% of clock
cycle
% of clock
cycle
Tsynq
T0
Sync pulse duration
Data=0 pulse duration
72
78
Interrupt Inputs (INT0_N, INT1_N, INT2_N, INT3_N, AC_FAIL, RES_N)
Rup_x
ViL_x
Pull-up resistor
17.5
-0.5
52.5
0.35 x
VDD
kΩ
LOW level input voltage
V
ViH_x
HIGH level input voltage
0.7 x VDD
0.06XVDD
VDD+0.5
V
V
Vhyst_x
Hysteresis of input Schmitt trigger
I2C Address Inputs
Rup_ADDRx
ViL_ADDRx
Pull-up resistor
17.5
-0.5
52.5
0.35 x
VDD
kΩ
LOW level input voltage
V
ViH_ADDRx
HIGH level input voltage
0.7 x VDD
0.06xVDD
VDD+0.5
V
V
Vhyst_ADDRx
Hysteresis of input Schmitt trigger
Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)
Rup_OKx
ViL_Okx
Pull-up resistor
17.5
-0.5
52.5
0.35 x
VDD
kΩ
LOW level input voltage
V
ViH_Okx
HIGH level input voltage
0.7 x VDD
0.06xVDD
VDD+0.5
V
V
Vhyst_OKx
Hysteresis of input Schmitt trigger
1 The SD rise and fall time depends on the number of POL converters connected to the SD bus and the total board distribution capacitance. It
is user’s responsibility to ensure the fall and rise time specifications given in this table are met.
5.4 I2C Interface
Parameter
Conditions/Description
Min
Nom
Max
Units
Standard according to I2C Bus
Specifications Version 2.1
HIGH level input voltage on I2C_SCL
and I2C_SDA lines
Data Transfer Rate
100
kbit/s
ViH_I2C_Sxx
VDD+0.5
V
4 MSBs hardwired
3 LSBs programmable
50h, 52h, 54h, 56h, 58h, 5Ah, 5Ch,
5Eh
Available Addresses
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ZM7100 Series Digital Power Manager
Data Sheet
6. Typical Applications
I2C
Auxiliary Supply
AC Fail
48V
IBV
I2C_SDA I2C_SCL
INT0_N
INT1_N
INT2_N
INT3_N
RES_N
AC Fail_N
FE_EN
CB
FE
Crowbar
(optional)
IBV_S
ZM7100
IBV
Group A
Group B
Group C
Group D
POL
POL
POL
POL
Vo1
Vo_n
Figure 1. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I2C Interface
The block diagram of a typical application of a ZM7100 digital power manager (DPM) is shown in Figure 1. The
system may include up to 32 Z-series Point Of Load converters (POLs). Each POL converter has a unique 5-bit
address programmed by grounding respective address pins. All POL converters are connected to the DPM and to
each other via a single-wire synchronization/data (SD) communication bus. The bus provides synchronization of
all POL converters to the master clock generated by the DPM and simultaneously performs bidirectional data
transfer between the POL converters and the DPM. The DPM communicates in a bidirectional way via the I2C bus
with the host system and/or ZIOSTM Graphical User Interface.
The DPM can be powered either directly from the intermediate voltage bus or from an independent voltage source.
In this case the DPM can control a DC-DC Front End via the FE_EN pin. The DPM can also trigger an optional
crowbar circuit and provide undervoltage and overvoltage protections of the intermediate bus voltage. In addition,
the DPM can be controlled by a host system via the interrupt inputs and the AC-Fail input.
There are four groups of POL converters in the application. A group is defined as a number of POL converters
interconnected via OK pins. Grouping of POL converters is optional, it enables users to program advanced fault
management schemes and define margining functions, monitoring, startup behavior, and reporting conventions.
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ZM7100 Series Digital Power Manager
Data Sheet
Figure 2. Complete Schematic of a Multiple Output Application that Includes a High Power Output
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ZM7100 Series Digital Power Manager
Data Sheet
7. Pinout Diagram
Pin Name
Pin
No.
Pin
Type
Buffer
Type
Pin Description
Notes
SD
OKD1
1
2
I/O
I/O
I/O
I/O
I/O
O
PU
PU
SYNC/DATA communication line
OK/FAULT line of POL group D
OK/FAULT line of POL group C
OK/FAULT line of POL group B
OK/FAULT line of POL group A
Front End enable signal
IBV crowbar signal
Bidirectional I/O port
Bidirectional I/O port
Bidirectional I/O port
Bidirectional I/O port
Bidirectional I/O port
OKC2
3
PU
OKB
4
PU
OKA
5
PU
FE_EN
CB
6
CMOS
CMOS
7
O
NC
8
Not used
Leave Floating
ADD2
9
I
I
PU
A
I2C Address bit 2
IBV_S
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IBV sense
Connect to IBV
Leave Floating
Not used
I2C_SCL
I2C_SDA
INT0_N
INT1_N
INT2_N2
INT3_N1
RES_N
ADD1
I/O
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
---
Serial clock I2C interface
Serial data I2C interface
Interrupt 0, active low
Interrupt 1, active low
Interrupt 2, active low
Interrupt 3, active low
Manual shutdown (active low)
I2C Address bit 1
Bidirectional I/O port
Bidirectional I/O port
I/O
I
I
I
I
I
I
ADD0
I
I2C Address bit 0
HW_RES_N
AC_FAIL_N
IBV
I
DPM reset (active low)
AC-Fail interrupt (active low)
Supply Voltage
I
P
P
DPM Input Power Supply
GND
---
Ground
Output of the Internal Linear
Regulator
3V3
25
P
---
3.3V Input/Output
Legend: I=input, O=output, I/O=input/output, P=power, CMOS=CMOS output stage, A=analog, PU=internal pull-up
1 ZM7132 only
2 ZM7116 and ZM7132 only
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ZM7100 Series Digital Power Manager
Data Sheet
8. Pins Description
AC_FAIL_N, AC Fail Input (Pin 22): A Schmitt-
Trigger input with internal pull-up resistor (active
low). Pulling low the input indicates to the DPM that
an AC-DC front-end has lost the mains and that a
system shut down should immediately be initiated.
inputs can be programmed to act as a remote enable
for a specific group(s) of POL converters. When
pulled low, the interrupt will turn-off respective POL
converters. When the interrupt is released, the POL
converters will turn-on according to their turn-on
delay and slew rate settings.
ADD[0:2], I2C Address Inputs (Pin 20, 19, 9):
Inputs with internal pull-up resistor. The 3 bit
encoded address determines the Digital Power
Manager’s communication address for the I2C
interface.
OKA, OKB, OKC, OKD, Group OK Signals (Pin 5,
4, 3, 2): Open drain input/outputs with internal pull-
up resistors. Pulling low the OK input will indicate to
the DPM a fault in a Group. The DPM can also pull
an OK line low to disable a Group of POL converters.
CB, Crowbar Output (Pin 7): A CMOS output which
is used to trigger a crowbar (SCR) in case of
overvoltage on the Intermediate Voltage Bus.
RES_N, Active Low Reset Input (Pin 18): An input
with internal pull-up resistor. When pulled low a soft
reset of the system (sequenced turn-off of all POL
converters) is initiated. When released the whole
system is reprogrammed and started (if Auto Turn-
On is enabled).
FE_EN, Front-End Enable (Pin 6): A CMOS output
which is used to turn-on/off the DC/DC converter
generating the IBV.
HW_RES_N, Hardware Reset (Pin 21): An input
with internal pull-up resistor. When pulled low a cold
start of the Digital Power Manager is initiated. This
function should not be used to initiate normal system
shutdown or turn-on.
SD, Sync/Data Line (Pin 1): An open drain
input/output
with
internal
pull-up
resistor.
Communication line to distribute a master clock and
at the same time to communicate with all POL
converters.
I2C_SDA, I2C_SCL, I2C Interface (Pin 13, 12).
Serial data (SDA) and clock (SCL) lines. Open drain
input/outputs with internal pull-up resistors. The pins
are not 5V tolerant; therefore, if external pull-ups are
added, they must be connected to the 3V3 pin of the
DPM.
3V3, VDD (Pin 25): The output of the internal 3.3V
linear regulator and input of an external 3.3V supply.
Also used for additional pull-ups on SD, I2C_SDA
and I2C_SCL lines
IBV, Positive Supply (Pin 23): Supply voltage.
GND, Ground (Pin 24): Ground.
IBV_S, Intermediate Voltage Bus Sense (Pin 10):
Analog input to an internal ADC circuit to monitor the
Intermediate Bus Voltage.
NC, No Connect (Pin 8, 11): All NC pins must
remain floating.
INT[0:3]_N, Interrupts (Pin 14, 15, 16, 17): Four
active low inputs with internal pull-ups. Each of the
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ZM7100 Series Digital Power Manager
Data Sheet
9. Digital Power Manager Description
The ZM7100 series DPMs perform translation between the I2C interface connected to a host system or the ZIOSTM
Graphical User Interface and the SD communication bus connected to Z-series POL converters. In addition,
DPMs carry out programming, monitoring, data storage, POL group management, protection, and control.
The DPMs can be controlled via the GUI or directly via the I2C bus by using high and low level commands as
described in the ‘”DPM Programming Manual”. DPM commands are summarized in Table 1.
Table 1. Commands From I2C to DPM
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
Description
Cmd
Data[0] Data[1] Data[2] Data[3] Data[4] Data[5] Data[6]
Low Level Commands
Write Data d into Register r of POL(s) a
Write Data d into DPM register r
Or Data d into DPM register r
And Data d into DPM register r
Write Data d into POL p Setup Register r
Read Data d from Register r of POL p
Read Data d from DPM register r
Read Monitoring Data d of type t from POL p
Read Data d from POL p setup register r
High Level Commands
0x01
0x02
0x03
0x04
0x05
0x11
0x12
0x13
0x15
a[3]
r
r
a[2]
a[1]
return
return
return
d
a[0]
r
d
return
d
d
d
r
r
d
t
r
p
p
r
p
p
return
return
d
return
numValid d[0…15] return
r
d
return
POL a Memory CRC check
Reprogram POL(s) a
Load POL p Setup Register Block into RAM
Store POL p Setup Register Block into Flash
Store DPM registers into Flash
Turn-On Group A
0x2F
0x31
0x32
0x33
0x34
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x39
0x3A
0x3B
0x40
a[3]
a[3]
p
a[2]
a[2]
return
return
a[1]
a[1]
a[0]
a[0]
return
return
p
return
return
return
return
return
return
return
return
return
return
return
return
return
return
return
return
m
Turn-On Group B
Turn-On Group C
Turn-On Group D
Turn-On all Groups
Turn-Off Group A
Turn-Off Group B
Turn-Off Group C
Turn-Off Group D
Turn-Off all Groups
Emergency Turn-Off Group A
Emergency Turn-Off Group B
Emergency Turn-Off Group C
Emergency Turn-Off Group D
Emergency Turn-Off all Groups
System Margining
return
STB
Front End On
Front End Off
return
return
STA
Read Status Monitoring Data
Read Parametric Monitoring Data
Read Time Counter
STC
STD
IMS
EST
return
0x41 Vo[0..31] Io[0..31] T[0..31] return
0x42
0x43
0x35
0x36
0x37
0x38
RTC[3] RTC[2] RTC[1] RTC[0] return
return
return
a[1]
return
a[1]
Clear Ring Buffer1
Load user memory from Flash into RAM
Writes a byte into user memory (RAM)
Save user memory in RAM into Flash
Read user memory byte from flash
a[0]
a[0]
d
d
return
return
1 In order to clear the buffer in both RAM and non-volatile memory, the command needs to be sent twice.
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ZM7100 Series Digital Power Manager
Data Sheet
Shaded cells in Table 1 indicate data transmitted from the DPM to the host, other cells indicate data transmitted
from the host to the DPM.
The DPM registers are listed in Table 2. The table relates to the digital power manager model number ZM7132
capable of supporting up to 32 POL converters. For other DPM models some of the registers and/or bits in the
registers are not available depending on the number of supported POLs/Groups/Interrupts/Parallel Buses for the
specific DPM. Writing into an unsupported register or bit will have no effect, reading from an unsupported register
or bit will return a zero.
Table 2. DPM Registers
Address Register
Content
Register
Type
User
Access Protect
Write
Initial Value
Base +
Name
0x00
0x04
0x08
0x0C
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x8F
0x90
0x1B
0x1C
0x1D
GAD[3:0]
GBD[3:0]
GCD[3:0]
GDD[3:0]
GAC
GBC
GCC
GDC
FPC1
FPC2
EPC
IC1
IC2
IBL
IBH
REL0
REL1
ID0
Group A Definition
Group B Definition
Group C Definition
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Run time
Run time
Run time
Run time
Run time
Run time
Run time
Run time
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Group D Definition
Group A Configuration
Group B Configuration
Group C Configuration
Group D Configuration
Fault Propagation Configuration 1
Fault Propagation Configuration 2
Error Propagation Configuration
Interrupt Configuration 1
Interrupt Configuration 2
IBV Low threshold
IBV high threshold
DPM Software Release Low Byte
DPM Software Release High Byte
DPM ID Low Byte
R
R
R
R/W
0xFF
0xFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ID1
ADDR
DPM ID High Byte
System Controller Address
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
0x1E
0x22
0x26
0x2A
0x2E
0x32
0x36
0x3A
0x3E
0x80
0x84
0x88
0x89
0x8A
0x8B
0x8C
0x8D
PB1[3:0]
PB2[3:0]
PB3[3:0]
PB4[3:0]
PB5[3:0]
PB6[3:0]
PB7[3:0]
PB8[3:0]
PID[31:0]
RTC[3:0]
PPS[3:0]
STA
Parallel Bus 1
Parallel Bus 2
Parallel Bus 3
Parallel Bus 4
Parallel Bus 5
Parallel Bus 6
Parallel Bus 7
Parallel Bus 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
POL Identification
Run Time Counter
POL Programming Status
Status of Group A
Status of Group B
Status of Group C
Status of Group D
DPM Status
N/A
value at last shutdown
(4x) 0x00
0x00
0x00
0x00
0x00
0x01
0x00
STB
STC
STD
IMS
EST
Event Status
Offset in Mon data where
last set was stored
0x15
0x91
0x8E
LCMDS
WP
Last Complete Monitoring Data Set Run time
Write Protection Volatile
R
R/W
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ZM7100 Series Digital Power Manager
Data Sheet
The static registers are saved in the non-volatile memory and used to store the system configuration data. The
run-time registers contain status information and are evaluated during run-time. Their content is saved to the non-
volatile memory together with monitoring data, but is not loaded into RAM when the DPM is powered up. The
Write Protection register WP is a volatile register that defaults to write protect at power-up.
9.1 POL Programming
Performance parameters of Z-series POL converters can be programmed via the I2C communication bus without
replacing any components or rewiring PCB traces. The POL programming data can be preloaded into DPMs by
Power-One or DPMs can be programmed by the user via the GUI and the I2C bus. The DPMs can be
programmed either before or after installation on a host board. The POL programming data (configuration
settings) is stored in non-volatile memory. Memory registers are listed in Table 3.
Table 3. POL Programming Memory
Address 1
Register 1
Content
Note
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
PC1_x
PC2_x
PC3_x
TC_x
INT_x
DON_x
DOF_x
VOS_x
CLS_x
DCL_x
B1_x
Protection Configuration 1
Protection Configuration 2
Protection Configuration 3
Tracking Configuration
Interleave Configuration and Frequency Selection
Turn-On Delay
Turn-Off Delay
Output Voltage Set-point
Current Limit Set-point
Duty Cycle Limit
Dig Controller Denominator z-1 Coefficient
Dig Controller Denominator z-2 Coefficient
Dig Controller Denominator z-3 Coefficient
Dig Controller Numerator z0 Coefficient Low Byte
Dig Controller Numerator z0 Coefficient High Byte
Dig Controller Numerator z-1 Coefficient Low Byte
Dig Controller Numerator z-1 Coefficient High Byte
Dig Controller Numerator z-2 Coefficient Low Byte
Dig Controller Numerator z-2 Coefficient High Byte
Dig Controller Numerator z-3 Coefficient Low Byte
Dig Controller Numerator z-3 Coefficient High Byte
reserved
2’s complement value
2’s complement value
2’s complement value
B2_x
B3_x
C0L_x
C0H_x
C1L_x
C1H_x
C2L_x
C2H_x
C3L_x
C3H_x
2’s complement value
2’s complement value
2’s complement value
2’s complement value
reserved
reserved
reserved
reserved
reserved
reserved
VOL_x 2
VOH_x 2
CRC0_x 2
CRC1_x 2
Output Voltage Margining Low Value
Output Voltage Margining High Value
Cyclic Redundancy Check Register 0
Cyclic Redundancy Check Register 1
1 x denotes the POL address
2 These registers are only used in the DPM and are not downloaded into POL converters during system programming
Refer to ZY7XXX data sheet for POL registers mapping and descriptions
Programming of POL converters is performed upon power-up, or when the Program Config… button is pressed in
the GUI System Configuration window shown in Figure 3, or when the high level command is sent directly via the
I2C bus.
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ZM7100 Series Digital Power Manager
Data Sheet
Figure 3. System Configuration Window
The programming is performed in several steps. Upon power-up, when the voltage on the IBV_S pin exceeds the
undervoltage protection threshold, the DPM uploads programming data from its static registers into RAM. Then
the DPM executes the cyclic redundancy check (CRC) to ensure integrity of the programming data. If the result is
OK, then the programming data stored in registers 00h through 14h of the DPM is sent to the respective POL
converter via the SD line. Every data transfer command is protected by parity check and followed by the POL
acknowledgement and read data back procedure. If both acknowledgement and readback operations are
successful, the POL converter is considered programmed, and the DPM continues with programming of the next
POL converter. It takes DPM approximately 15ms to program one POL.
Upon completion of the programming cycle, programming status information is recorded in the registers PPS0-
PPS3, and IMS shown in Figure 4 and Figure 5.
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ZM7100 Series Digital Power Manager
Data Sheet
Byte
PPS[3]
Base
PPS[2]
Base+1
PPS[1]
Base+2
PPS[0]
Base+3
Address
PPS
...
...
...
...
Figure 4. POL Programming Status Registers PPS0 and PPS1
R-0
ERR
Bit 7
R-0
R-0
R-0
SP
R-0
SD
R-0
R-0
CB
R-1
FE
FAULT
WAR
CRC
Bit 0
Bit 7
ERR: Error bit
0 = no error
1 = error occured
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
Bit 6
Bit 5
Bit 4
FAULT: Fault bit
0 = no error
1 = fault occured
- n = Value at POR reset
WAR: Warning bit
0 = no error
1 = warning occured
SP: System programmed successfully
0 = not all POLs are programmed
1 = all POLs were programmed successfully
Bit 31) SD: Transmission error on SD interface
0 = no error
1 = error occurred
Bit 21) CRC: CRC error after a memory check
0 = no error
1 = error occurred
Bit 1
Bit 0
CB: Crow-Bar (CB) output
0 = low
1 = high
FE: Front-End (FE) output
0 = low
1 = high
1) these bits are cleared when the register is read
Figure 5. DPM Status Register IMS
9.1.1
Write Protection
Figure 6 gives an overview of the different memory sections contained in the Z-One digital IBA system. A write
protection register WP in the DPM limits the write access to the memory blocks in the DPM and the POL
converters. The WP register content is defaulted to write protect upon powering up the DPM.
The write protection can be disabled by checking appropriate boxes in the Write Protections window shown in
Figure 7 or via the I2C bus by writing directly into the Write Protection Register WP shown in Figure 8. The write
protections are automatically restored when the DPM input power is recycled.
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ZM7100 Series Digital Power Manager
Data Sheet
POLs
DPM
Read
Write
I2C
SD Bus
POL
Registers
WP[3:2]
WP[5:4]
WP[1:0]
User
Memory
DPM
Registers
POL Setup
Registers
Monitoring
Data
FLASH
Figure 6. DPM Memory and Write Protection
Figure 7. Write Protections Window
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ZM7100 Series Digital Power Manager
Data Sheet
U
---
U
R/W-0
WP5
RW-1
WP4
RW-0
WP3
RW-1
WP2
RW-0
WP1
RW-1
WP0
Bit 0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
---
Bit 7
- n = Value at POR reset
Bit 7:6
: read as 0
Unimplemented
Bit 5:4 WP[5:4]: DPM configuration registers
00 = read only
01 = read only
10 = read and write
11 = read only
Bit 3:2
: Write commands to POL bypassing DPM
WP[3:2]
00 = read only
01 = read only
10 = read and write
11 = read only
Bit 1:0 WP[1:0]: POL setup registers
00 = read only
01 = read only
10 = read and write
11 = read only
Figure 8. Write Protection Register WP
9.2 POL Monitoring
Z-series POL converters can monitor own performance parameters such as output voltage, output current, and
temperature. Monitored parameters are stored in POL registers VOM, IOM, and TMON that are continuously
updated. If monitoring is enabled, the DPM will be continuously copying POL status and parametric data into
monitoring data registers. There are two blocks of POL monitoring memory as shown in Table 4. The first block
contains 32 bytes representing the status registers of all POL converters. The second block contains monitoring
data for each POL converter output voltage, output current, and temperature. For each parameter there is a ring
buffer of 10 most recent values (3x10 values times 32 POLs=960 Bytes).
Table 4. POL Monitoring Memory
Address
Register
Content
00h
01h
…
1Eh
1Fh
20h
30h
ST01)
Status Register POL0
Status Register POL1
ST11)
…
…
ST301)
ST311)
VO0[9:0]
VO1[9:0]
…
Status Register POL30
Status Register POL31
Ring buffer Output Voltage POL0
Ring buffer Output Voltage POL1
…
200h
210h
220h
220h
…
VO30[9:0]
VO31[9:0]
IO0[9:0]
IO1[9:0]
…
Ring buffer Output Voltage POL30
Ring buffer Output Voltage POL30
Ring buffer Output Current POL0
Ring buffer Output Current POL1
400h
410h
420h
430h
...
IO30[9:0]
IO31[9:0]
T0[9:0]
T1[9:0]
...
Ring buffer Output Current POL30
Ring buffer Output Current POL31
Ring buffer Temperature POL0
Ring buffer Temperature POL1
600h
610h
T15[9:0]
T31[9:0]
Ring buffer Temperature POL30
Ring buffer Temperature POL31
1) Initialized at BF at power-up
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ZM7100 Series Digital Power Manager
Data Sheet
Monitoring is enabled by checking the Retrieve Monitoring bits in the GUI Group Configuration window shown in
Figure 9 or directly via the I2C bus by writing into the respective Group Configuration Register GxC shown in
Figure 10. Update frequency is also programmable and can be set at 1 or 2Hz.
Figure 9. POL Group Configuration Window
R/W-0
TOC
Bit 7
U
U
R/W-0
NST
U
R/W-1
SMON
R/W-0
PMON
R/W-0
FRM
Bit 0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
---
---
---
- n = Value at POR reset
Bit 7
TOC: Turn-On Configuration
0 = Auto turn-on of group after POR
1 = Manual turn-on of group after POR
Bit 6:5 Unimplemented, read as ‘0’
Bit 4
NST: Notify user when STx changes
0 = Disables auto notification
1 = Enables auto notification
Bit 3
Bit 2
Unimplemented, read as ‘0’
SMON: Retrieve status monitoring data
0 = Disables auto retrieve of status monitoring data from the POLs
1 = Enables auto retrieve of status monitoring data from the POLs
Bit 1
Bit 0
PMON: Retrieve parametric monitoring data
0 = Disables auto retrieve of parametric monitoring data from the POLs
1 = Enables auto retrieve of parametric monitoring data from the POLs
FRM: Frequency of retrieving monitoring data
0 = 1Hz update frequency
1 = 2Hz update frequency
Figure 10. Group Configuration Registers GxC
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ZM7100 Series Digital Power Manager
Data Sheet
9.2.1
Ring Buffer
In the case of system failure (IBV_L, IBV_H, AC_FAIL, RES_N), the data for 10 monitoring cycles immediately
preceding the system shutdown is copied into the non-volatile ring buffer memory. After the system shutdown, the
ring buffer can be accessed either via the GUI or directly via the I2C bus using high and low level commands. The
data will be stored in the ring buffer until the next time the system is turned on therefore allowing for remote
diagnostics and troubleshooting. Once the data is written into the ring buffer it cannot be overwritten until the DPM
supply voltage is recycled or the ring buffer is cleared in GUI as shown in Figure 11 or directly via the I2C bus
using high and low level commands.
Contents of the ring buffer can be displayed in the GUI IBS Monitoring Window shown in Figure 12 or can be read
directly via the I2C bus using high and low level commands.
Figure 11. Monitoring Ring Buffer
9.2.2
Monitoring Setup
Retrieval of status and parametric monitoring data and update frequency are programmed in the GUI Group
Configuration window shown in Figure 9 or directly via the I2C bus by writing into the respective Group
Configuration Register GxC. Status and parametric monitoring data of a single POL regulator can be seen in the
GUI IBS Monitoring Window shown in Figure 12 or directly via the I2C bus using the low level Read Monitoring
Data command.
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ZM7100 Series Digital Power Manager
Data Sheet
9.2.3
Run Time Counter
The DPM also monitors the duration of time that it has been in operation. The 4 bytes Run Time Counter is active
whenever the DPM is powered up. The count rate is 1 second. New counter state is saved into non-volatile
memory at least once per day of continuous operation. Contents of the counter can be examined in the GUI IBS
Monitoring Window shown in Figure 12 or directly via the I2C bus using high and low level commands.
Figure 12. IBS Monitoring Window
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ZM7100 Series Digital Power Manager
Data Sheet
9.3 POL Group Management
Z-series POL converters can be arranged in up to four groups. A group of POL converters is defined as a number
of POL converters with interconnected OK pins. A group can include from 1 to 32 POL converters, but a POL
converter can be a member of only one group. In addition, the OK lines can be connected to the DPM to facilitate
propagation of faults and errors between groups. One DPM can manage up to four independent groups of POL
converters: A, B, C, and D, depending on the model.
Group management includes fault and error propagation, margining, turn-on and turn-off, monitoring setup, and
interrupt configuration.
9.3.1
Fault and Error Propagation
To enable fault and error propagation between groups, the respective bit needs to be checked in the GUI Fault
and Error Propagation window shown in Figure 13.
Figure 13. Fault and Error Propagation Window
The parameters can also be programmed directly via the I2C bus by writing into the FPC1, FPC2, and EPC
registers shown in Figure 14, Figure 15, and Figure 16, respectively.
When propagation is enabled, the faulty POL converter pulls its OK pin low. A low OK line initiates turn-off of
other POL converters in the group and signals the DPM to pull other OK lines low to initiate turn-off of other POL
converters as programmed.
Propagation of a fault (overcurrent, undervoltage, overtemperature, and tracking) between groups initiates regular
turn-off of other POL converters. The faulty POL converter in this case performs either the regular or the fast turn-
off depending on a specific fault.
Propagation of an error (overvoltage or phase voltage error) initiates fast turn-off of other POL converters. The
faulty POL converter performs the fast turn-off and turns on its low side switch. In addition, when an error is
propagated, the DPM can generate commands to turn off a front end (a DC-DC converter generating the
intermediate bus voltage) and trigger an optional crowbar protection to accelerate removal of the intermediate bus
voltage (IBV).
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ZM7100 Series Digital Power Manager
Data Sheet
R/W-0
FPBD
Bit 7
R/W-0
FPBC
U
R/W-0
FPBA
R/W-0
FPAD
R/W-0
FPAC
R/W-0
FPAB
U
---
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
---
Bit 0
- n = Value at POR reset
Bit 7
FPBD: Fault propagation from Group B to Group D
0 = disabled
1 = enabled
Bit 6
FPBC: Fault propagation from Group B to Group C
0 = disabled
1 = enabled
Bit 5
Bit 4
Unimplemented: read as ‘0’
FPBA: Fault propagation from Group B to Group A
0 = disabled
1 = enabled
Bit 3
Bit 2
FPAD: Fault propagation from Group A to Group D
0 = disabled
1 = enabled
FPAC: Fault propagation from Group A to Group C
0 = disabled
1 = enabled
Bit 1
Bit 0
FPAB: Fault propagation from Group A to Group B
0 = disabled
1 = enabled
Unimplemented: read as ‘0’
Figure 14. Fault Propagation Configuration Register FPC1
U
R/W-0
FPDC
R/W-0
FPDB
R/W-0
FPDA
R/W-0
FPCD
U
R/W-0
FPCB
R/W-0
FPCA
Bit 0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
---
---
Bit 7
- n = Value at POR reset
Bit 7
Unimplemented: read as ‘0’
Bit 6
Bit 5
Bit 4
Bit 3
FPDC: Fault propagation from Group D to Group C
0 = disabled
1 = enabled
FPDB: Fault propagation from Group D to Group B
0 = disabled
1 = enabled
FPDA: Fault propagation from Group D to Group A
0 = disabled
1 = enabled
FPCD: Fault propagation from Group C to Group D
0 = disabled
1 = enabled
Bit 2
Bit 1
Unimplemented: read as ‘0’
FPCB: Fault propagation from Group C to Group B
0 = disabled
1 = enabled
Bit 0
FPCA: Fault propagation from Group C to Group A
0 = disabled
1 = enabled
Figure 15. Fault Propagation Register FPC2
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ZM7100 Series Digital Power Manager
Data Sheet
R/W-0
EPB1
R/W-0
EPD1
Bit 7
R/W-0
EPD0
R/W-0
EPC1
R/W-0
EPC0
R/W-0
EPB0
R/W-0
EPA1
R/W-0
EPA0
Bit 0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 7:6 EPD[1:0]: Error propagation from Group D
00 = none
01 = disable Front-End (set FE_EN low)
10 = disable Front-End and trigger Crow-Bar (FE_EN low, CB high)
11 = none
Bit 5:4 EPC[1:0]: Error propagation from Group C
00 = none
01 = disable Front-End (set FE_EN low)
10 = disable Front-End and trigger Crow-Bar (FE_EN low, CB high)
11 = none
Bit 3:2 EPB[1:0]: Error propagation from Group B
00 = none
01 = disable Front-End (set FE_EN low)
10 = disable Front-End and trigger Crow-Bar (FE_EN low, CB high)
11 = none
Bit 1:0 EPA[1:0]: Error propagation from Group A
00 = none
01 = disable Front-End (set FE_EN low)
10 = disable Front-End and trigger Crow-Bar (FE_EN low, CB high)
11 = none
Figure 16. Error Propagation Register EPC
Group status information is stored in the Group Status Registers STA, STB, STC, and STD shown in Figure 17.
R-0
OC
R-0
PT
R-0
PG
R-0
R-0
OT
R-0
UV
R-0
OV
R-0
PC
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
TRK
Bit 7
Bit 0
- n = Value at POR reset
Classification
Warning
Warning
Fault
Bit 7
PT: Pre-warning Temperature
PG: Power Good Warning
TR: Tracking Fault
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
OT: Temperature Fault
OC: Over Current Fault
UV: Under Voltage Fault
OV: Over Voltage Fault
PV: Phase Voltage Fault
Fault
Fault
Fault
Error
Error
- A fault shall be encoded as ‘0’
Figure 17. Group Status Reference Registers STx
9.3.2
Margining
Margining can be executed separately for each group by clicking an appropriate radio button in the GUI IBS
monitoring window or directly via the I2C bus by high level commands.
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ZM7100 Series Digital Power Manager
Data Sheet
9.3.3
Turn-ON and Turn-Off commands
Automatic turn–on upon application of the input voltage is enabled by checking the Auto Turn-On bit in the GUI
Group Configuration window shown in Figure 9 or directly via the I2C bus by writing into the respective Group
Configuration Register GxC register shown in Figure 10.
Turn-on and turn-off of various groups during the operation is controlled from the GUI IBS Monitoring window or
directly via the I2C bus by high level commands. If the commands are used, POL converters will turn on and off
according to their tracking and sequencing settings. If the Emergency Turn Off command is used the POL
converters will perform the fast turn-off. In this case, the POL converters will immediately turn off both switches
and output voltages will decay depending on load parameters.
9.3.4
Interrupt Configurations
The DPM has four interrupt inputs that allow temporary turn-off of POL groups by pulling the interrupts inputs low.
The interrupts are enabled in the GUI Interrupt Configuration window shown in Figure 18 or directly via the I2C bus
by writing into the Interrupt Configuration registers IC1 and IC2 shown in Figure 19.
Figure 18. Interrupt Configuration Window
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ZM7100 Series Digital Power Manager
Data Sheet
R/W-0
I2D
R/W-0
I2C
R/W-1
I2B
R/W-0
I2A
R/W-0
I1D
R/W-0
I1C
R/W-0
I1B
R/W-1
I1A
R/W-1
I4D
R/W-0
I4C
R/W-0
I4B
R/W-0
I4A
R/W-0
I3D
R/W-1
I3C
R/W-0
I3B
R/W-0
I3A
Bit 7
Bit 0
Bit 7
Bit 0
Bit 7
I1D: Interrupt 1 propagation to Group D
0 = disabled
1 = enabled
Bit 7
I3D: Interrupt 3 propagation to Group D
0 = disabled
1 = enabled
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I1C: interrupt 1 propagation to Group C
0 = disabled
1 = enabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I3C: interrupt 3 propagation to Group C
0 = disabled
1 = enabled
- n = Value at POR reset
- n = Value at POR reset
I1B: interrupt 1 propagation Group B
0 = disabled
1 = enabled
I3B: interrupt 3 propagation Group B
0 = disabled
1 = enabled
I1A: Interrupt 1 propagation Group A
0 = disabled
1 = enabled
I3A: Interrupt 3 propagation Group A
0 = disabled
1 = enabled
I0D: Interrupt 0 propagation to Group D
0 = disabled
1 = enabled
I2D: Interrupt 2 propagation to Group D
0 = disabled
1 = enabled
I0C: interrupt 0 propagation to Group C
0 = disabled
1 = enabled
I2C: interrupt 2 propagation to Group C
0 = disabled
1 = enabled
I0B: interrupt 0 propagation Group B
0 = disabled
1 = enabled
I2B: interrupt 2 propagation Group B
0 = disabled
1 = enabled
I0A: Interrupt 0 propagation Group A
0 = disabled
I2A: Interrupt 2 propagation Group A
0 = disabled
1 = enabled
1 = enabled
Figure 19. Interrupt Configuration Registers IC1 (left) and IC2
9.4 Protections
The DPM provides undervoltage and overvoltage protections for the intermediate voltage bus, support error
protection by controlling a front end and a crowbar circuit, and perform controlled system shutdown in case of the
main AC-DC failure.
9.4.1
Intermediate Voltage Bus Protections
The DPM continuously monitors the intermediate bus voltage via the IBV_S input. Thresholds of IBV protections
are programmed in the GUI Intermediate Bus Configuration Window shown in Figure 20 or directly via the I2C bus
by writing into the IBV Low Threshold and High Threshold IBH registers IBL and IBV shown in Figure 21.
Figure 20. Intermediate Bus Configuration Window
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ZM7100 Series Digital Power Manager
Data Sheet
W/R-0
IBL7
W/R-0
IBL6
W/R-0
IBL5
W/R-0
IBL4
W/R-0
IBL3
W/R-0
IBL2
W/R-0
IBL1
W/R-0
IBL0
W/R-1
IBH7
Bit 7
W/R-1
IBH6
W/R-1
IBH5
W/R-1
IBH4
W/R-1
IBH3
W/R-1
IBH2
W/R-1
IBH1
W/R-1
IBH0
Bit 0
Bit 7
Bit 0
Bit 7:0 IBL[7:0]: IBV low threshold
00h = 0
Bit 7:0 IBH[7:0]: IBV high threshold
00h = 0
01h = 1/256 of full scale voltage
02h = 2/256 of full scale voltage
ꢀ
FEh = 254/256 of full scale voltage
FFh = 255/256 of full scale voltage
01h = 1/256 of full scale voltage
02h = 2/256 of full scale voltage
ꢀ
FEh = 254/256 of full scale voltage
FFh = 255/256 of full scale voltage
Full Scale = 14.19V
Full scale = 14.19V
Figure 21. IBV Low Threshold Register IBL (left) and IBV High Threshold Register IBH
When the IBV decreases below the IBV Low Threshold, the DPM will pull all OK lines low turning off all POL
converters. The POL converters will enter regular turn-off sequence. Contents of the Ring Buffer will be saved in
non-volatile memory. When the IBV recovers, the DPM will first reprogram all POL converters and then turn them
on, if the Auto Turn On is enabled in the GUI POL Group Configuration Window.
When the IBV exceeds the IBV High Threshold, the DPM will pull all OK lines low turning off all POL converters.
The POL converters will enter regular turn-off sequence. Contents of the Ring Buffer will be saved in non-volatile
memory. After a delay (typically 50ms), the DPM will turn off the front end. If the voltage does not decrease below
the threshold within the next 50ms, the DPM will trigger the crowbar protection. One second after clearing the IBV
High fault, the DPM will attempt to turn on the front end. If the IBV is within limits, the DPM will reprogram all POL
converters and then turn them on, if the Auto Turn On is enabled in the GUI POL Group Configuration Window.
9.4.2
AC_Fail Protection
The AC_Fail signal is generated by a main AC-DC source supplying 48V backplane voltage that in turn powers the
DC-DC Front End. Whenever the AC voltage disappears, the AC-Fail signal will be set low. If there is no battery
backup, it means the 48V will disappear after 20ms. When DPM receives the AC_Fail signal, it will pull all OK
lines low, turning off all POL converters. The POL converters will enter regular turn-off sequence. Contents of the
Ring Buffer will be saved in non-volatile memory. When the AC voltage recovers and the AC_Fail goes high, the
DPM will reprogram all POL converters and then turn them on, if the Auto Turn On is enabled in the GUI POL
Group Configuration Window.
9.5 Controls
9.5.1
Front End Enable
The FE_EN pin is dedicated to the control of a DC-DC Front End. The Front End is typically used to convert the
48V into the intermediate bus voltage. If the DPM is powered from an auxiliary source, not from the IBV, it can
control the Front End.
When FE_EN is internally pulled up to 3V, the Front End is enabled. The FE_EN output can provide up to 10mA
of current. When the FE_EN goes below 0.5V, the Front End is disabled. The Front End can be enabled and
disabled via the GUI IBS Monitoring Window or directly via the I2C bus using high and low level commands.
The FE_EN pin should not be directly connected to the Front End Enable pin. Typically, the Enable pin is
referenced to the primary side of the Front End that is isolated from low voltage secondary side. In addition, the
Enable pin can be pulled up internally to a voltage potentially damaging to the DPM FE_EN output. The best
method is to interface the DPM with the Front End through an optocoupler as shown in Figure 22. This
configuration provides interface for negative logic front ends. The 3.3k resistor was added between the FE_EN
pin and the ground to avoid a glitch during application of input voltage to the DPM.
REV. 3.0 JAN 04, 2006
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Page 24 of 29
ZM7100 Series Digital Power Manager
Data Sheet
Front End
DPM
FE_EN
R
Enable
Q
3.3k
-VIN
GND
Figure 22. Interface Between DPM and Front End
9.5.2
Crowbar Enable
When the crowbar protection is enabled, the CB pin goes to 3V for 1ms. It is capable of supplying 10mA to turn
on a crowbar circuit.
9.5.3
RES_N
If the RES_N pin is pulled low, the DPM will pull all OK lines low, turning off all POL converters. The POL
converters will enter regular turn-off sequence. Contents of the Ring Buffer will be saved in non-volatile memory.
Releasing the RES_N will first reprogram all POL converters and then turn them on, if the Auto Turn-On is enabled
in the GUI POL Group Configuration Window.
9.6 User Memory
This non-volatile memory block is reserved for users’ notes and it is not related to other functions in the DPM. It
can be used to save application information such as manufacturing data and location, application code,
configuration file version, etc. A total of 1024 Bytes of user memory is provided. The user memory can be
accessed via the GUI System Configuration window shown in Figure 3, or directly via the I2C bus using high and
low level commands.
Figure 23. User Memory Window
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Page 25 of 29
ZM7100 Series Digital Power Manager
Data Sheet
10. Application Information
10.1 Powering the DPM
The DPM can be powered directly from the intermediate voltage bus (IBV) or from an auxiliary source such as a
housekeeping, standby, or backplane supply. In applications where the DPM is used to control the front end
generating IBV and/or the crowbar, the DPM must be powered from an auxiliary source.
If the intermediate bus voltage exceeds 4.0V, the DPM can be powered directly from the IBV via Pin 23.
Schematic in Figure 24 shows power connections when the DPM input voltage is supplied directly by IBV. A low-
pass RC-filter is added to increase noise immunity of the voltage sense line.
100
Pin 10
IBV_S
DPM
4.7uF
Pin 25
3V3
LDO
IBV=4.0...14V
Pin 23
IBV
22uF
Pin 24
GND
POLs
Input Voltage
Figure 24. Power Connections for IBV>4.0V
If the DPM is powered by an auxiliary source higher than 4.0V, the IBV voltage range can be extended to 3.0 to
14V as shown in Figure 25.
IBV=3.0...14V
100
Pin 10
IBV_S
DPM
4.7uF
22uF
Pin 25
3V3
POLs
Input Voltage
LDO
Pin 23
IBV
4.0...14V
DPM
Auxiliary
Supply
Pin 24
GND
Figure 25. Power Connections For Application With Auxiliary Source Higher Than 4.0V
REV. 3.0 JAN 04, 2006
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Page 26 of 29
ZM7100 Series Digital Power Manager
Data Sheet
In applications where the DPM is powered from a 3.3V auxiliary supply, the schematic in Figure 25 needs to be
modified by adding a jumper between Pin 23 and Pin 25 as shown in Figure 26. This effectively shorts the internal
linear regulator and applies the voltage directly to the DPM ASICs. It is user’s responsibility to ensure the voltage
on Pin 25 never exceeds specified limits.
IBV=3.0...14V
100
Pin 10
IBV_S
DPM
4.7uF
Pin 25
3V3
POLs
LDO
Input Voltage
Pin 23
IBV
3.3V DPM
Auxiliary
Supply
22uF
Pin 24
GND
Figure 26. Power Connections For Application With 3.3V Auxiliary Source
In applications where the intermediate voltage bus is 3.3V, both the DPM and POL converters can be powered
directly from the IBV as shown in Figure 27.
Pin 10
IBV_S
DPM
100
4.7uF
Pin 25
3V3
LDO
Pin 23
IBV
IBV=3.0...3.6V
22uF
Pin 24
GND
POLs
Input Voltage
Figure 27. Power Connections for IBV=3.3V
REV. 3.0 JAN 04, 2006
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Page 27 of 29
ZM7100 Series Digital Power Manager
Data Sheet
11. Mechanical Drawings
All Dimensions are in mm
Tolerances:
0.5-10 ±0.1
10-100 ±0.2
14±0.3
Pin 1
0.4
1.27
10
2.54
8
0.5
0.1
Z-Axis
6.25±0.3
2.3
Figure 28. ZM7100 Mechanical Drawing – Top View
Figure 29. ZM7100 Mechanical Drawing – Bottom View
REV. 3.0 JAN 04, 2006
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Page 28 of 29
ZM7100 Series Digital Power Manager
Data Sheet
8.6
32
3
6
10
10
(x 3)
1.4
1.1
0.1
0.1
16.9
Top View
14.2
0.8
1
2.4
2.03
1.27
2.54
(x 22)
Figure 30. Recommended PCB Pad Sizes
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical
components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written
consent of the respective divisional president of Power-One, Inc
2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
I2C is a trademark of Philips Corporation.
REV. 3.0 JAN 04, 2006
www.power-one.com
Page 29 of 29
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