ZY8160-Q1 [BEL]
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, PACKAGE-24;
| 型号： | ZY8160-Q1 |
| 厂家： | 
BEL FUSE INC. |
| 描述： | DC-DC Regulated Power Supply Module, 1 Output, Hybrid, PACKAGE-24 |
| 文件： | 总29页 (文件大小：1114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Member of the
Family
Features
•
RoHS lead free and lead-solder-exempt products are
available
•
•
•
•
•
•
Wide input voltage range: 8V–14V
High continuous output current: 60A
Programmable output voltage range: 0.5V–2.75V
Efficiency greater than 92%
Active digital current share
Single-wire serial communication bus for frequency
synchronization, programming, and monitoring
•
•
•
Real time voltage, current, and temperature
measurements, monitoring, and reporting
Optimal voltage positioning with programmable slope
of the VI line
Applications
•
Low voltage, high density systems with
Intermediate Bus Architectures (IBA)
Overcurrent, overvoltage, undervoltage, and
overtemperature protections with programmable
thresholds and types
•
Point-of-load regulators for high performance
DSP, FPGA, ASIC, and microprocessors
•
•
•
Programmable fixed switching frequency 0.5-1.0MHz
Programmable turn-on and turn-off delays
•
•
Desktops, servers, and portable computing
Broadband, networking, optical, and
communications systems
Programmable turn-on and turn-off voltage slew rates
with tracking protection
•
•
•
•
•
•
Programmable feedback loop compensation
Power Good signal with programmable limits
Programmable fault management
Benefits
•
•
•
Integrates digital power conversion with
intelligent power management
Start up into the load pre-biased up to 100%
Current sink capability
Eliminates the need for external power
management components
Industry standard size through-hole single-in-line
package: 2.4”x0.55”
Completely programmable via industry-standard
I2C communication bus
•
•
•
Low height of 1.1”
•
•
One part that covers all applications
Wide operating temperature range: 0 to 70ºC
Reduces board space, system cost and
complexity, and time to market
UL 60950-1/CSA 22.2 No. 60950-1-07 Second
Edition, IEC 60950-1: 2005, and EN 60950-1:2006
Description
Power-One’s point-of-load converters are recommended for use with regulated bus converters in an Intermediate
Bus Architecture (IBA). The ZY8160 is an intelligent, fully programmable multiphase step-down point-of-load DC-
DC module integrating digital power conversion and intelligent power management. When used with ZM7300
Series Digital Power Managers, the ZY8160 completely eliminates the need for external components for
sequencing, tracking, protection, monitoring, and reporting. All parameters of the ZY8160 are programmable via
the industry-standard I2C communication bus and can be changed by a user at any time during product
development and service.
Reference Documents:
•
•
•
•
ZM7300G Series Digital Power Manager. Data Sheet
ZM7300 Digital Power Manager Programming Manual
Power-One I2C Graphical User Interface Program
ZM00056-KIT USB to I2C Adapter Kit. User Manual
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 1 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
1. Ordering Information
ZY
81
60
y
–
zz
RoHS compliance:
Product
family:
Z-One
Series:
Server Class
Intelligent POL
Converter
Packaging Option2:
R1 – 30 pc Tray
Q1 – 1 pc sample for
evaluation only
Output
Current:
60A
No suffix - RoHS compliant
with Pb solder exemption1
G - RoHS compliant for all
six substances
Dash
Module
______________________________________
1
The solder exemption refers to all the restricted materials except lead in solder. These materials are Cadmium (Cd), Hexavalent chromium
(Cr6+), Mercury (Hg), Polybrominated biphenyls (PBB), Polybrominated diphenylethers (PBDE), and Lead (Pb) used anywhere except in
solder.
2
Packaging option is used only for ordering and not included in the part number printed on the POL converter label.
3
Z-One evaluation board is available in only one configuration: ZM7300-KIT-HKS.
Example: ZY8160G-R1: A 30-piece tray of RoHS compliant POL converters. Each POL converter is labeled
ZY8160G.
2. Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-
term reliability, and cause permanent damage to the converter.
Parameter
Operating Temperature
Input Voltage
Conditions/Description
Controller case temperature
250ms Transient
Min
Max
100
15
Units
°C
0
VDC
3. Environmental and Mechanical Specifications
Parameter
Ambient Temperature Range
Storage Temperature (Ts)
Weight
Conditions/Description
Min
Nom
Max
70
Units
0
°C
°C
-55
125
33
grams
Frequency Range
Magnitude
Sweep Rate
Repetitions in each axis (Min-Max-Min Sweep)
5
0.5
1
500
Hz
G
oct/min
sweeps
G
Operating Vibration
(sinusoidal)
2
Acceleration
Duration
Number of shocks in each axis
50
11
10
Non-Operating Shock
(half sine)
ms
MTBF
Calculated Per Telcordia Technologies SR-332
18.5
MHrs
°C
Peak Reflow Temperature
Peak Reflow Temperature
Lead Plating
ZY8160
ZY8160G
220
260
245
°C
ZY8160 and ZY8160G
100% Matte Tin
Moisture Sensitivity Level
per JEDEC J-STD-020C
ZY8160
ZY8160G
2
3
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 2 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
4. Electrical Specifications
Specifications apply at the input voltage from 8V to 14V, output load from 0 to 60A, ambient temperature from 0°C
to 70°C, output capacitance consisting of 110µF ceramic and 220µF tantalum, and default performance
parameters settings unless otherwise noted.
4.1
Input Specifications
Parameter
Conditions/Description
Refer to Figure 1
VIN=12V
Min
Nom
Max
Units
VDC
Input voltage (VIN)
8
14
Input Current (at no load)
Maximum Input Current
29
mADC
ADC
VIN=8V, VOUT=2.1V
17.5
4.2
Output Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
Programmable1
Default (no programming)
0.5
2.75
VDC
VDC
Output Voltage Range (VOUT
)
0.5
VIN=12V, IOUT=0.5*IOUT MAX
FSW=500kHz, room temperature
,
±1.2% or 10mV whichever is
greater
Output Voltage Setpoint Accuracy
%VO.SET
Output Current (IOUT
Line Regulation
)
VIN MIN to VIN MAX
VIN MIN to VIN MAX
0 to IOUT MAX
-402
60
ADC
±0.5
±0.5
%VOUT
%VOUT
Load Regulation
Dynamic Regulation
Peak Deviation
Settling Time
50% - 75% load step, Slew rate 1A/µs
COUT=660µF, FSW=1MHz
mV
µs
100
35
to 10% of peak deviation
Output Voltage Peak-to-Peak
Ripple and Noise
BW=20MHz
VIN=12V, VOUT=0.75V
VIN=12V, VOUT=1.0V
VIN=12V, VOUT=1.8V
VIN=12V, VOUT=2.5V
15
20
25
30
mV
mV
mV
mV
Full Load
VIN=12V, VOUT=0.5V
VIN=12V, VOUT=0.75V
VIN=12V, VOUT=1.0V
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=1.5V
VIN=12V, VOUT=1.8V
VIN=12V, VOUT=2.5V
78.8
82.3
85.5
87.4
89.3
90.6
92.5
%
%
%
%
%
%
%
Efficiency
FSW=500kHz
Full Load
Room temperature
Temperature Coefficient
VIN=12V, VOUT =2.5V, IOUT=0.5*IOUT MAX
50
ppm/°C
Switching Frequency
(3 phases combined)
Default
500
kHz
kHz
Programmable, 250kHz steps
500
0
1,000
33
Default
Programmable, 0.5% steps
33
%
%
Duty Cycle
1
2
ZY8160 is a step-down converter, thus the output voltage is always lower than the input voltage as show in Figure 1.
At the negative output current (bus terminator mode) efficiency of the ZY8160 degrades resulting in increased internal power dissipation.
Therefore maximum allowable negative current is limited to 40A.
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 3 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Vo
[V]
3.0
2.75
2.5
2.1
2.0
1.5
1.0
0.5
9.6
10.5
11.0
8.0
9.0
10.0
12.0
13.0
14.0
Vi [V]
Figure 1. Output Voltage as a Function of Input Voltage
4.3
Protection Specifications
Parameter
Conditions/Description
Output Overcurrent Protection
Min
Nom
Max
Units
Default
Programmable
Non-Latching, 130ms period
Latching/Non-Latching
Type
Default
Programmable in 11 steps
140
140
%IOUT
%IOUT
Threshold
40
Threshold Accuracy
-25
25
%IOCP.SET
Output Overvoltage Protection
Default
Programmable
Non-Latching, 130ms period
Latching/Non-Latching
Type
Default
Programmable in 10% steps
130
%VO.SET
%VO.SET
Threshold
1101
-2
130
2
Threshold Accuracy
Measured at VO.SET=2.5V
%VOVP.SET
From instant when threshold is exceeded until
the turn-off command is generated
Delay
6
μs
ZD-01674 Rev. 1.5, 5-May-2011
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Page 4 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Output Undervoltage Protection
Default
Programmable
Non-Latching, 130ms period
Latching/Non-Latching
Type
Default
Programmable in 5% steps
75
%VO.SET
%VO.SET
Threshold
Threshold Accuracy
Delay
75
-2
90
2
Measured at VO.SET=2.5V
%VUVP.SET
From instant when threshold is exceeded until
the turn-off command is generated
6
μs
Overtemperature Protection
Default
Programmable
Non-Latching, 130ms period
Latching/Non-Latching
Type
Turn Off Threshold
Turn On Threshold
Threshold Accuracy
Temperature is increasing
120
110
5
°C
°C
°C
Temperature is decreasing after the module was
shut down by OTP
-5
From instant when the controller junction
temperature reaches the OTP threshold until the
turn-off command is generated
Delay
2
ms
Tracking Protection (when Enabled)
Default
Programmable
Disabled
Type
Latching/Non-Latching, 130ms period
Threshold
Enabled during output voltage ramping up
mVDC
±250
Threshold Accuracy
-50
50
mVDC
From instant when threshold is exceeded until
the turn-off command is generated
Delay
6
μs
Overtemperature Warning
Threshold
Threshold Accuracy
Hysteresis
Always enabled, reported in Status register
120
°C
°C
°C
-5
5
3
6
From instant when threshold is exceeded until
the warning signal is generated
Delay
μs
Power Good Signal (PGOOD pin)
VOUT is inside the PG window
VOUT is outside the PG window
High
Low
Logic
N/A
Default
Programmable in 5% steps
90
%VO.SET
%VO.SET
Lower Threshold
Upper Threshold
Delay
90
-2
95
2
110
6
%VO.SET
μs
From instant when threshold is exceeded until
status of PG signal changes
Threshold Accuracy
Measured at VO.SET=2.5V
%VO.SET
___________________
1
Minimum OVP threshold is 1.0V
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 5 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
4.4
Feature Specifications
Parameter
Conditions/Description
Current Share
Min
Nom
Max
Units
Type
Active, Single Line
±20
Current Share Accuracy
IOUT MIN≥20%*IOUT NOM
%IOUT
Interleave
Default
0
Degree
degree
Interleave (Phase Shift)
0
348.75
Programmable in 11.25° steps
Sequencing
Default
Programmable in 1ms steps
Default
Programmable in 1ms steps
0
ms
ms
ms
ms
Turn ON Delay
Turn OFF Delay
0
0
255
0
63
Tracking
Default
Programmable in 7 steps
Default
Programmable in 7 steps
0.1
V/ms
V/ms
V/ms
V/ms
Turn ON Slew Rate
Turn OFF Slew Rate
0.1
8.331
-0.1
-0.1
-8.331
Optimal Voltage Positioning
Default
Programmable in 7 steps
0
mV/A
mV/A
Load Regulation
0
1.3
Feedback Loop Compensation
Zero1 (Effects phase lead and
increases gain in mid-band)
Zero 2 (Effects phase lead and
increases gain in mid-band)
Pole 1 (Integrator Pole, effects
loop gain)
Pole 2 (Effects phase lag and
limits gain in mid-band)
Pole 3 (High frequency low- pass
filter to limit PWM noise)
Programmable
0.05
0.05
0.05
1
50
50
kHz
kHz
kHz
kHz
kHz
Programmable
Programmable
Programmable
50
1000
1000
Programmable
Monitoring
1
-1%VOUT
– 1 LSB
1%VOUT
+ 1 LSB
Voltage Monitoring Accuracy
Current Monitoring Accuracy
1 LSB=22mV
mV
20%IOUT NOM <IOUT≤IOUT NOM
20
20
+5
%IOUT
Temperature Monitoring Accuracy Junction temperature of POL controller
-5
°C
Remote Voltage Sense (+VS and –VS pins)2
Voltage Drop Compensation
Voltage Drop Compensation
Between +VS and VOUT
300
100
mV
mV
Between -VS and PGND
___________________
1
Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment
2
If the voltage sense outputs are connected remotely, it is recommended to place a 0.01-0.1μF ceramic capacitor between +VS and –VS pins
as close to the POL converter as possible. The capacitor improves noise immunity of the POL converter.
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 6 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
4.5
Signal Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
VDD
Internal supply voltage
3.15
3.3
3.45
V
SYNC/DATA Line (SD pin)
ViL_sd
ViH_sd
LOW level input voltage
HIGH level input voltage
-0.5
0.3 x VDD
VDD + 0.5
V
V
0.75 x
VDD
0.25 x
VDD
0.45 x
VDD
Vhyst_sd
Hysteresis of input Schmitt trigger
V
VoL
Tr_sd
LOW level sink current @ 0.5V
Maximum allowed rise time 10/90%VDD
Added node capacitance
14
60
300
10
mA
ns
Cnode_sd
Ipu_sd
5
pF
Pull-up current source at Vsd=0V
Clock frequency of external SD line
0.3
1.0
525
mA
kHz
Freq_sd
475
% of clock
cycle
% of clock
cycle
Tsynq
T0
Sync pulse duration
22
72
28
78
Data=0 pulse duration
ADDR0…ADDR4 Inputs
LOW level input voltage
ViL_x
ViH_x
-0.5
0.3 x VDD
VDD+0.5
0.3 x VDD
V
V
V
HIGH level input voltage
0.7 x VDD
0.1 x VDD
Vhyst_x
Hysteresis of input Schmitt trigger
External pull down resistance
ADDRX forced low
RdnL_ADDR
10
kOhm
Power Good and OK Inputs/Outputs
Iup_PG
Iup_OK
ViL_x
Pull-up current source input forced low PG
Pull-up current source input forced low OK
25
110
725
μA
μA
V
175
-0.5
LOW level input voltage
HIGH level input voltage
0.3 x VDD
VDD+0.5
0.3 x VDD
20
ViH_x
Vhyst_x
IoL
0.7 x VDD
0.1 x VDD
4
V
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
V
mA
Current Share Bus (CS pin)
Iup_CS
ViL_CS
Pull-up current source at VCS = 0V
LOW level input voltage
0.84
-0.5
3.1
mA
V
0.3 x VDD
0.75 x
VDD
0.25 x
VDD
ViH_CS
HIGH level input voltage
VDD+0.5
V
V
0.45 x
VDD
Vhyst_CS
Hysteresis of input Schmitt trigger
IoL
LOW level sink current at 0.5V
14
60
mA
ns
Tr_CS
Maximum allowed rise time 10/90% VDD
100
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 7 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
5. Typical Performance Characteristics
95
90
85
80
5.1
Efficiency Curves
95
90
85
80
75
Vin=9.6V
Vin=12V
2
Vo=0.75V
Vo=1.8V
Vo=1.0V
Vo=2.5V
Vo=1.2V
50
75
0.5
1
1.5
Output Voltage, V
2.5
0
10
20
30
Output Current, A
40
60
Figure 4. Efficiency vs. Output Voltage, Iout=60A,
Fsw=500kHz
Figure 2. Efficiency vs. Load. Vin=9.6V, Fsw=500kHz
95
90
85
80
75
95
90
85
80
75
Vo=0.5V
Vo=1.8V
Vo=2.5V
Vo=0.75V
Vo=1.8V
Vo=1.0V
Vo=2.5V
Vo=1.2V
8
9
10
11
12
13
14
Input Voltage, V
0
10
20
30
Output Current, A
40
50
60
Figure 5. Efficiency vs. Input Voltage. Iout=60A, Fsw=500kHz
Figure 3. Efficiency vs. Load. Vin=12V, Fsw=500kHz
ZD-01674 Rev. 1.5, 5-May-2011
www.power-one.com
Page 8 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
94
92
90
88
86
84
82
Vo=1V
Vo=1.8V
Vo=2.5V
500
750
1000
Switching Frequency, kHz
Figure 8. Turn-On with Different Rising Slew Rates.
Rising Slew Rates are Programmed as follows: V1-
and V2-0.5V/ms, V3-0.2V/ms.
Figure 6. Efficiency vs. Switching Frequency. Vin=12V,
Iout=60A
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
5.2
Turn-On Characteristics
Figure 9. Turn On with Sequencing and Tracking. Rising Slew
Rate Programmed at 0.5V/ms, V1 and V2 delays are
programmed at 5ms.
Figure 7. Tracking Turn-On. Rising Slew Rate is
Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
ZD-01674 Rev. 1.5, 5-May-2011
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Page 9 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Figure 10. Turn On into Prebiased Load. V1 and V2 are
Prebiased by V3 via a Diode.
Figure 12. Turn-Off with Tracking and Sequencing. Falling
Slew Rate is Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
5.3
Turn-Off Characteristics
5.4
Transient Response
The picture below shows the deviation of the output
voltage in response to the 50-75-50% step load at
1A/μs. In all tests the ZY8160 converters had the
switching frequency of 1MHz and a total of 660μF
ceramic and tantalum capacitors connected across
the output pins. Bandwidth of the feedback loop was
programmed for faster transient response.
Figure 11. Tracking Turn-Off. Falling Slew Rate is
Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Figure 13. Vin=12V, Vout=1.8V
ZD-01674 Rev. 1.5, 5-May-2011
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Page 10 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
5.5
Thermal Derating Curves
60
50
40
30
0 LFM
100 LFM (0.5 m/s)
200 LFM (1 m/s)
300 LFM (1.5 m/s)
400 LFM (2 m/s)
500 LFM (2.5 m/s)
20
25
35
45
55
65
75
Ambient Temperature, C
Figure 14. Thermal Derating Curves. Vin=12V, Vout=2.5V, Fsw=500kHz
60
50
40
30
20
0 LFM
100 LFM (0.5 m/s)
200 LFM (1 m/s)
300 LFM (1.5 m/s)
400 LFM (2 m/s)
500 LFM (2.5 m/s)
25
35
45
Ambient Temperature, C
Figure 15. Thermal Derating Curves. Vin=12V, Vout=2.5V, Fsw=1,000kHz
55
65
75
ZD-01674 Rev. 1.5, 5-May-2011
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Page 11 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
6. Typical Application
Intermediate Voltage Bus
IBV
100n 100n 100n 100n
+3.3V
6
25 42 57 60
47k
VDD VDD VDD VDD VDD
48
44
23
17
IBVS
AREF
CB
FE_EN
R4
R3
10n
10k
10n
56
SD
Connect to other
Z-One® POL
Converters
30
27
53
20
13
11
SDA
SCL
OKD
OKC
OKB
OKA
SDA
SCL
Connect CS pin to
other ZY8160 to
enable current share
45
46
47
ADDR2
ADDR1
ADDR0
Low ESR Ceramic
Tantalum Capacitors
Are Not Required, If
Inductance Of Input
Source <0.1µH
Capacitors To Keep
The Input Voltage
Ripple ≤2% Of VIN
4
6
3
5
PG
CS
OK
SD
12
13
VIN
VIN
36 INT3_N
37 INT2_N
40 INT1_N
41 INT0_N
34
33
31
32
ZM73XX
TDI
TDO
TCK
TMS
10µ
10µ
22µ
22µ
1.5mΩ
1.5mΩ
125mΩ 125mΩ
7
8
GND
GND
61
11
18
20
22
24
LCK_N
VS+
Low ESR Ceramic And
Tantalum Capacitors
VOUT
VOUT
VOUT
VOUT
50
55
7
ZY8160
EN3
EN2
EN1
EN0
18
RES_N
16
+VOUT
5
ACFAIL_N
22µ
22µ
22µ
47µ
220µ
4
49
51
52
54
1
9
14
15
16
17
19
21
23
10
HRES_N
IR
PG3
PG2
PG1
PG0
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
GND
GND
GND
GND
VS-
-VOUT
63
VSS VSS VSS VSS VSS VSS
26 38 43 58
10k
8
9
Figure 16. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I2C Interface
The schematic of a typical application of ZY8160 point-of-load converters (POL) is shown in Figure 16. The
system includes a ZM7300 series Digital Power Manager (DPM), a ZY8160 POL, and may include additional
ZY8160 POLs and other Z-One® series POLs. All POLs are connected to the DPM and to each other via a single-
wire SD (sync/data) line. The line provides synchronization of all POLs to the master clock generated by the DPM
and simultaneously performs data transfer between POLs and the DPM. Each POL has a unique 5-bit address
programmed by grounding respective address pins. To enable the current share, CS pins of POLs connected in
parallel are interconnected.
In addition to the SD line, OK pins of the POLs are connected to the respective OK pins of the DPM. A number of
POLs connected to the same OK pin of the DPM forms a group. Grouping of POLs enables users to program,
control, and monitor multiple POLs simultaneously and execute advanced fault management schemes.
The type, value, and the number of output capacitors shown in the schematic are required to meet the
specifications published in the data sheet. However, ZY8160 POLs are fully operational with different parameters
of output capacitors. The feedback loop compensation may need to be adjusted to optimize performance of the
POLs for specific parameters of the output capacitors.
ZD-01674 Rev. 1.5, 5-May-2011
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Page 12 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
7. Pin Assignments and Description
Pin
Name
Pin
Pin
Buffer
Type
Pin Description
Notes
Number Type
Connect to OK pin of other Z-POL and/or DPM.
Leave floating, if not used
OK
3
I/O
PU
Fault/Status Condition
SD
5
4
I/O
I/O
PU
PU
Sync/Data Line
Power Good
Connect to SD pin of DPM
PGOOD
Connect to CS pin of other Z-POLs connected in
parallel
CS
6
I/O
PU
Current Share
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-VS
16
15
14
9
I
I
I
I
I
I
I
PU
PU
PU
PU
PU
A
POL Address Bit 4
POL Address Bit 3
Tie to GND for 0 or leave floating for 1
Tie to GND for 0 or leave floating for 1
Tie to GND for 0 or leave floating for 1
Tie to GND for 0 or leave floating for 1
Tie to GND for 0 or leave floating for 1
Connect to the negative point close to the load
Connect to the positive point close to the load
POL Address Bit 2
POL Address Bit 1
1
POL Address Bit 0
10
11
Negative Voltage Sense
Positive Voltage Sense
+VS
A
18, 20,
22,24
7, 8, 17,
19, 21,
23
VOUT
P
Output Voltage
GND
VIN
P
P
Power Ground
Input Voltage
12, 13
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
ZY8160 converters can be programmed using the
Graphical User Interface or directly via the I2C bus by
using high and low level commands as described in
the ”ZM7300 Digital Power Manager Programming
Manual”.
8. Programmable Features
Performance parameters of ZY8160 POL converters
can be programmed via the industry standard I2C
communication
bus
without
replacing
any
components or rewiring PCB traces. Each parameter
has a default value stored in the volatile memory
registers detailed in Table 1. The setup registers 00h
through 14h are programmed at the system power-
up. When the user programs new performance
parameters, the values in the registers are
overwritten. Upon removal of the input voltage, the
default values are restored.
ZY8160 parameters can be reprogrammed at any
time during the system operation and service except
for the digital filter coefficients, the switching
frequency and the duty cycle limit, that can only be
changed when the POL output is turned off.
8.1
Output Voltage
The output voltage can be programmed in the POL
Output Configuration window shown in the Figure 17
or directly via the I2C bus by writing into the VOS
register shown in Figure 18.
Table 1. ZY8160 Memory Registers
Register
Content
Address
PC1
PC2
PC3
DON
DOF
TC
Protection Configuration 1
Protection Configuration 2
Protection Configuration 3
Turn-On Delay
00h
01h
02h
05h
06h
03h
04h
Turn-Off Delay
Tracking Configuration
Interleave Configuration and
Frequency Selection
INT
RUN
ST
VOS
CLS
DCL
B1
RUN Register
Status Register
15h
16h
07h
08h
09h
0Ah
Output Voltage Setpoint
Current Limit Setpoint
Duty Cycle Limit
Dig Controller Denominator z-1
Coefficient
B2
Dig Controller Denominator z-2
Coefficient
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
B3
Dig Controller Denominator z-3
Coefficient
C0L
C0H
C1L
C1H
C2L
C2H
C3L
C3H
Dig Controller Numerator z0
Coefficient, Low Byte
Dig Controller Numerator z0
Coefficient, High Byte
Dig Controller Numerator z-1
Coefficient, Low Byte
Dig Controller Numerator z-1
Coefficient, High Byte
Dig Controller Numerator z-2
Coefficient, Low Byte
Dig Controller Numerator z-2
Coefficient, High Byte
Dig Controller Numerator z-3
Coefficient, High Byte
Dig Controller Numerator z-3
Coefficient, Low Byte
Output Voltage Monitoring
Output Current Monitoring
Temperature Monitoring
Figure 17. Output Configuration Window
R/W-0
VOS7
Bit 7
R/W-0
VOS6
R/W-0
VOS5
R/W-0
VOS4
R/W-0
VOS3
R/W-0
VOS2
R/W-0
VOS1
R/W-0
VOS0
Bit 0
VOS[7:0]
Bit 7:0
, Output voltage setting
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
00h: corresponds to 0.5000V
01h: corresponds to 0.5125V
…
77h: corresponds to 1.9875V
78h: corresponds to 2.0000V
79h: corresponds to 2.025V
…
- n = Value at POR reset
…
96h: corresponds to 2.750V
VOM
IOM
TMP
17h
18h
19h
Figure 18. Output Voltage Setpoint Register VOS
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
8.1.1
Output Voltage Setpoint
VOUT
The output voltage programming range is from 0.5V
to 2.75V. To improve the resolution of the output
voltage settings, the voltage range is divided into
sub-ranges as shown in Table 2.
Upper Regulation
Limit
Operating
Point
VI Curve Without
Load Regulation
VI Curve With
Load Regulation
Headroom without
Load Regulation
Headroom with
Table 2. Output Voltage Adjustment Resolution
Lower Regulation
Limit
VOUT MIN, V
0.500
VOUT MAX, V
2.000
Resolution, mV
Load Regulation
12.5
25
Heavy
Load
Light
Load
IOUT
2.025
2.75
Figure 19. Concept of Optimal Voltage Positioning
8.1.2
Output Voltage Margining
Increased headroom allows tolerating larger voltage
deviations. For example, the step load change from
light to heavy load will cause the output voltage to
drop. If the optimal voltage positioning is utilized, the
output voltage will stay within the regulation window.
Otherwise, the output voltage will drop below the
lower regulation limit. To compensate for the voltage
drop external output capacitance will need to be
added, thus increasing cost and complexity of the
system.
If the output voltage needs to be varied by a certain
percentage, the margining function can be utilized.
The margining can be programmed in the POL
Output Configuration window or directly via the I2C
bus using high level commands as described in the
‘”DPM Programming Manual”.
In order to properly margin POLs that are connected
in parallel, the POLs must be members of one of the
Parallel Buses. Refer to the DPM Configure Devices
window shown in Figure 45.
The effect of optimal voltage positioning is shown in
Figure 20 and Figure 21. In this case, switching
output load causes large peak-to-peak deviation of
the output voltage. By programming load regulation,
the peak to peak deviation is dramatically reduced.
8.1.3
Optimal Voltage Positioning
Optimal voltage positioning increases the voltage
regulation window by properly positioning the output
voltage setpoint. Positioning is determined by the
load regulation that can be programmed in the GUI
Output Configuration window shown in Figure 17 or
directly via the I2C bus by writing into the CLS
register shown in Figure 28.
Figure 19 illustrates optimal voltage positioning
concept. If no load regulation is programmed, the
headroom (voltage differential between the output
voltage setpoint and
a
regulation limit) is
approximately half of the voltage regulation window.
When load regulation is programmed, the output
voltage will decrease as the output current
increases, so the VI characteristic will have a
negative slope. Therefore, by properly selecting the
operating point, it is possible to increase the
headroom as shown in the picture.
Figure 20. Transient Response without Optimal Voltage
Positioning
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
R/W-0
DON7
Bit 7
R/W-0
DON6
R/W-0
DON5
R/W-0
DON4
R/W-0
DON3
R/W-0
DON2
R/W-0
DON1
R/W-0
DON0
Bit 0
Bit 7:0 DON[7:0]: Turn-on delay time
00h: corresponds to 0ms delay after turn-on command has occurred
…
FFh: corresponds to 255ms delay after turn-on command has occurred
Figure 23. Turn-On Delay Register DON
8.2.2
Turn-Off Delay
U
U
R/W-0
DOF5
R/W-0
DOF4
R/W-0
DOF3
R/W-0
DOF2
R/W-0
DOF1
R/W-0
DOF0
Bit 0
---
---
Bit 7
Bit 7:6 Unimplemented, read as ‘0’
Bit 5:0 DOF[5:0]: Turn-off delay time
Figure 21. Transient Response with Optimal Voltage
Positioning
00h: corresponds to 0ms delay after turn-off command has occurred
…
3Fh: corresponds to 63ms delay after turn-off command has occurred
Figure 24. Turn-Off Delay Register DOF
8.2
Sequencing and Tracking
Turn-on delay, turn-off delay, and rising and falling
output voltage slew rates can be programmed in the
GUI Sequencing/Tracking window shown in Figure
22 or directly via the I2C bus by writing into the DON,
DOF, and TC registers, respectively. The registers
are shown in Figure 23, Figure 24, and Figure 26.
Turn-off delay is defined as an interval from the
application of the Turn-Off command until the output
voltage reaches zero (if the falling slew rate is
programmed) or until both high side and low side
switches are turned off (if the slew rate is not
programmed). Therefore, for the slew rate controlled
turn-off the ramp-down time is included in the turn-off
delay as shown in Figure 25.
User programmed turn-off delay, TDF
Turn-Off
Command
Calculated
Ramp-down time, TF
delay TD
Internal
ramp-down
command
Falling slew
rate dVF/dT
VOUT
Time
Figure 25. Relationship between Turn-Off Delay and Falling
Slew Rate
Figure 22. Sequencing Window
As it can be seen from the figure, the internally
calculated delay TD is determined by the equation
8.2.1
Turn-On Delay
below.
VOUT
Turn-on delay is defined as an interval from the
application of the Turn-On command until the output
voltage starts ramping up.
TD = TDF
−
,
dVF
dT
For proper operation TD shall be greater than zero.
The appropriate value of the turn-off delay needs to
be programmed to satisfy the condition.
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
If the falling slew rate control is not utilized, the turn-
off delay only determines an interval from the
application of the Turn-Off command until both high
side and low side switches are turned off. In this
case, the output voltage ramp-down process is
determined by load parameters.
R/W-1
SC
U
---
R/W-0
R2
R/W-0
R1
R/W-0
R0
R/W-0
F2
R/W-0
F1
R/W-0
F0
Bit 7
Bit 0
Unimplemented
Bit 7
, read as ‘0’
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
R[2:0]
Bit 6:4
: Value of Vo rising slope
0: corresponds to 0.1V/ms (default)
1: corresponds to 0.2V/ms
2: corresponds to 0.5V/ms
3: corresponds to 1.0V/ms
4: corresponds to 2.0V/ms
5: corresponds to 5.0V/ms
6: corresponds to 8.3V/ms
7: corresponds to 8.3V/ms
- n = Value at POR reset
8.2.3
Rising and Falling Slew Rates
The output voltage tracking is accomplished by
programming the rising and falling slew rates of the
output voltage. To achieve programmed slew rates,
the output voltage is being changed in 12.5mV steps
where duration of each step determines the slew
rate. For example, ramping up a 1.0V output with a
slew rate of 0.5V/ms will require 80 steps duration of
25μs each.
SC
Bit 3
, Slew rate control at turn-off
0: Slew rate control is disabled
1: Slew rate control is enabled
F[2:0]
Bit 2:0
: Value of Vo falling slope
0: corresponds to -0.1V/ms (default)
1: corresponds to -0.2V/ms
2: corresponds to -0.5V/ms
3: corresponds to -1.0V/ms
4: corresponds to -2.0V/ms
5: corresponds to -5.0V/ms
6: corresponds to –8.3V/ms
7: corresponds to –8.3V/ms
Duration of each voltage step is calculated by
dividing the master clock frequency generated by the
DPM. Since all POLs in the system are synchronized
to the master clock, the matching of voltage slew
rates of different outputs is very accurate as it can be
seen in Figure 7 and Figure 11.
Figure 26. Tracking Configuration Register TC
8.3
Protection
ZY8160 Series converters have a comprehensive set
of programmable protection functions. The set
includes the output over- and undervoltage
protection, overcurrent protection, overtemperature
protection, tracking protection, overtemperature
warning, and Power Good signal. Status of
protection functions is stored in the ST register
shown in Figure 27.
During the turn on process, a POL not only delivers
current required by the load (ILOAD), but also charges
the load capacitance. The charging current can be
determined from the equation below:
dVR
ICHG = CLOAD
×
dt
Where, CLOAD is load capacitance, dVR/dt is rising
voltage slew rate, and ICHG is charging current.
R-1
TP
R-0
PG
R-1
TR
R-1
OT
R-1
OC
R-1
UV
R-1
OV
R-1
PV
Bit 7
Bit 0
When selecting the rising slew rate, a user needs to
ensure that
TP
Bit 7
: Temperature Warning
R
W
U
= Readable bit
= Writable bit
PG
TR
OT
OC
UV
OV
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
: Power Good Warning
: Tracking Fault
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
ILOAD + ICHG < IOCP
: Overtemperature Fault
: Overcurrent Fault
Where IOCP is the overcurrent protection threshold of
the ZY8160. If the condition is not met, then the
overcurrent protection will be triggered during the
turn-on process. To avoid this, dVR/dt and the
overcurrent protection threshold should be
programmed to meet the condition above.
: Undervoltage Fault
: Overvoltage Error
PV
: Phase Voltage Error (Not Active)
- An activated warning/fault/error is encoded as ‘0’
Figure 27. Protection Status Register ST
Thresholds of overcurrent, over- and undervoltage
protections, and Power Good limits can be
programmed in the POL Output Configuration
window or directly via the I2C bus by writing into the
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
CLS and PC2 registers shown in Figure 28 and
Figure 29.
R/W-0
LR2
R/W-0
LR1
R/W-0
LR0
R/W-1
TCE
R/W-1
CLS3
R/W-0
CLS2
R/W-1
CLS1
R/W-1
CLS0
Bit 0
Bit 7
Bit 7:5 LR[2:0], Load regulation configuration
000: 0 V/A/Ohm
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
001: 0.39 V/A/Ohm
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
100: 1.57 V/A/Ohm
- n = Value at POR reset
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
Bit 4
TCE, Temperature compensation enable
0: disabled
1: enabled
Bit 3:0 CLS[3:0], Current limit setting
0h: corresponds to 37%
1h: corresponds to 47%
…
Figure 30. Fault management window
Bh: corresponds to 140%
Values higher than Bh are translated to Bh (140%)
R/W-0
TRE
R/W-1
PVE
R/W-0
TRP
R/W-0
OTP
R/W-0
OCP
R/W-0
UVP
R/W-1
OVP
R/W-1
PVP
Figure 28. Current Limit Setpoint Register CLS
Bit 7
Bit 0
U
---
U
U
R/W-0
PGLL
R/W-1
R/W-0
R/W-0
R/W-0
UVPL0
Bit 0
TRE
Bit 7
: Tracking fault enable
1 = enabled
0 = disabled
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
---
---
OVPL1 OVPL0 UVPL1
Bit 7
PVE
1 = enabled
0 = disabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
: Phase voltage error enable
- n = Value at POR reset
Unimplemented
: Set Power Good Low Level
1 = 95% of Vo
Bit 7:5
Bit 4
, read as ‘0’
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
PGLL
TRP
1 = latching
0 = non latching
: Tracking fault protection
0 = 90% of Vo (Default)
- n = Value at POR reset
OVPL[1:0]
Bit 3:2
: Set Over Voltage Protection
OTP
1 = latching
0 = non latching
: Overtemperature protection configuration
Level
00 = 110% of Vo
01 = 120% of Vo
10 = 130% of Vo (Default)
11 = 130% of Vo
OCP
1 = latching
0 = non latching
: Overcurrent protection configuration
UVPL[1:0]
00 = 75% of Vo (Default)
01 = 80% of Vo
10 = 85% of Vo
11 = 90% of Vo
Bit 1:0
: Set Under Voltage Protection Level
UVP
1 = latching
0 = non latching
: Undervoltage protection configuration
OVP
1 = latching
0 = non latching
: Overvoltage protection configuration
Figure 29. Protection Configuration Register PC2
PVP
: Phase Voltage Protection (Not Active)
1 = latching
0 = non latching
Note that the overvoltage and undervoltage
protection thresholds and Power Good limits are
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
Figure 31. Protection Configuration Register PC1
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection is removed. When
restarting, the output voltages follow tracking and
sequencing settings.
In addition, a user can change type of protections
(latching or non-latching) or disable certain
protections. These settings are programmed in the
POL Fault management window shown in Figure 30
or directly via the I2C by writing into the PC1 register
shown in Figure 31.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault is removed and
the respective bit in the ST register was cleared, or
the Turn On command was recycled, or the input
voltage was recycled.
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
All protection functions can be classified into three
groups based on their effect on system operation:
warnings, faults, and errors.
8.3.2
Faults
This group includes overcurrent, overtemperature,
undervoltage, and tracking protections. Triggering
any protection in this group will turn off the POL.
8.3.1
Warnings
This group includes Overtemperature Warning and
Power Good Signal. Warnings do not turn off POLs
but rather set status bits which can be noted by the
DPM and be transmitted to a host controller via the
I2C bus.
8.3.2.1
Overcurrent Protection
Overcurrent protection is active whenever the output
voltage of the POL exceeds the pre-bias voltage (if
any). When the output current reaches the OC
threshold, the output voltage will start decreasing. As
soon as the output voltage decreases below the
undervoltage protection threshold, the OC fault
signal is generated, the POL turns off and the OC bit
in the register ST is changed to 0. Both high side and
low side switches of the POL are turned off instantly
(fast turn-off).
8.3.1.1
Overtemperature Warning
The Overtemperature Warning is generated when
temperature of the controller exceeds 120°C. The
Overtemperature Warning changes the PT bit of the
status register ST to 0 and sends the signal to the
DPM. Reporting is enabled in the POL Configuration
Faults window or directly via the I2C by writing into
the PC3 register shown in Figure 33. When the
temperature falls below 117°C, the PT bit is cleared
and the Overtemperature Warning is removed.
The temperature compensation is added to keep the
OC
temperatures above room temperature. Note that the
temperature compensation can be disabled in the
POL Output Configuration window or directly via the
I2C by writing into the CLS register. However, it is
threshold
approximately
constant
at
8.3.1.2
Power Good
recommended
to
keep
the
temperature
compensation enabled.
Power Good is an open collector output that is pulled
low, if the output voltage is outside of the Power
Good window. The window is formed by the Power
Good High threshold that is equal to 110% of the
output voltage and the Power Good Low threshold
that can be programmed at 90 or 95% of the output
voltage.
8.3.2.2
Undervoltage Protection
The undervoltage protection is only active during
steady state operation of the POL to prevent
nuisance tripping. If the output voltage decreases
below the UV threshold and there is no OC fault, the
UV fault signal is generated, the POL turns off, and
the UV bit in the register ST is changed to 0. The
output voltage is ramped down according to
sequencing and tracking settings (regular turn-off).
The Power Good protection is only enabled after the
output voltage reaches its steady state level. The PG
pin is pulled low during transitions of the output
voltage from one level to other as shown in Figure
32.
8.3.2.3
Overtemperature Protection
The Power Good Warning pulls the Power Good pin
low and changes the PG bit of the status register ST
to 0. It sends the signal to the DPM, if the reporting is
enabled. When the output voltage returns within the
Power Good window, the PG pin is pulled high, the
PG bit is cleared and the Power Good Warning is
removed. The Power Good pin can also be pulled
low by an external circuit to initiate the Power Good
Warning.
Overtemperature protection is active whenever the
POL is powered up. If temperature of the controller
exceeds 120°C, the OT fault is generated, POL turns
off, and the OT bit in the register ST is changed to 0.
The output voltage is ramped down according to
sequencing and tracking settings (regular turn-off).
If non-latching OTP is programmed, the POL will
restart as soon as the temperature of the controller
decreases below the Overtemperature Warning
threshold of 110°C.
Note: To retrieve status information, Status Monitoring in the DPM
Configure Devices window should be enabled (refer to
Digital Power Manager Data Sheet). The DPM will retrieve
the status information from each POL on a continuous
basis.
ZD-01674 Rev. 1.5, 5-May-2011
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Page 19 of 29
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
8.3.2.4
Tracking Protection
value of the difference exceeds 250mV, the tracking
fault signal is generated, the POL turns off, and the
TR bit in the register ST is changed to 0. Both high
side and low side switches of the POL are turned off
instantly (fast turn-off).
Tracking protection is active only when the output
voltage is ramping up. The purpose of the protection
is to ensure that the voltage differential between
multiple rails being tracked does not exceed 250mV.
This protection eliminates the need for external
clamping diodes between different voltage rails
which are frequently recommended by ASIC
manufacturers.
The tracking protection can be disabled, if it
contradicts requirements of a particular system (for
example turning into high capacitive load where
rising slew rate is not important). It can be disabled
in the POL Configuration Faults window or directly
via the I2C bus by writing into the PC1 register.
When the tracking protection is enabled, the POL
continuously compares actual value of the output
voltage to its programmed value as defined by the
output voltage and its rising slew rate. If absolute
Vo
1
Enable command
OTP
0
continuously enabled
1
0
OCP enabled
1
0
Power Good
Signal
OVP Threshold
OVP Threshold
PG High=110%VOUT
PG High=110%VOUT
OVP Threshold
Output Voltage
Output Voltage
PG High=110%VOUT
Output Voltage
PG Low Threshold
UVP Threshold
PG Low Threshold
UVP Threshold
PG Low Threshold
1.0V
prebiased output
UVP Threshold
Tracking
Thresholds
Time
Figure 32. Protections Enable Conditions
energy stored in the output filter and achieve
effective voltage limitation.
8.3.3
Errors
The group includes overvoltage protection and the
phase voltage error. The phase voltage error is not
available in ZY8160.
The OV threshold can be programmed from 110% to
130% of the output voltage setpoint, but not lower
than 1.0V.
8.3.3.1
Overvoltage Protection
The overvoltage protection is active whenever the
output voltage of the POL exceeds the pre-bias
voltage (if any). If the output voltage exceeds the
overvoltage protection threshold, the overvoltage
error signal is generated, the POL turns off, and the
OV bit in the register ST is changed to 0. The high
side switch is turned off instantly, and simultaneously
the low side switch is turned on to ensure reliable
protection of sensitive loads. The low side switch
provides low impedance path to quickly dissipate
8.3.4
Faults and Errors Propagation
The feature adds flexibility to the fault management
scheme by giving users control over propagation of
fault signals within and outside of the system. The
propagation means that a fault in one POL can be
programmed to turn off other POLs and devices in
the system, even if they are not directly affected by
the fault.
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
8.3.4.1
Grouping of POLs
Z-Series POLs can be arranged in several groups to
simplify fault management. A group of POLs is
defined as a number of POLs with interconnected
OK pins. A group can include from 1 to 32 POLs. If
fault propagation within a group is desired, the
propagation bit needs to be checked in the GUI Fault
Management Window. The parameters can also be
programmed directly via the I2C bus by writing into
the PC3 register shown in Figure 33.
When propagation is enabled, the faulty POL pulls its
OK pin low. A low OK line initiates turn-off of other
POLs in the group.
Figure 34. DPM Fault Propagation Window
R/W-0
PTM
R/W-0
PGM
R/W-1
TRP
R/W-1
OTP
R/W-1
OCP
R/W-1
UVP
R/W-1
OVP
R/W-1
PVP
In this case low OK line will signal DPM to pull other
OK lines low to initiate shutdown of other POLs as
programmed in the DPM Faults / Group Fault
Propagation window. If an error is propagated, the
DPM can also generate commands to turn off a front
end (a DC-DC converter generating the intermediate
bus voltage) and trigger an optional crowbar
protection to accelerate removal of the IBV voltage.
Bit 7
Bit 0
PTM
Bit 7
: Temperature warning Message
1 = enabled
0 = disabled
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
PGM
1 = enabled
0 = disabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
: Power good message
- n = Value at POR reset
TRP
1 = enabled
0 = disabled
: Tracking fault propagation
8.3.4.2
Propagation Process
OTP
1 = enabled
0 = disabled
: Overtemperature fault propagation
Propagation of a fault (OCP, UVP, OTP, and TRP)
initiates regular turn-off of other POLs. The faulty
POL in this case performs either the regular or the
fast turn-off depending on a specific fault as
described in section 8.3.2.
OCP
1 = enabled
0 = disabled
: Overcurrent fault propagation
UVP
1 = enabled
0 = disabled
: Undervoltage fault propagation
OVP
1 = enabled
0 = disabled
: Overvoltage error propagation
Propagation of an error initiates fast turn-off of other
POLs. The faulty POL performs the fast turn-off and
turns on its low side switch.
PVP
: Phase voltage error propagation (Not Active)
1 = enabled
0 = disabled
Example of the fault propagation is shown in Figure
35 - Figure 36. In this three-output system (refer to
the block diagram in Figure 16), the POL powering
the output V3 (Ch 1 in the picture) encounters the
undervoltage fault after the turn-on. When the fault
propagation is not enabled, the POL turns off and
generates the UV fault signal. Because the UV fault
triggers the regular turn off, the POL meets its turn-
off delay and falling slew rate settings during the
turn-ff process as shown in Figure 35. Since the UV
fault is programmed to be non-latching, the POL will
attempt to restart every 130ms, repeating the
process described above until the condition causing
the undervoltage is removed.
Figure 33. Protection Configuration Register PC3
In addition, the OK lines can be connected to the
DPM to facilitate propagation of faults and errors
between groups. One DPM can control up to 4
independent groups. To enable fault propagation
between groups, the respective bit needs to be
checked in the DPM Faults
/
Group Fault
Propagation window shown in Figure 34.
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
If the fault propagation between groups is enabled,
the POL powering the output V3 pulls its OK line low
and the DPM propagates the signal to the POL
powering the output V1 that belongs to other group.
The POL powering the output V1 (Ch3 in the picture)
executes the regular turn-off. Since both V1 and V3
have the same delay and slew rate settings they will
continue to turn off and on synchronously every
130ms as shown in Figure 36 until the condition
causing the undervoltage is removed. The POL
powering the output V2 continues to ramp up until it
reaches its steady state level.
130ms is the interval from the instant of time when
the output voltage ramps down to zero until the
output voltage starts to ramp up again. Therefore,
the 130ms hiccup interval is guaranteed regardless
of the turn-off delay setting.
Figure 36. Turn-On into UVP on V3. The UV Fault Is
Programmed To Be Non-Latching and Propagate
From Group C to Group A. Ch1 – V3 (Group C),
Ch2 – V2, Ch3 – V1 (Group A)
Summary of protections, their parameters and
features are shown in Table 3
Figure 35. Turn-On into UVP on V3. The UV Fault Is
Programmed To Be Non-Latching. Ch1 – V3 (Group
C), Ch2 – V2, Ch3 – V1 (Group A)
Table 3. Summary of Protections Parameters and Features
Code
PT
Name
Type
When Active
Turn
Off
Low Side
Switch
Propagation
Disable
No
Temperature
Warning
Power Good
Warning
Warning
Whenever VIN is applied
During steady state
No
N/A
Readable by
DPM
Readable by
DPM
PG
No
N/A
No
TR
OT
OC
UV
OV
Tracking
Overtemperature
Overcurrent
Fault
Fault
Fault
Fault
Error
During ramp up
Fast
Regular
Fast
Off
Off
Off
Off
On
Regular turn off
Regular turn off
Regular turn off
Regular turn off
Fast turn off
Yes
No
No
No
No
Whenever VIN is applied
When VOUT exceeds prebias
During steady state
Undervoltage
Overvoltage
Regular
Fast
When VOUT exceeds prebias
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
8.4
PWM Parameters
R/W-0
FRQ2
Bit 7
R/W-0
FRQ1
R/W-0
FRQ0
R/W-01) R/W-01) R/W-01) R/W-01) R/W-01)
INT4
INT3
INT2
INT1
INT0
Bit 0
Z-Series POLs utilize the digital PWM controller. The
controller enables users to program most of the
PWM performance parameters, such as switching
frequency, interleave, duty cycle, and feedback loop
compensation.
FRQ[2:0]
Bit 7:5
: PWM Frequency Selection
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
000: 500kHz
001: 750kHz
010: 1000kHz
- n = Value at POR reset
8.4.1
Switching Frequency
The switching frequency can be programmed in the
PWM sub window in the POL Configuration
Compensation window shown in Figure 37 or directly
via the I2C bus by writing into the INT register shown
in Figure 38. Note that the content of the register can
be changed only when the POL is turned off.
INT[4:0]
Bit 4:0
: Interleave position
00h: Ton starts with 0.0° Phase lag to SD Line
01h: Ton starts with 11.25° Phase lag to SD Line
02h: Ton starts with 22.50° Phase lag to SD Line
…
1Fh: Ton starts with 348.75° Phase lag to SD Line
1) Initial value depends on the state of the Interleave Mode (
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded
IM=Low: At POR reset a 0 is loaded
) Input:
IM
Switching actions of all POLs connected to the SD
line are synchronized to the master clock generated
by the DPM. Each POL is equipped with a PLL and a
frequency divider so they can operate at multiples
(including fractional) of the master clock frequency
as programmed by a user. The POL converters can
operate at 500kHz, 750kHz, and 1MHz. Although
synchronized, switching frequencies of different
POLs are independent of each other. It is
permissible to mix POLs operating at different
frequencies in one system. It allows optimizing
efficiency and transient response of each POL in the
system individually.
Figure 38. Interleave Configuration Register INT
8.4.2
Interleave
Interleave is defined as a phase delay between the
synchronizing slope of the master clock on the SD
pin and PWM signal of a POL. The interleave can be
programmed in the PWM section of the POL
Controller Compensation window or directly via the
I2C bus by writing into the INT register.
Every POL generates switching noise. If no
interleave is programmed, all POLs in the system
switch simultaneously and noise reflected to the
input source from all POLs is added together as
shown in Figure 39.
Figure 37. POL Controller Compensation Window
Figure 39. Input Voltage Noise, No Interleave
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Figure 40 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 67.5°, 180°, and 303.75°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction. To
achieve similar noise reduction without the interleave
will require the addition of an external LC filter.
Figure 42. Output Voltage Noise, Full Load, 180° Interleave
ZY8160 interleave is independent of the number of
POLs in a system and is fully programmable in
11.25° steps. It allows maximum output noise
reduction by intelligently spreading switching energy.
Note: Due to noise sensitivity issues that may occur in limited
cases, it is recommended to avoid phase lag settings of
112.5 and 123.75 degrees, otherwise false PG and/or OV
indications may occur.
Figure 40. Input Voltage Noise with Interleave
8.4.3
Duty Cycle Limit
Similar noise reduction can be achieved on the
output of POLs connected in parallel. Figure 41 and
Figure 42 show the output noise of two POLs
connected in parallel without and with a 180°
interleave, respectively. Resulting noise reduction is
more than 2 times and is equivalent to doubling
switching frequency or adding extra capacitance on
the output of the POLs.
The ZY8160 is a step-down converter therefore VOUT
is always less than VIN. The relationship between the
two parameters is characterized by the duty cycle
and can be estimated from the following equation:
VOUT
DC =
,
VIN.MIN
Where, DC is the duty cycle, VOUT is the required
maximum output voltage (including margining),
VIN.MIN is the minimum input voltage.
It is good practice to limit the maximum duty cycle of
the PWM controller to a somewhat higher value
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the PWM section
of the POL Controller Compensation window or
directly via the I2C bus by writing into the DCL
register shown in Figure 43.
Figure 41. Output Voltage Noise, Full Load, No Interleave
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
R/W-1
DCL5
Bit 7
R/W-1
DCL4
R/W-1
DCL3
R/W-0
DCL2
R/W-1
DCL1
R/W-0
DCL0
R/W-0
HI
R/W-0
LO
The transfer function of the POL converter is shown
in Figure 44. It is a third order function with two zeros
and three poles. Pole 1 is the integrator pole, Pole 2
is used in conjunction with Zero 1 and Zero 2 to
adjust the phase lead and limit the gain increase in
mid band. Pole 3 is used as a high frequency low-
pass filter to limit PWM noise.
Bit 0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
DCL[5:0]
Bit 7:2
, Duty Cycle Limitation
00h: 0
01h: 1/192
…
- n = Value at POR reset
3Fh: 63/192
HI
Bit 1:
Bit 0:
, ADC high saturation feed -forward
0: disabled
1: enabled
Magnitude[dB]
LO
, ADC low saturation feed -forward
50
40
30
20
10
Z1 P1 Z2 P2
P3
0: disabled
1: enabled
P1: Pole 1
P2: Pole 3
P3: Pole 3
Z1: Zero 1
Z2: Zero 2
Figure 43. Duty Cycle Limit Register
8.4.4
ADC Saturation Feedforward
To speed up the PWM response in case of heavy
dynamic loads, the duty cycle can be forced either to
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
two comparators defining a window around the
output voltage setpoint. When an error signal is
inside the window, it will produce gradual duty cycle
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
output current steps), the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
controller, reducing amount of required external
capacitance.
Freq
[kHz]
0.1
0.1
1
1
10
10
100
1000
1000
Phase
[°]
+45
Freq
[kHz]
0
-45
100
-90
-135
-180
Figure 44. Transfer Function of PWM
Positions of poles and zeroes are determined by
coefficients of the digital filter. The filter is
characterized by four numerator coefficients (C0, C1,
C2, C3) and three denominator coefficients (B1, B2,
B3). The coefficients are automatically calculated
when desired frequency of poles and zeros is
entered in the PWM section of the POL Controller
Compensation window. The coefficients are stored in
the C0H, C0L, C1H, C1L, C2H, C2L, C3H, C3L, B1,
B2, and B3 registers.
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
overcompensation of the output error. The
phenomenon manifests itself as low frequency
oscillations on the output of the POL. It can usually
be reduced or eliminated by disabling the ADC
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V.
Note: The GUI automatically transforms zero and pole
frequencies into the digital filter coefficients. It is strongly
recommended to use the GUI to determine the filter
coefficients.
The ADC saturation feedforward can be
programmed in the PWM section of the DPM
Configuration Compensation window or directly via
the I2C bus by writing into the DCL register.
Programming feedback loop compensation allows
optimizing POL performance for various application
conditions. For example, increase in bandwidth can
significantly improve dynamic response.
8.4.5
Feedback Loop Compensation
8.5
Current Share
Feedback loop compensation can be programmed in
the POL Controller Compensation window by setting
frequency of poles and zeros of the transfer function.
The POL converters are equipped with the digital
current share function. To activate the current share,
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
interconnect the CS pins of the POLs connected in
parallel. The digital signal transmitted over the CS
line sets output currents of all POLs to the same
level.
The output voltage is measured at the output sense
pins, output current is measured using the ESR of
the output inductor and temperature is measured by
the thermal sensor built into the controller IC. Output
current readings are adjusted based on temperature
readings to compensate for the change of ESR of
the inductor with temperature.
When POLs are connected in parallel, they must be
included in the same parallel bus in the DPM
Configure Devices window shown in Figure 45. In
this case, the GUI automatically copies parameters
of one POL onto all POLs connected to the parallel
bus. It makes it impossible to configure different
performance parameters for POLs connected in
parallel except for interleave and load regulation
settings that are independent. The interleave allows
to reduce and move the output noise of the
converters connected in parallel to higher
frequencies as shown in Figure 41 and Figure 42.
The load regulation allows controlling the current
share loop gain in case of small signal oscillations. It
is recommended to always add a small amount of
load regulation to one of the converters connected in
parallel to reduce loop gain and therefore improve
stability.
An 8-Bit Analog to Digital Converter (ADC) converts
the output voltage, output current, and temperature
into a digital signal to be transmitted via the serial
interface. The ADC allows a minimum sampling
frequency of 700 Hz for all three values.
Monitored parameters are stored in registers (VOM,
IOM, and TMON) that are continuously updated. If
the Retrieve Monitoring bits for Parametric (P-
Monitor) and Status (S-Monitor) in the DPM
Configure Devices window shown in Figure 45 are
checked, those registers are being copied into the
ring buffer located in the DPM. Contents of the ring
buffer can be displayed in the DPM Monitoring
window shown in Figure 46 or it can be read directly
2C bus using high and low level commands
via the I
8.6
Performance Parameters Monitoring
as described in the ”ZM7300 Digital Power Manager
Programming Manual”.
The POL converters can monitor their own
performance parameters such as output voltage,
output current, and temperature.
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Figure 45. DPM Configure Devices Window
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
Figure 46. DPM Monitoring Window
selection of the input fuse. Both input traces and the
chassis ground trace (if applicable) must be capable
of conducting a current of 1.5 times the value of the
fuse without opening. The fuse must not be placed in
the grounded input line.
9. Safety
The ZY8160 POL converters do not provide
isolation from input to output. The input devices
powering ZY8160 must provide relevant isolation
requirements according to all IEC60950 based
standards. Nevertheless, if the system using the
converter needs to receive safety agency approval,
certain rules must be followed in the design of the
system. In particular, all of the creepage and
clearance requirements of the end-use safety
requirements must be observed. These requirements
are included in UL60950 - CSA60950-00 and
EN60950, although specific applications may have
other or additional requirements.
Abnormal and component failure tests were
conducted with the POL input protected by a fast-
acting 32V, 25A, fuse. If a fuse rated greater than
25A is used, additional testing may be required.
In order for the output of the ZY8160 POL converter
to be considered as SELV (Safety Extra Low
Voltage), according to all IEC60950 based
standards, the input to the POL needs to be supplied
by an isolated secondary source providing a SELV
also.
The ZY8160 POL converters have no internal fuse. If
required, the external fuse needs to be provided to
protect the converter from catastrophic failure. Refer
to the “Input Fuse Selection for DC/DC converters”
application note on www.power-one.com for proper
ZD-01674 Rev. 1.5, 5-May-2011
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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input • 0.5V to 2.75V Output
Data Sheet
10. Mechanical Drawings
All Dimensions are in mm
XX.X: ±0.1 XX.XX: ±0.05
Tolerances:
Figure 47. Mechanical Drawing
Figure 48. Recommended Footprint – Top View
Notes:
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical
components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written
consent of the respective divisional president of Power-One, Inc.
2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
I2C is a trademark of Philips Corporation.
ZD-01674 Rev. 1.5, 5-May-2011
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Page 29 of 29
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