AFBR-732BEHWZ [BOARDCOM]
Ultra Short Link Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver;
| 型号： | AFBR-732BEHWZ |
| 厂家： | 
Broadcom Corporation. |
| 描述： | Ultra Short Link Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver |
| 文件： | 总22页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFBR-732BWZ/BEWZ/BEHWZ and AFBR-742BZ/BEZ/BEHZ
Ultra Short Link Pluggable Parallel Fiber Optic Modules,
Transmitter and Receiver
Data Sheet
Description
Features
•ꢀ RoHS Compliant
•ꢀ Low cost per Gb/s
The AFBR-732BWZ transmitter and AFBR-742BZ receiver
are high performance fiber optic modules for parallel
optical data communication applications. These 12- •ꢀ High package density per Gb/s
channel devices, operating up to 2.5Gbd per channel,
provide a cost effective solution for short-reach appli-
cations requiring up to 30 Gb/s aggregate bandwidth.
These modules are designed to operate on multimode
fiber systems at a nominal wavelength of 850 nm. They
incorporate high performance, highly reliable, short
wavelength optical devices coupled with proven circuit
technology to provide long life and consistent service.
•ꢀ 3.3 volt power supply for low power consumption
•ꢀ 850 nm VCSEL array source
•ꢀ 12 independent channels per module
•ꢀ Separate transmitter and receiver modules
•ꢀ 2.5 Gbd data rate per channel
•ꢀ Standard MTP® (MPO) ribbon fiber connector inter-
face
•ꢀ Pluggable package
•ꢀ 50/125 micron multimode fiber operation:
Distance up to 50 m with 50um,
500 MHz.km fiber at 2.5 Gbd
•ꢀ Data I/O is CML compatible
•ꢀ Control I/O is LVTTL compatible
•ꢀ Manufactured in an ISO 9002 certified facility
The AFBR-732BWZ transmitter module incorporates a
12- channel VCSEL (Vertical Cavity Surface Emitting Laser)
array together with a custom 12-channel laser driver in-
tegrated circuit providing IEC-60825 and CDRH Class 1M
laser eye safety.
The AFBR-742BZ receiver module contains a 12-channel
PIN photodiode array coupled with a custom preamplifier
/ post amplifier integrated circuit.
Applications
•ꢀ Proprietary Ultra short link interconnects
Operating from a single +3.3 V power supply, both
modules provide LVTTL or LVCMOS control interfaces and
Current Mode Logic (CML) compatible data interfaces to
simplify external circuitry.
Ordering Information
The AFBR-732BWZ and AFBR-742BZ products are
available for production orders through the Avago
Component Field Sales office.
The transmitter and receiver devices are housed in MTP®/
MPO receptacled packages. Electrical connections to the
devices are achieved by means of a pluggable 10 x 10
connector array.
AFBR-732BWZ No EMI Nose Shield, with Heatsink
AFBR-742BZ No EMI Nose Shield, with Heatsink
AFBR-732BEWZ With EMI Nose Shield, with Heatsink
AFBR-742BEZ With EMI Nose Shield, with Heatsink
AFBR-732BEHWZ With EMI Nose Shield, No Heatsink
AFBR-742BEHZ With EMI Nose Shield, No Heatsink
Patent - www.avagotech.com/patents
Design Summary:
Functional Description, Receiver Section
Design for low-cost, high-volume manufacturing
The receiver section, Figure 2, contains a 12-channel
AlGaAs/ GaAs photodetector array, transimpedance
preamplifier, filter, gain stages to amplify and buffer the
signal, and a quantizer to shape the signal.
Avago’s parallel optics solution combines twelve 2.5
Gb/s channels into discrete transmitter and receiver
modules providing a maximum aggregate data rate of
30 Gb/s. Moreover, these modules employ a heat sink for
thermal management when used on high-density cards,
have excellent EMI performance, and interface with the
industry standard MTP®/MPO connector systems. They
provide the most cost-effective high- density (Gb/s per
inch) solutions for high-data capacity applications. See
The Signal Detect function is designed to sense the
proper optical output signal on each of the 12 channels.
If loss of signal is detected on an individual channel, that
channel output is squelched.
Packaging
Figure 1 for the transmitter and Figure 2 for the receiver The flexible electronic subassembly was designed to
block diagrams.
allow high-volume assembly and test of the VCSEL, PIN
photo diode and supporting electronics prior to final
assembly.
The AFBR-732BWZ transmitter and the AFBR-742BZ
receiver modules provide very closely spaced, high-speed
parallel data channels. Within these modules there will be
some level of cross talk between channels. The cross talk
within the modules will be exhibited as additional data
jitter or sensitivity reduction compared to single-channel
performance. Avago Technologies’ jitter and sensitiv-
ity specifications include cross talk penalties and thus
represent real, achievable module performance.
Regulatory Compliance
The overall equipment design into which the parallel
optics module is mounted will determine the certifica-
tion level. The module performance is offered as a figure
of merit to assist the designer in considering their use in
the equipment design.
Organization Recognition
Functional Description, Transmitter Section
See the Regulatory Compliance Table for a listing of the
standards, standards associations and testing laboratories
applicable to this product.
The transmitter section, Figure 1, uses a 12-channel 850
nm VCSEL array as the optical source and a diffractive
optical lens array to launch the beam of light into the
fiber. The package and connector system are designed to
allow repeatable coupling into standard 12-fiber ribbon
cable. In addition, this module has been designed to be
compliant with IEC 60825 Class 1M eye safety require-
ments.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The first case is during handling of the module prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and floor mats in ESD controlled
areas.
The optical output is controlled by a custom IC, which
provides proper laser drive parameters and monitors
drive current to ensure eye safety. An EEPROM and state
machine are programmed to provide both ac and dc
current drive to the laser to ensure correct modulation,
eye diagram over variations of temperature and power
supply voltages.
The second case to consider is static discharges to the
exterior of the equipment chassis containing the module
parts. To the extent that the MTP® (MPO) connector recep-
tacle is exposed to the outside of the equipment chassis
it may be subject to system level ESD test criteria that the
equipment is intended to meet.
See the Regulatory Compliance Table for further details.
2
COMPARATOR
SHUT
DOWN
AMPLIFIER
D/A
CONVERTER
12
12
DIN+
DIN-
12
INPUT
STAGE
LEVEL
SHIFTER
DRIVER
VCSEL ARRAY
4
SERIAL
CONTROL
I/O*
D/A
CONVERTER
CONTROLLER
TEMPERATURE
DETECTION
CIRCUIT
Figure 1. Transmitter block diagram(each channel).
* TX_EN, TX_DIS, RESET-, FAULT-
OFFSET
CONTROL
PIN
DOUT+
DOUT-
TRANS-
IMPEDANCE
PRE-AMPLIFIER
LIMITING
AMPLIFIER
OUTPUT
BUFFER
SIGNAL
DETECT
CIRCUIT
SD
Figure 2. Receiver block diagram (each channel).
3
Electromagnetic Interference (EMI)
Connector Cleaning
Many equipment designs using these high-data-rate The optical connector used is the MTP® (MPO). The optical
modules will be required to meet the requirements of the ports have recessed optics that are visible through the
FCC in the United States, CENELEC in Europe and VCCI in nose of the ports. The provided port plug should be
Japan. These modules, with their shielded design, perform installed any time a fiber cable is not connected. The port
to the levels detailed in the Regulatory Compliance Table. plug ensures the optics remain clean and no cleaning
The performance detailed in the Regulatory Compliance should be necessary. In the event the optics become
Table is intended to assist the equipment designer in the contaminated, forced nitrogen or clean dry air at less than
management of the overall equipment EMI performance. 20 psi is the recommended cleaning agent. The optical
However, system margins are dependent on the customer port features, including guide pins, preclude use of any
board and chassis design.
solid instrument. Liquids are not advised due to potential
damage.
Immunity
Process Plug
Equipment using these modules will be subject to radio
frequency electromagnetic fields in some environments. Each parallel optics module is supplied with an inserted
These modules have good immunity due to their shielded process plug for protection of the optical ports within the
designs. See the Regulatory Compliance Table for further MTP® (MPO) connector receptacle.
detail.
Handling Precautions
The AFBR-732BWZ and AFBR-742BZ can be damaged by
Eye Safety
These 850 nm VCSEL-based modules provide eye safety current surges and overvoltage conditions. Power supply
by design. The AFBR-732BWZ has been registered with transient precautions should be taken.
CDRH and certified by TUV as a Class 1M device under
Application of wave soldering, reflow soldering and/or
Amendment 2 of IEC 60825-1. See the Regulatory Com-
aqueous wash processes with the parallel optic device on
pliance Table for further detail. If Class 1M exposure is
board is not recommended as damage may occur.
possible, a safety-warning label should be placed on the
product stating the following:
Normal handling precautions for electrostatic sensitive
devices should be taken (see ESD section).
LASER RADIATION
DO NOT VIEW DIRECTLY WITH OPTICAL INSTRUMENTS
CLASS 1M LASER PRODUCT
The AFBR-732BWZ is a Class 1M laser product.
DO NOT VIEW RADIATION DIRECTLY WITH OPTICAL IN-
STRUMENTS.
4
[1,2]
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
Reference
Storage Temperature
(non-operating)
TS
–40
100
°C
1
Case Temperature (operating)
Supply Voltage
TC
90
°C
V
1, 2, 4
1, 2
1
VCC
VI
–0.5
–0.5
4.6
Data/Control Signal Input Voltage
VCC + 0.5
2
V
Transmitter Differential Data Input
Voltage
|VD|
V
1, 3
Output Current (dc)
ID
25
95
mA
%
1
1
Relative Humidity (non-condensing) RH
5
Notes:
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. See Reliability Data Sheet for specific reliability
performance.
2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability
is not implied, and damage to the device may occur over an extended period of time.
3. This is the maximum voltage that can be applied across the Transmitter Differential Data Inputs without damaging the input circuit.
4. Case Temperature is measured as indicated in Figure 3.
[1]
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Case Temperature
TC
0
40
80
°C
2, Figs. 3, 4
Supply Voltage
VCC
3.135
3.3
3.465
V
Figs. 5, 6,
12
Signaling Rate per Channel
1
2.5
Gbd
3
Data Input Differential
DVDINP-P
175
1400
mVP-P
4, Figs. 7, 8
Peak-to-Peak Voltage Swing
Control Input Voltage High
Control Input Voltage Low
VIH
VIL
NP
2.0
VEE
VCC
0.8
V
V
Power Supply Noise for
Transmitter and Receiver
200
mVP-P
5, Figs. 5, 6
Fig. 7
Transmitter/Receiver Data
I/O Coupling Capacitors
CAC
RDL
0.1
mF
W
Receiver Differential Data
Output Load
100
Fig. 7
Notes:
1. Recommended Operating Conditions are those values outside of which functional performance is not intended, device reliability is not im-
plied, and damage to the device may occur over an extended period of time. See Reliability Data Sheet for specific reliability performance.
2. Case Temperature is measured as indicated in Figure 3. A +55 °C, 1 m/s, parallel to the printed circuit board, air flow at the module or equiva-
lent cooling is required. See Figure 4.
3. The receiver has a lower cut off frequency near 100 kHz.
4. Data inputs are CML compatible. Coupling capacitors are required to block DC. DV
= DV
– DV , where DV
DINL
= High State Differ-
DINH
DINP-P
DINH
ential Data Input Voltage and DV
= Low State Differential Data Input Voltage.
DINL
5. Power Supply Noise is defined for the supply, VCC, over the frequency range from 500 Hz to 2500 MHz, with the recommended power supply
filter in place, at the supply side of the recommended filter. See Figures 5 and 6 for recommended power supply filters.
5
Electrical Characteristics
Transmitter Electrical Characteristics
(T = 0 °C to +80 °C, V = 3.3 V 5%, Typical T = +40 °C, V = 3.3 V)
C
CC
C
CC
Reference
(Conditions)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Current
ICCT
364
415
mA
Fig. 6
Power Dissipation
PDIST
Zin
1.2
1.45
120
250
W
W
Differential Input Impedance
FAULT Assert Time
80
100
200
1, Fig. 7, 11
Fig. 13
TOFF
ms
RESET Assert Time
TOFF
5
7.5
ms
Fig. 14
RESET De-assert Time
TON
TON
TOFF
55
55
5
100
100
7.5
ms
ms
ms
Fig. 14
Transmit Enable (TX_EN) Assert Time
Transmit Enable (TX_EN) De-assert Time
Fig. 15
2, Fig. 15
Transmit Disable (TX_DIS) Assert Time
TOFF
5
7.5
ms
Fig. 15
Transmit Disable (TX_DIS) De-assert Time
Power On Initiation Time
TON
TINT
55
60
100
100
ms
ms
Fig. 15
Fig. 12
Control I/Os
|Input Current High |
| Input Current Lo w|
Output Voltage Low
Output Voltage High
|IIH|
|IIL|
0.5
0.5
0.4
VCC
mA
mA
V
(2.0 V < VIH < VCC
(VEE < VIL < 0.8 V)
(IOL = 4.0 mA)
)
(TX_EN, TX_DIS
FAULT, RESET)
Compatible
VOL
VOH
VEE
2.5
3.3
V
(IOH = –0.5 mA)
Notes:
1. Differential impedance is measured between D and D over the range 4 MHz to 2 GHz.
IN+
IN–
2. When the control signal Transmitter Enable, Tx_EN, is used to disable the transmitter, Tx_EN must be taken to a logic low-state level (VIL) for
one millisecond or longer. Similarly, if the control signal Transmitter Disable, Tx_DIS, is used, then Tx_DIS must be taken to a logic high- state
level (VIH) for one millisecond or longer.
6
Receiver Electrical Characteristics
(T = 0 °C to +80 °C, V = 3.3 V 5%, Typical T = +40 °C, V = 3.3 V)
C
CC
C
CC
Reference
(Conditions)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Current
ICCR
400
445
mA
1, Fig. 5
Power Dissipation
PDISR
ZOUT
Data Output Differential Peak-to-Peak Volt- DVD-
1.3
1.55
120
750
W
W
Differential Output Impedance
80
100
600
2, Fig. 8, 10
3, Figs. 7, 8
450
mVP-P
age Swing
OUTP-P
Inter-channel Skew
100
110
150
150
ps
ps
4
5
Differential Data Output Rise/Fall Time
tr/tf
Signal Detect
Assert Time (OFF-to-ON)
De-assert Time (ON-to-OFF)
tSDA
tSDD
170
190
µs
µs
6
7
Control I/O
Output Voltage LowLVTTL & LVCMOS
Output Voltage HighCompatible
VOL
VOH
VEE
2.5
3.1
0.4
VCC
V
V
(IOL = 4.0 mA)
(IOH = -0.5 mA)
Notes:
1.
I R is the dc supply current, dependent upon the number of active channels, where the Data Outputs are ac coupled with capacitors be-
CC
tween the outputs and any resistive terminations. See Figure 7 for recommended termination.
2. Measured over the range 4 MHz to 2 GHz.
3. DV = DV – DV , where DV
= High State Differential Data Output Voltage and DV = Low State Differential Data
DOUTL
DOUTP-P
DOUTH
DOUTL
DOUTH
Output Voltage. DV
and DV
= V
– V , measured with a 100 W differential load connected with the recommended cou-
DOUT–
DOUTH
DOUTL
DOUT+
pling capacitors and with a 2500 MBd, 8B10B serial encoded data pattern.
4. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals. Input power at –10 dBm.
5. Rise and Fall Times are measured between the 20% and 80% levels using a 500 MHz square wave signal.
6. The Signal Detect output will change from logic “0”(Low) to “1”(High) within the specified assert time for a step transition in optical input
power from the de-asserted condition to the specified asserted optical power level on all 12 channels.
7. The Signal Detect output will change from logic “1”(High) to “0”(Low) within the specified de-assert time for a step transition in optical input
power from the specified asserted optical power level to the de-asserted condition on any 1 channel.
7
Optical Characteristics
Transmitter Optical Characteristics
(T = 0 °C to +80 °C, V = 3.3 V 5%, Typical T = +40 °C, V = 3.3 V)
C
CC
C
CC
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
POUT
–1
dBm avg.
1
Output Optical Power – Off State
Optical Modulation Amplitude
POUT DIS
OMA
–30
dBm avg.
dBm
-9.84
830
Center Wavelength
Spectral Width – rms
lC
s
850
0.4
860
nm
0.85
nm rms
Rise/Fall Time
tr/tf
50
150
ps
2
3
Inter-channel Skew
Relative Intensity Noise
110
200
ps
RIN
–124
dB/Hz
Jitter Contribution
Deterministic
Total
DJ
TJ
80
162
psp-p
psp-p
4
5
Notes:
1. The specified optical output power, measured at the output of a short test cable, will be compliant with IEC 60825-1 Amendment 2, Class
1 Accessible Emission Limits, AEL, and the output power of the module without an attached cable will be compliant with the IEC 60825-1
Amendment 2, Class 1M AEL. See discussion in the Regulatory Compliance section.
2. These are unfiltered 20-80% value measured with optical-electrical converter with 12 GHz bandwidth. To increase accuracy of measurement
owning to laser overshoot and ringing, a filtered rise/fall time measurement is adopted with a 2.5Gbps (1.875 GHz bandwidth) 4th Bessel
Thompson filter. A max spec of 150 ps for unfiltered waveform is equivalent to a max spec 242 ps for filtered waveform.
3. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals.
4. Deterministic Jitter (DJ) is defined as the combination of Duty Cycle Distortion (Pulse-Width Distortion) and Data Dependent Jitter. Determin-
istic Jitter is measured at the 50% signal threshold level using a 2.5 GBd K28.5, or equivalent, test pattern with zero skew between the differ-
ential data input signals.
-12
5. Total Jitter (TJ) includes Deterministic Jitter and Random Jitter (RJ). Total Jitter is specified at a BER of 10 for the same 2.5 GBd test pattern
as for DJ.
8
Receiver Optical Characteristics
(T = 0 °C to +80 °C, V = 3.3 V 5%, Typical T = +40 °C, V = 3.3 V)
C
CC
C
CC
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Input Optical Power Sensitivity (OMA) PIN MIN
-13
dBm
1
Input Optical Power Saturation (OMA) PIN MAX
–1.22
830
dBm
nm
dBm
ps
2
Operating Center Wavelength
Stressed Receiver Sensitivity (OMA)
Stressed Receiver Eye Opening
Return Loss
lC
860
-11.8
3
4
5
120
12
19
dB
Signal Detect
Asserted (OMA)
De-asserted (OMA)
Hysteresis
PA
PD
PA-PD
-15
dBm
dBm
dB
6
-35
0.5
-21
2
Notes:
-12
1. Sensitivity is defined as the OMA necessary to produce a BER of 10 at the center of the Baud interval using a 2.5 GBd Pseudo Random
7
Bit Sequence of length 2 – 1 (PRBS), or equivalent, test pattern. For this parameter, input power is equivalent to that provided by an ideal
source, i.e., a source with RIN and switching attributes that do not degrade the sensitivity measurement. All channels not under test are oper-
ating receiving data with an average input power up to 6 dB above P
.
IN MIN
2. Saturation is defined as the OMA that produces at the center of the output swing a receiver output eye width less than 120 ps where BER <
-12
7
10 using a 2.5 GBd Pseudo Random Bit Sequence of length 2 –1 (PRBS), or equivalent, test pattern.
-12
3. Stressed receiver sensitivity is defined as the average input power necessary to produce a BER < 10 at the center of the Baud interval using
7
a 2.5 GBd Pseudo Random Bit Sequence of length 2 – 1 (PRBS), or equivalent, test pattern. For this parameter, input power is conditioned
with 2.5 dB Inter-Symbol Interference, ISI, (min), 120 ps Total Jitter, TJ (min). All channels not under test are operating receiving data with an
average input power up to 6 dB above P
4. Stressed receiver eye opening is defined as the receiver output eye width where BER < 10 at the center of the output swing using a 2.5 GBd
.
IN MIN
-12
7
Pseudo Random Bit Sequence of length 2 – 1 (PRBS), or equivalent, test pattern. For this parameter, input power is an average input optical
power of –10.4 dBm and conditioned with 1.2 dB ISI (min), 120 ps TJ (min), All channels not under test are operating receiving data with an
average input power up to 6 dB above P
.
IN MIN
5. Return loss is defined as the ratio, in dB, of the received optical power to the optical power reflected back down the fiber.
6. Signal Detect assertion requires all optical inputs to exhibit a minimum -15 dBm OMA. All channels not under test are operating with PRBS 7
serial encoded patterns, asynchronous with the channel under test, and an average input power up to 6 dB higher than P
IN MIN.
9
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge
(ESD) to the Electrical
Pads
JEDEC Human Body Model (HBM)
(JESD22-A114-B)
Transmitter Module > 1000 V
Receiver Module > 2000 V
JEDEC Machine Model (MM)
Variation of IEC 61000-4-2
Transmitter Module > 50 V
Receiver Module > 200 V
Electrostatic Discharge
(ESD) to the Connector
Receptacle
Typically withstands at leasr 6 kV air discharge
(with module biased) without damage.
Electromagnetic
Interference (EMI)
FCC Part 15 CENELEC EN55022
(CISPR 22A) VCCI Class 1
Typically pass with 10 dB margin. Actual perfor-
mance dependent on enclosure design.
Immunity
Variation of IEC 61000-4-3
Typically minimal effect from a 10 v/m field swept
from 80 MHz to 1 GHz applied to the module
without a chassis enclosure.
Laser Eye Safety and
Equipment Type Testing CFR 21 Section 1040
IEC 60825-1 Amendment 2
POUT: IEC AEL & US FDA CRDH Class 1M
CDRH Accession Number: 9720151-22
TUV Certficate Number: E2171095.04
Component
Recognition
Underwriters Laboratories and Canadian Stan-
UL File Number: E173874
dards Association Joint Component Recogni-
tion for Information Technology Equipment
including Electrical Business Equipment
RoHS Complaince
Less than 1000ppm of Cadmium, lead, mercury,
hexavalent chromium, polybrominated biphe-
nyls, and polybrominated biphenyl ethers
10
Table 1. Transmitter Module Pad Description
Symbol
Functional Description
VEE
Transmitter Signal Common. All voltages are referenced to this potential unless otherwise indi-
cated. Directly connect these pads to transmitter signal ground plane.
VCC
T
Transmitter Power Supply. Use recommended power supply filter circuit in Figure 6.
DIN0+ through DIN11+
DIN0– through DIN11–
TX_EN
Transmitter Data In+ for channels 0 through 11, respectively. Differential termination and self bias
are included, see Figure 11.
Transmitter Data In- for channels 0 through 11, respectively. Differential termination and self bias
are included; see Figure 11.
TX Enable. Active high. Internal pull-up High = VCSEL array is enabled if TX_DIS is inactive (Low).
Low = VCSEL array is off. TX_EN must be taken to a logic low state level (VOL) for 1 ms or longer.
TX_DIS
TX Disable. Active high. Internal pull-down Low = VCSEL array is enabled if TX_EN is active (High).
High = VCSEL array is off. TX_DIS must be taken to a logic High state level (VOH) for 1 ms or longer.
RESET-
Transmitter RESET- input. Active low. Internal pull-up. Low = Resets logic functions, clears FAULT-
signal, VCSEL array is off. high = Normal operation. See Figure 14.
FAULT-
Transmitter FAULT- output. Active low. Low (logic “0”) results from a VCSEL over-current condi-
tion, out of temperature range, or EEPROM calibration data corruption condition detected for any
VCSEL. An asserted (logic “0”) FAULT- disables the VCSEL array and is cleared by RESET- or power
cycling VCCT FAULT- is a single ended LVTTL compatible output.
DNC
Do not connect to any electrical potential.
Table 2. Receiver Module Pad Description
Symbol
Functional Description
VEE
Receiver Signal Common. All voltages are referenced to this potential unless otherwise indicated.
Directly connect these pads to receiver signal ground plane.
VCC
R
Receiver Power Supply. Use recommended power supply filter circuit in Figure 5.
Not required for Avago product. Pads not internally connected
VPP
DOUT0+ through
DOUT11+
Receiver Data Out+ for channels 0 through 11, respectively. Terminate these high-speed differen-
tial CML outputs with standard CML techniques at the inputs of the receiving device. Individual
data outputs will be squelched for insufficient input signal level.
DOUT0– through
DOUT11–
Receiver Data Out- for channel 0 through 11, respectively. Terminate these high-speed differen-
tial CML outputs with standard CML techniques at the inputs of the receiving device. Individual
data outputs will be squelched for insufficient input signal level.
SD
Signal Detect. Normal optical input levels to all channels results in a logic “1”output, VOH, as-
serted. Low input optical levels to any channel results in a fault condition indicated by a logic “0”
output, VOL, de-asserted. SD is a single-ended LVTTL compatible output.
RX_EN
SQ_EN
EN_SD
DNC
Receiver output enable. Active high (logic “1”), internal pull-up. Low (logic “0”) = receiver outputs
disabled, all outputs are high (logic “1”).
Squelch enable input. Active high (logic “1”), internal pull-up. Low (logic “0”) = squelch disabled.
When SQ_EN is high and SD is low, corresponding outputs are squelched.
Enable Signal Detect. Active high (logic “1”), internal pull-up. Low (logic “0”) = Signal detect
output forced active high.
Do not connect to any electrical potential.
11
TRANSMITTER MODULE PAD ASSIGNMENT
(TOWARD MTP® CONNECTOR)
J
I
H
G
F
E
D
C
B
A
1
2
DNC
DNC
DNC
V
V
V
V
V
V
V
V
V
V
DNC
EE
EE
EE
EE
EE
EE
EE
EE
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
V
V
DIN5+
DIN8+
V
V
EE
EE
EE
EE
EE
EE
3
V
V
DIN4+ DIN5-
DIN7+ DIN8-
CCT
CCT
CCT
CCT
CCT
CCT
CCT
CCT
4
V
V
V
V
V
V
DIN3+ DIN4-
V
DIN6+ DIN7-
V
DNC
EE
EE
5
DIN3-
V
DIN2+ DIN6-
V
DIN9-
V
V
EE
EE
EE
EE
6
V
DIN1+ DIN2-
V
DIN10- DIN9+
EE
EE
7
DNC
DNC
DIN0+ DIN1-
V
V
V
DIN11- DIN10+
V
V
V
DNC
DNC
DNC
DNC
EE
EE
EE
EE
EE
EE
8
RESET- FAULT-
TX_EN TX_DIS
DIN0-
V
V
DIN11+
V
V
EE
EE
EE
EE
9
V
V
EE
EE
10
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
TOP VIEW (PCB LAYOUT)
(10 x 10 ARRAY)
12
RECEIVER MODULE PAD ASSIGNMENT
(TOWARD MTP® CONNECTOR)
J
I
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
V
V
DNC
DNC
V
V
V
V
V
V
V
V
V
V
DNC
PP
EE
EE
EE
EE
EE
EE
EE
EE
DNC
DNC
V
V
DOUT5-
DOUT8-
V
V
PP
EE
EE
EE
EE
EE
EE
DNC
DNC
DNC
DNC
DNC
V
V
DOUT4- DOUT5+
DOUT7- DOUT8+
CCR
CCR
CCR
CCR
CCR
CCR
V
V
V
V
V
V
DOUT3- DOUT4+
V
DOUT6- DOUT7+
V
DNC
EE
EE
DOUT3+
V
DOUT2- DOUT6+
V
DOUT9+
V
V
CCR
CCR
SD
EE
EE
EE
EE
V
DOUT1- DOUT2+
V
DOUT10+ DOUT9-
EE
EE
DNC
DNC
DOUT0- DOUT1+
V
V
V
DOUT11+ DOUT10-
V
V
V
DNC
DNC
DNC
DNC
EE
EE
EE
EE
EE
EE
V
V
DNC
DOUT0+
V
V
DOUT11-
V
V
PP
PP
EE
EE
EE
EE
RX_EN EN_SD
V
V
EE
EE
10 SQ_EN
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
TOP VIEW (PCB LAYOUT)
(10 x 10 ARRAY)
13
Case Temperature Measurement Point
Figure 3. Case temperature measurement. (label and heatsink removed for clarity)
25.0
No Heatsink
Heatsink
20.0
15.0
10.0
5.0
0.0
0.5
0
1.0
2
1.5
Air Velocity (m/s)
Figure 4. Case to Ambient thermal resistance (C/W) versus air velocity (sea level)
14
R = 1.0 kΩ
R = 100Ω
AFBR-742BZ
0603
0603
V
V
V
V
V
V
V
V
CCR
CCR
CCR
CCR
CCR
CCR
CCR
CCR
V
CC
L = 6.8 nH
0805
L = 1 µH
2220
C = 0.1 µF
0603
C = 0.1 µF
0603
C = 10 µF
1210
C = 10 µF
1210
NOTE:
1. V IS DEFINED BY 3.135 < V < 3.465 VOLTS AND THE POWER SUPPLY FILTER HAS < 50 mV DROP
CC CC
ACROSS IT RESULTING IN 3.085 < V
< 3.415 VOLTS.
CCR
Figure 5. Recommended receiver power supply filter.
R = 1.0 k
0603
R = 100
0603
AFBR-732BWZ
V
V
V
V
V
V
V
V
CCT
CCT
CCT
CCT
CCT
CCT
CCT
CCT
V
CC
L = 6.8 nH
0805
L = 1 µH
2220
C = 0.1 µF
0603
C = 0.1 µF
0603
C = 10 µF
1210
C = 10 µF
1210
NOTE:
IS DEFINED BY 3.135 < V
V
< 3.465 VOLTS AND THE POWER SUPPLY FILTER HAS < 50 mV DROP
CC
CC
ACROSS IT RESULTING IN 3.085 < V
< 3.415 VOLTS.
CCT
Figure 6. Recommended transmitter power supply filter.
15
AFBR-732BWZ
DATA OUT (+)
DATA OUT (–)
R
50
C = 100 nF
C = 100 nF
R
100
R
50
AFBR-742BZ
ASIC
D
OUT
(+)
UNUSED RECEIVER
CHANNEL OUTPUTS
MUST BE TERMINATED.
C = 100 nF
RDL
100
D
OUT
(–)
C = 100 nF
NOTE:
AC COUPLING CAPACITORS SHOULD BE USED TO CONNECT DATA OUTPUTS
TO DATA INPUTS BETWEEN THE AFBR-732BWZ, AFBR-742BZ, AND HOST BOARD
ICs (e.g., ASIC) WITH EITHER 50WSINGLE-ENDED OR 100 DIFFERENTIAL
TERMINATIONS AS SHOWN. THE CAPACITORS' VALUES CAN BE REDUCED FROM
100 nF (0603 SIZE) IF THE DATA RATE AND RUN LENGTH ARE LIMITED.
Figure 7. Recommended ac coupling and data signal termination.
V
D
+
DI/O+
IN+
∅V
TRANSMITTER
DIN
∅V
∅V
DI/OL
DI/OH
–
D
IN–
V
DI/O–
D
D
OUT+
+
∅V
RECEIVER
DOUT
∅V
∅V
DI/OH
DI/OL
+
–
∅V
DI/O P-P
–
OUT–
V
REFERS TO
DI/O
EITHER V
OR V
DIN
AS APPROPRIATE
DOUT
Figure 8. Differential signals.
16
2 x ∅2.54 MIN. PAD KEEP-OUT
∅0.1 A B-C
2 x ∅1.7 0.05 HOLES
∅0.1 A B-C
3 x ∅4.17 MIN. PAD KEEP-OUT
∅0.1 A B-C
5.46
B
3 x ∅2.69 0.05 HOLES
A
FOR #2 SCREW
∅0.1 A B-C
Rx
SYM.
13.72
18 REF.
100 PIN FCI
MEG-Array® RECEPTACLE
CONNECTORS
18.42 MIN.
C
Tx
9 x 1.27 TOT = 11.43
SYM.
END OF
MODULE
FRONT
(10 x 10 =) 100 x∅ 0.58 0.05 PADS
∅0.05 A B-C
8.00
50
9 x 1.27 TOT = 11.43
1.89 REF.
KEEP-OUT AREA
FOR MPO CONNECTOR
30.23
8.95 REF.
PCB LAYOUT
(TOP VIEW)
NOTE:
The host electrical connector attached to the PCB must be a 100-position FCI Meg-Array plug (FCI PN: 84512-102) or equivalent.
Figure 9. Package board footprint (dimensions in mm). PCB top view.
17
V
CCR
V
CCT
50
50
D
IN+
D
D
OUT+
OUT–
50
50
V
Z
BIAS
(NOMINAL 1.7 V)
IN
D
IN–
V
EE
V
EE
Figure 10. Rx data output equivalent circuit.
Figure 11. Tx data input equivalent circuit.
V
> 2.8 V
CC
V
CC
~60 ms
~6.5 ms
~4.6 ms
SHUTDOWN
SHUTDOWN
SHUTDOWN
NORMAL
NORMAL
NORMAL
TX OUT 0
TX OUT 1
~4.6 ms
TX OUT 2
SHUTDOWN
NORMAL
TX OUT 11
Figure 12. Typical transmitter power-up sequence.
NO FAULT DETECTED
FAULT DETECTED
~100 ns
~Toff
<200 µs
-FAULT
TX OUT CH 0-11
Figure 13. Transmitter FAULT signal timing diagram.
18
RESET
FAULT
> 100 ns
~4.2 ms
(Ton)
~55 ms
SHUTDOWN
~4.6 ms
NORMAL
TX OUT 0
TX OUT 1
~4.6 ms
TX OUT 2
TX OUT 11
~5 µs (Toff)
Figure 14. Transmitter RESET timing diagram.
TX_EN
TX_DIS
~5 µs (Toff)
~5 µs (Toff)
SHUTDOWN
TX OUT
CH 0-11
TX OUT
CH 0-11
NORMAL
(a)
SHUTDOWN
NORMAL
(b)
NOTE [1]: TX_DIS, WHICH IS
NOT SHOWN, IS THE
FUNCTIONAL COMPLIMENT
OF TX_EN.
[1]
(Ton)
TX_EN
~55 ms
~4.6 ms
~4.2 ms
TX OUT CH 0
TX OUT CH 1
TX OUT
CH 11
(c)
Figure 15. Transmitter TX_EN and TX_DIS timing diagram.
19
Module Outline
Notes:
1. Module supplied with port process plug.
2. Module mass approximately 20 grams.
Figure 16. Package outline for AFBR-732BWZ and AFBR-742BZ (dimensions in mm).
20
Notes:
1. Module supplied with port process plug.
2. Module mass approximately 20 grams.
Figure 17. Package Outline for AFBR-732BEWZ and AFBR-742BEZ (dimensions in mm)
21
Figure 18. Host Frontplate Layout (dimensions in mm)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-1157EN - January 29, 2013
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