TISP2072F3SL [BOURNS]
Silicon Surge Protector, 72V V(BO) Max, 6A, PLASTIC, SIP-3;
| 型号： | TISP2072F3SL |
| 厂家： | 
BOURNS ELECTRONIC SOLUTIONS |
| 描述： | Silicon Surge Protector, 72V V(BO) Max, 6A, PLASTIC, SIP-3 |
| 文件： | 总17页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
Copyright © 1997, Power Innovations Limited, UK
MARCH 1994 - REVISED SEPTEMBER 1997
TELECOMMUNICATION SYSTEM SECONDARY PROTECTION
●
Ion-Implanted Breakdown Region
Precise and Stable Voltage
D PACKAGE
(TOP VIEW)
Low Voltage Overshoot under Surge
1
2
3
4
8
7
6
5
G
G
G
G
T
NC
NC
R
VDRM V(BO)
DEVICE
V
V
‘2072F3
‘2082F3
58
66
72
82
MDXXAE
NC - No internal connection
●
●
Planar Passivated Junctions
Low Off-State Current < 10 µA
P PACKAGE
(TOP VIEW)
Rated for International Surge Wave Shapes
T
1
2
8
7
T
ITSP
G
G
WAVE SHAPE
STANDARD
A
3
4
G
R
6
5
G
R
2/10 µs
8/20 µs
FCC Part 68
ANSI C62.41
FCC Part 68
FCC Part 68
RLM 88
80
70
60
45
38
50
50
50
35
MDXXAF
10/160 µs
10/560 µs
0.5/700 µs
Specified T terminal ratings require connection of pins 1 and 8.
Specified R terminal ratings require connection of pins 4 and 5.
FTZ R12
SL PACKAGE
(TOP VIEW)
10/700 µs
VDE 0433
CCITT IX K17/K20
REA PE-60
10/1000 µs
1
2
3
T
G
R
●
Surface Mount and Through-Hole Options
PACKAGE
Small-outline
Small-outline taped
and reeled
PART # SUFFIX
D
MDXXAG
MD23AA
DR
device symbol
Plastic DIP
P
T
R
Single-in-line
SL
●
UL Recognized, E132482
description
These low voltage dual symmetrical transient
voltage suppressor devices are designed to
protect ISDN applications against transients
caused by lightning strikes and a.c. power lines.
Offered in two voltage variants to meet battery
and protection requirements they are guaranteed
to suppress and withstand the listed international
lightning surges in both polarities. Transients are
initially clipped by breakdown clamping until the
voltage rises to the breakover level, which
causes the device to crowbar. The high crowbar
holding current prevents d.c. latchup as the
current subsides.
SD2XAA
G
Terminals T, R and G correspond to the
alternative line designators of A, B and C
These monolithic protection devices are
fabricated in ion-implanted planar structures to
ensure precise and matched breakover control
and are virtually transparent to the system in
normal operation
P R O D U C T
I N F O R M A T I O N
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
description (Continued)
The small-outline 8-pin assignment has been carefully chosen for the TISP series to maximise the inter-pin
clearance and creepage distances which are used by standards (e.g. IEC950) to establish voltage withstand
ratings.
absolute maximum ratings
RATING
SYMBOL
VALUE
± 58
UNIT
‘2072F3
‘2082F3
Repetitive peak off-state voltage (0°C < TJ < 70°C)
VDRM
V
± 66
Non-repetitive peak on-state pulse current (see Notes 1, 2 and 3)
1/2 µs (Gas tube differential transient, open-circuit voltage wave shape 1/2 µs)
2/10 µs (FCC Part 68, open-circuit voltage wave shape 2/10 µs)
120
80
8/20 µs (ANSI C62.41, open-circuit voltage wave shape 1.2/50 µs)
10/160 µs (FCC Part 68, open-circuit voltage wave shape 10/160 µs)
5/200 µs (VDE 0433, open-circuit voltage wave shape 2 kV, 10/700 µs)
0.5/310 µs (RLM 88, open-circuit voltage wave shape 1.5 kV, 0.5/700 µs)
5/310 µs (CCITT IX K17/K20, open-circuit voltage wave shape 2 kV, 10/700 µs)
5/310 µs (FTZ R12, open-circuit voltage wave shape 2 kV, 10/700 µs)
10/560 µs (FCC Part 68, open-circuit voltage wave shape 10/560 µs)
10/1000 µs (REA PE-60, open-circuit voltage wave shape 10/1000 µs)
70
60
ITSP
50
A
38
50
50
45
35
Non-repetitive peak on-state current (see Notes 2 and 3)
50 Hz, 1 s
D Package
4
P Package
ITSM
6
6
A rms
SL Package
Initial rate of rise of on-state current, Linear current ramp, Maximum ramp value < 38 A
diF/dt
TJ
250
A/µs
°C
Junction temperature
-40 to +150
-40 to +150
Storage temperature range
Tstg
°C
NOTES: 1. Further details on surge wave shapes are contained in the Applications Information section.
2. Initially the TISP must be in thermal equilibrium with 0°C < TJ <70°C. The surge may be repeated after the TISP returns to its initial
conditions.
3. Above 70°C, derate linearly to zero at 150°C lead temperature.
electrical characteristics for the T and R terminals, T = 25°C
J
TISP2072F3
TISP2082F3
PARAMETER
TEST CONDITIONS
VD = ±VDRM, 0°C < TJ < 70°C
UNIT
MIN
MAX
MIN
MAX
Repetitive peak off-
state current
IDRM
ID
±10
±10
mA
Off-state current
VD = ±50 V
±10
±10
µA
f = 100 kHz, Vd = 100 mV VD = 0,
Coff
Off-state capacitance
Third terminal voltage = 0
(see Notes 4 and 5)
32†
55
32†
55
pF
NOTES: 4. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The third terminal is
connected to the guard terminal of the bridge.
5. Further details on capacitance are given in the Applications Information section.
† Typical value of the parameter, not a limit value.
electrical characteristics for the T and G or the R and G terminals, T = 25°C
J
TISP2072F3
TISP2082F3
PARAMETER
TEST CONDITIONS
VD = ±VDRM, 0°C < TJ < 70°C
UNIT
MIN
MAX
MIN
MAX
Repetitive peak off-
state current
IDRM
±10
±10
mA
P R O D U C T
I N F O R M A T I O N
2
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
electrical characteristics for the T and G or the R and G terminals, T = 25°C (Continued)
J
TISP2072F3
TISP2082F3
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
dv/dt = ±250 V/ms,
V(BO) Breakover voltage
±72
±82
V
Source Resistance = 300 W
dv/dt = ±1000 V/µs, di/dt < 20 A/µs
Impulse breakover volt-
V(BO)
age
±84†
±94†
V
A
Source Resistance = 50 W
dv/dt = ±250 V/ms,
I(BO)
Breakover current
±0.15
±0.6
±3
±0.15
±0.6
±3
Source Resistance = 300 W
IT = ±5 A, tW = 100 µs
di/dt = -/+30 mA/ms
VT
IH
On-state voltage
Holding current
V
A
±0.15
±5
±0.15
±5
Linear voltage ramp,
Critical rate of rise of
off-state voltage
dv/dt
ID
kV/µs
Maximum ramp value < 0.85V(BR)MIN
VD = ±50 V
Off-state current
±10
130
70
±10
130
70
µA
pF
pF
pF
f = 100 kHz, Vd = 100 mV VD = 0,
77†
42†
19†
77†
42†
19†
Coff
Off-state capacitance
Third terminal voltage = 0
(see Notes 6 and 7)
VD = -5 V
VD = -50 V
30
30
NOTES: 6 These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The third terminal is
connected to the guard terminal of the bridge.
7. Further details on capacitance are given in the Applications Information section.
PARAMETER MEASUREMENT INFORMATION
+i
Quadrant I
ITSP
Switching
Characteristic
ITSM
IT
V(BO)
VT
I(BO)
IH
V(BR)
I(BR)
V(BR)M
IDRM
VDRM
VD
ID
+v
-v
ID
VD
VDRM
I(BR)
V(BR)
IDRM
V(BR)M
IH
I(BO)
VT
V(BO)
IT
ITSM
Quadrant III
ITSP
Switching
Characteristic
-i
PMXXAA
Figure 1. VOLTAGE-CURRENT CHARACTERISTIC FOR ANY PAIR OF TERMINALS
The high level characteristics for terminals R and T are not guaranteed.
P R O D U C T
I N F O R M A T I O N
3
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
† Typical value of the parameter, not a limit value.
thermal characteristics
MIN
TYP
MAX
PARAMETER
UNIT
D Package
P Package
SL Package
160
100
105
RqJA
Junction to free air thermal resistance
°C/W
TYPICAL CHARACTERISTICS
T and G, or R and G terminals
OFF-STATE CURRENT
vs
NORMALISED BREAKDOWN VOLTAGES
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
TC2LAO
TC2LAL
100
10
1
Normalised to V(BR)
I(BR) = 100 µA and 25°C
1.2
1.1
1.0
0.9
Positive Polarity
VD = 50 V
V(BR)M
0·1
VD = -50 V
V(BO)
V(BR)
0·01
0·001
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 2.
Figure 3.
P R O D U C T
I N F O R M A T I O N
4
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
T and G, or R and G terminals
NORMALISED BREAKDOWN VOLTAGES
ON-STATE CURRENT
vs
vs
JUNCTION TEMPERATURE
ON-STATE VOLTAGE
TC2MAQ
TC2LAP
100
10
1
Normalised to V(BR)
I(BR) = 100 µA and 25°C
Negative Polarity
1.2
1.1
1.0
0.9
V(BR)M
V(BO)
150°C
V(BR)
25°C
-40°C
-25
0
25
50
75
100
125
150
1
2
3
4
5
6
7
8 9 10
TJ - Junction Temperature - °C
VT - On-State Voltage - V
Figure 4.
Figure 5.
HOLDING CURRENT & BREAKOVER CURRENT
vs
NORMALISED BREAKOVER VOLTAGE
vs
JUNCTION TEMPERATURE
RATE OF RISE OF PRINCIPLE CURRENT
TC2LAM
TC2LAF
1.0
0.9
0.8
1.3
1.2
1.1
1.0
0.7
0.6
I(BO)
0.5
0.4
0.3
IH
0.2
0.1
Positive
Negative
10
-25
0
25
50
75
100
125
150
0·001
0·01
0·1
1
100
TJ - Junction Temperature - °C
di/dt - Rate of Rise of Principle Current - A/µs
Figure 6.
Figure 7.
P R O D U C T
I N F O R M A T I O N
5
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
T and G, or R and G terminals
OFF-STATE CAPACITANCE
OFF-STATE CAPACITANCE
vs
vs
TERMINAL VOLTAGE (POSITIVE)
TERMINAL VOLTAGE (NEGATIVE)
TC2LAB
TC2LAD
Third Terminal Bias = -50 V
Third Terminal Bias = 0
Third Terminal Bias = -50 V
Third Terminal Bias = 0
100
10
1
100
10
1
Third Terminal Bias = 50 V
Third Terminal Bias = 50 V
0·1
1
10
0·1
1
10
50
50
Terminal Voltage (Positive) - V
Terminal Voltage (Negative) - V
Figure 8.
Figure 9.
OFF-STATE CAPACITANCE
vs
JUNCTION TEMPERATURE
TC2LAH
100
Third Terminal Bias = 50 V
Terminal Bias = 50 V
Terminal Bias = 0
10
1
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 10.
P R O D U C T
I N F O R M A T I O N
6
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
T and G, or R and G terminals
OFF-STATE CAPACITANCE
OFF-STATE CAPACITANCE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
TC2LAI
TC2LAJ
500
500
Third Terminal Bias = -50 V
Third Terminal Bias = 0
100
100
Terminal Bias = 0
Terminal Bias = 0
Terminal Bias = 50 V
Terminal Bias = -50 V
Terminal Bias = -50 V
10
10
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 11.
Figure 12.
SURGE CURRENT
vs
DECAY TIME
TC2LAA
1000
100
10
2
10
100
1000
Decay Time - µs
Figure 13.
P R O D U C T
I N F O R M A T I O N
7
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
T and R terminals
OFF-STATE CURRENT
vs
NORMALISED BREAKDOWN VOLTAGES
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
TC2LAK
TC2LAN
100
10
VD = ±50 V
Normalised to V(BR)
I(BR) = 100 µA and 25°C
1.2
1.1
1.0
0.9
Both Polarities
V(BR)M
1
0·1
V(BO)
V(BR)
0·01
0·001
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 14.
Figure 15.
NORMALISED BREAKOVER VOLTAGE
vs
RATE OF RISE OF PRINCIPLE CURRENT
TC2LAG
2.5
2.0
1.5
1.0
0·001
0·01
0·1
1
10
100
di/dt - Rate of Rise of Principle Current - A/µs
Figure 16.
P R O D U C T
I N F O R M A T I O N
8
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
T and R terminals
OFF-STATE CAPACITANCE
vs
OFF-STATE CAPACITANCE
vs
TERMINAL VOLTAGE (POSITIVE)
TERMINAL VOLTAGE (NEGATIVE)
TC2LAC
TC2LAE
100
10
1
100
10
1
Third Terminal Bias = -50 V
Third Terminal Bias = -50 V
Third Terminal Bias = 0
Third Terminal Bias = 0
Third Terminal Bias = 50 V
1
Third Terminal Bias = 50 V
1
0·1
10
0·1
10
50
50
Terminal Voltage (Positive) - V
Terminal Voltage (Negative) - V
Figure 17.
Figure 18.
THERMAL INFORMATION
MAXIMUM NON-RECURRING 50 Hz CURRENT
vs
THERMAL RESPONSE
CURRENT DURATION
TI2LAA
TI2MAA
VGEN = 250 Vrms
100
10
1
RGEN = 10 to 150 W
SL Package
10
D Package
P Package
P Package
SL Package
D Package
1
0·1
1
10
100
1000
0·0001 0·001 0·01
0·1
1
10
100
1000
t - Current Duration - s
t - Power Pulse Duration - s
Figure 19.
Figure 20.
P R O D U C T
I N F O R M A T I O N
9
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
APPLICATIONS INFORMATION
electrical characteristics
The electrical characteristics of a TISP are strongly dependent on junction temperature, T . Hence a
J
characteristic value will depend on the junction temperature at the instant of measurement. The values given
in this data sheet were measured on commercial testers, which generally minimise the temperature rise
caused by testing. Application values may be calculated from the parameters’ temperature curves, the power
dissipated and the thermal response curve (Z ).
q
lightning surge
wave shape notation
Most lightning tests, used for equipment verification, specify a unidirectional sawtooth waveform which has an
exponential rise and an exponential decay. Wave shapes are classified in terms of peak amplitude (voltage
or current), rise time and a decay time to 50% of the maximum amplitude. The notation used for the wave
shape is amplitude, rise time/decay time. A 50A, 5/310 µs wave shape would have a peak current value of
50 A, a rise time of 5 µs and a decay time of 310 µs. The TISP surge current graph comprehends the wave
shapes of commonly used surges.
generators
There are three categories of surge generator type, single wave shape, combination wave shape and circuit
defined. Single wave shape generators have essentially the same wave shape for the open circuit voltage
and short circuit current (e.g. 10/1000 µs open circuit voltage and short circuit current). Combination
generators have two wave shapes, one for the open circuit voltage and the other for the short circuit current
(e.g. 1.2/50 µs open circuit voltage and 8/20 µs short circuit current) Circuit specified generators usually
equate to a combination generator, although typically only the open circuit voltage waveshape is referenced
(e.g. a 10/700 µs open circuit voltage generator typically produces a 5/310 µs short circuit current). If the
combination or circuit defined generators operate into a finite resistance the wave shape produced is
intermediate between the open circuit and short circuit values.
current rating
When the TISP switches into the on-state it has a very low impedance. As a result, although the surge wave
shape may be defined in terms of open circuit voltage, it is the current wave shape that must be used to
assess the required TISP surge capability. As an example, the CCITT IX K17 1.5 kV, 10/700 µs surge is
changed to a 38 A, 5/310 µs waveshape when driving into a short circuit. Thus the TISP surge current
capability, when directly connected to the generator, will be found for the CCITT IX K17 waveform at 310 µs
on the surge graph and not 700 µs. Some common short circuit equivalents are tabulated below:
STANDARD
OPEN CIRCUIT
VOLTAGE
SHORT CIRCUIT
CURRENT
CCITT IX K17
CCITT IX K20
RLM88
VDE 0433
FTZ R12
1.5 kV, 10/700 µs
1 kV, 10/700 µs
1.5 kV, 0.5/700 µs
2.0 kV, 10/700 µs
2.0 kV, 10/700 µs
38 A, 5/310 µs
25 A, 5/310 µs
38 A, 0.2/310 µs
50 A, 5/200 µs
50 A, 5/310 µs
Any series resistance in the protected equipment will reduce the peak circuit current to less than the
generators’ short circuit value. A 2 kV open circuit voltage, 50 A short circuit current generator has an
effective output impedance of 40 W (2000/50). If the equipment has a series resistance of 25 W then the
surge current requirement of the TISP becomes 31 A (2000/65) and not 50 A.
P R O D U C T
I N F O R M A T I O N
10
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
APPLICATIONS INFORMATION
protection voltage
The protection voltage, (V
), increases under lightning surge conditions due to thyristor regeneration. This
(BO)
increase is dependent on the rate of current rise, di/dt, when the TISP is clamping the voltage in its
breakdown region. The V value under surge conditions can be estimated by multiplying the 50 Hz rate
(BO)
V
(250 V/ms) value by the normalised increase at the surge’s di/dt (Figure 7.) . An estimate of the di/dt
(BO)
can be made from the surge generator voltage rate of rise, dv/dt, and the circuit resistance.
As an example, the CCITT IX K17 1.5 kV, 10/700 µs surge has an average dv/dt of 150 V/µs, but, as the rise
is exponential, the initial dv/dt is higher, being in the region of 450 V/µs. The instantaneous generator output
resistance is 25 W. If the equipment has an additional series resistance of 20 W, the total series resistance
becomes 45 W. The maximum di/dt then can be estimated as 450/45 = 10 A/µs. In practice the
measured di/dt and protection voltage increase will be lower due to inductive effects and the finite slope
resistance of the TISP breakdown region.
capacitance
off-state capacitance
The off-state capacitance of a TISP is sensitive to junction temperature, T , and the bias voltage, comprising
J
of the dc voltage, V , and the ac voltage, V . All the capacitance values in this data sheet are measured
D
d
with an ac voltage of 100 mV. The typical 25°C variation of capacitance value with ac bias is shown in Figure
21. When V >> V the capacitance value is independent on the value of V . The capacitance is essentially
D
d
d
constant over the range of normal telecommunication frequencies.
NORMALISED CAPACITANCE
vs
RMS AC TEST VOLTAGE
AIXXAA
1.05
1.00
0.95
0.90
0.85
0.80
Normalised to Vd = 100 mV
DC Bias, VD = 0
0.75
0.70
1
10
100
1000
Vd - RMS AC Test Voltage - mV
Figure 21.
P R O D U C T
I N F O R M A T I O N
11
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
APPLICATIONS INFORMATION
longitudinal balance
Figure 22 shows a three terminal TISP with its equivalent "delta" capacitance Each capacitance, C
, C
RG
TG
and C , is the true terminal pair capacitance measured with a three terminal or guarded capacitance
TR
bridge. If wire R is biased at a larger potential than wire T then C > C . Capacitance C is equivalent to
TG
RG
TG
a capacitance of C
in parallel with the capacitive difference of (C - C ). The line capacitive unbalance
RG
TG RG
is due to (C - C ) and the capacitance shunting the line is C + C /2 .
TG
RG
TR
RG
Figure 22.
All capacitance measurements in this data sheet are three terminal guarded to allow the designer to
accurately assess capacitive unbalance effects. Simple two terminal capacitance meters (unguarded third
terminal) give false readings as the shunt capacitance via the third terminal is included.
P R O D U C T
I N F O R M A T I O N
12
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
D008
plastic small-outline package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
D008
Designation per JEDEC Std 30:
PDSO-G8
5,00 (0.197)
4,80 (0.189)
8
7
6
5
6,20 (0.244)
5,80 (0.228)
4,00 (0.157)
3,81 (0.150)
1
2
3
4
7° NOM
3 Places
1,75 (0.069)
1,35 (0.053)
5,21 (0.205)
4,60 (0.181)
0,50 (0.020)
0,25 (0.010)
x 45°NOM
0,203 (0.008)
0,102 (0.004)
7° NOM
4 Places
0,51 (0.020)
0,36 (0.014)
8 Places
4° ± 4°
0,79 (0.031)
0,28 (0.011)
Pin Spacing
1,27 (0.050)
(see Note A)
6 Places
0,229 (0.0090)
0,190 (0.0075)
1,12 (0.044)
0,51 (0.020)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
MDXXAA
NOTES: A. Leads are within 0,25 (0.010) radius of true position at maximum material condition.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0,15 (0.006).
D. Lead tips to be planar within ±0,051 (0.002).
P R O D U C T
I N F O R M A T I O N
13
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
P008
plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions The package is intended for
insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted,
sufficient tension is provided to secure the package in the board during soldering. Leads require no
additional cleaning or processing when used in soldered assembly.
P008
Designation per JEDEC Std 30:
PDIP-T8
10,2 (0.400) MAX
8
7
6
5
Index
Dot
C
C
L
L
7,87 (0.310)
7,37 (0.290)
T.P.
1
2
3
4
6,60 (0.260)
6,10 (0.240)
1,78 (0.070) MAX
4 Places
5,08 (0.200)
MAX
Seating
Plane
105°
90°
8 Places
0,51 (0.020)
MIN
3,17 (0.125)
MIN
0,36 (0.014)
0,20 (0.008)
8 Places
2,54 (0.100) T.P.
6 Places
(see Note A)
0,533 (0.021)
0,381 (0.015)
8 Places
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position
MDXXABA
P R O D U C T
I N F O R M A T I O N
14
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
SL003
3-pin plastic single-in-line package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
SL003
4,57 (0.180)
MAX
10,2 (0.400) MAX
6,60 (0.260)
6,10 (0.240)
8,31 (0.327)
MAX
Index
Dot
12,9 (0.492)
MAX
4,267 (0.168)
MIN
1
2
3
Pin Spacing
2,54 (0.100) T.P.
(see Note A)
2 Places
0,356 (0.014)
0,203 (0.008)
3 Places
1,854 (0.073) MAX
0,711 (0.028)
0,559 (0.022)
3 Places
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
MDXXAD
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. Body molding flash of up to 0,15 (0.006) may occur in the package lead plane.
P R O D U C T
I N F O R M A T I O N
15
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
D008
tape dimensions
D008 Package (8 pin SOIC) Single-Sprocket Tape
4,10
3,90
1,60
1,50
8,05
7,95
2,05
1,95
0,40
0,8 MIN.
5,55
5,45
12,30
11,70
Cover
Tape
6,50
6,30
0 MIN.
ø 1,5 MIN.
Carrier Tape
Embossment
2,2
2,0
Direction of Feed
ALL LINEAR DIMENSIONS IN MILLIMETERS
NOTES: A. Taped devices are supplied on a reel of the following dimensions:-
MDXXAT
Reel diameter:
Reel hub diameter:
Reel axial hole:
330 +0,0/-4,0 mm
100 ±2,0 mm
13,0 ±0,2 mm
B. 2500 devices are on a reel.
P R O D U C T
I N F O R M A T I O N
16
TISP2072F3, TISP2082F3
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
MARCH 1994 - REVISED SEPTEMBER 1997
IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the
information being relied on is current.
PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI
deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except as mandated by government requirements.
PI accepts no liability for applications assistance, customer product design, software performance, or infringement
of patents or services described herein. Nor is any license, either express or implied, granted under any patent
right, copyright, design right, or other intellectual property right of PI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.
Copyright © 1997, Power Innovations Limited
P R O D U C T
I N F O R M A T I O N
17
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