BH616UV8010AIG70 [BSI]
Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit; 超低功耗/高速CMOS SRAM 512K ×16位
| 型号： | BH616UV8010AIG70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit |
| 文件： | 总11页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/High Speed CMOS SRAM
512K X 16 bit
BSI
BH616UV8010
n FEATURES
n DESCRIPTION
ŸWide VCC low operation voltage : 1.65V ~ 3.6V
The BH616UV8010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 by 16 bits and operates
in a wide range of 1.65V to 3.6V supply voltage.
ŸUltra low power consumption :
VCC = 3.0V
VCC = 2.0V
Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 2.5uA at 25OC
Data retention current : 2.5uA at 25OC
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
ŸHigh speed access time :
-70
70ns at 1.8V at 85OC
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE1, CE2 and OE options
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
ŸThree state outputs and TTL compatible
ŸFully static operation, no clock, no refreash
ŸData retention supply voltage as low as 1.0V
The BH616UV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH616UV8010 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
n PRODUCT FAMILY
POWER CONSUMPTION
SPEED
(ns)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
STANDBY
Operating
(ICC, Max)
PKG TYPE
(ICCSB1, Max)
VCC=1.8~3.6V
70
VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
+0OC to +70OC
-25OC to +85OC
13uA
15uA
10uA
12uA
10mA
10mA
7mA
7mA
BH616UV8010DI
BH616UV8010TI
BH616UV8010AI
DICE
1.65V ~ 3.6V
TSOP1-48
70
BGA-48-0608
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A12
A11
A10
A8
8
A9
A8
A7
A6
A5
A4
A3
Address
Input
1024
Memory Array
1024 x 8192
10
NC
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Row
Decoder
Buffer
BH616UV8010TC
BH616UV8010TI
8192
DQ0
Column I/O
16
16
Data
.
.
.
.
.
.
.
Input
Buffer
.
VSS
CE1
A0
Write Driver
Sense Amp
.
16
16
.
Data
Output
Buffer
.
.
512
1
2
3
4
5
6
Column Decoder
DQ15
A
B
C
D
E
F
LB
OE
A0
A1
A2
CE2
9
CE2
CE1
WE
OE
UB
DQ8
UB
A3
A5
A4
A6
CE1
DQ1
DQ3
DQ4
DQ5
WE
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
Address Input Buffer
Control
DQ9 DQ10
VSS DQ11
LB
A18 A17 A15 A14 A13 A16 A2 A1 A0
A17
A7
VCC
VSS
VCC DQ12 VSS
DQ14 DQ13 A14
A16
A15
A13
A10
G
H
DQ15
A18
NC
A8
A12
A9
A11
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
1
BSI
BH616UV8010
n PIN DESCRIPTIONS
Name
Function
These 19 address inputs select one of the 524,288 x 16 bit in the RAM
A0-A18 Address Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
CE1
CE2
WE
X
LB
X
X
H
X
L
UB
X
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
OE
X
H
X
X
L
X
L
High Z
High Z
High Z
High Z
DOUT
High Z
DOUT
DIN
High Z
High Z
High Z
High Z
DOUT
DOUT
High Z
DIN
ICCSB, ICCSB1
Chip De-selected
(Power Down)
X
X
X
ICCSB, ICCSB1
X
H
X
X
H
X
ICCSB, ICCSB1
Output Disabled
Read
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
L
L
H
H
H
L
L
H
L
L
H
L
L
Write
X
H
L
L
X
DIN
H
DIN
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
R0201-BH616UV8010
Revision 1.0
Jul. 2005
2
BSI
BH616UV8010
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
PARAMETER
RATING
-0.5(2) to 4.6V
-40 to +125
UNITS
RANG
VCC
Terminal Voltage with
Respect to GND
Temperature Under
Bias
VTERM
V
Commercial
Industrial
1.65V ~ 3.6V
1.65V ~ 3.6V
TBIAS
OC
-25OC to + 85OC
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
-60 to +150
OC
W
1.0
20
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns
n DC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
PARAMETER
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
NAME
VCC
1.65
--
3.6
V
0.4
0.8
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Leakage Current
-0.3(2)
--
--
--
V
V
1.4
2.0
VCC+0.3(3)
VIN = 0V to VCC
,
--
--
--
1
uA
CE1 = VIH or CE2 = VIL
VI/O = 0V to VCC,
ILO
Output Leakage Current
CE1 = VIH or CE2 = VIL or OE = VIH or
UB = LB = VIH
--
1
uA
VCC = Max, IOL = 0.2mA
0.2
0.4
VCC=1.8V
VOL
VOH
ICC
Output Low Voltage
Output High Voltage
--
--
V
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.1mA
VCC = Min, IOH = -1.0mA
CE1 = VIL and CE2 = VIH,
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC-0.2
2.4
--
V
4.5
5.0
1.0
1.5
7
Operating Power Supply
Current
(4)
--
--
--
--
mA
mA
mA
uA
IDQ = 0mA, f = FMAX
10
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
1.5
2.0
0.5
1.0
12
Operating Power Supply
Current
ICC1
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
ICCSB
Standby Current – TTL
--
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
2.5
2.5
(5)
ICCSB1
Standby Current – CMOS
15
1. Typical characteristics are at TA=25OC.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICCSB1(MAX.) is 10uA/13uA at VCC=1.8V/3.6V and TA=0OC ~ 70OC.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
3
BSI
BH616UV8010
n DATA RETENTION CHARACTERISTICS (TA = -25OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VDR
VCC for Data Retention
1.0
--
--
V
0.5
2.5
3.0
12
VCC=1.0V
VCC=2.0V
(3)
ICCDR
Data Retention Current
--
0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
1. TA=25OC.
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
tRC
2. tRC = Read Cycle Time.
3. ICCDR(MAX.) is 2.5uA /10uA at VCC=1.0V/2.0V and TA=0OC ~ 70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1
tCHZ2, tBDO, tOHZ, tWHZ, tOW
,
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
CHANGE :
STATE UNKNOW
1 TTL
90%
90%
Output
10%
10%
GND
(1)
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
®
¬
®
¬
CL
DOES NOT
APPLY
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
4
BSI
BH616UV8010
n AC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
PARANETER
DESCRIPTION
Read Cycle Time
UNITS
NAME
MIN.
70
--
TYP.
--
MAX.
--
tAVAX
tAVQX
tE1LQV
tE2LQV
tBLQV
tGLQV
tE1LQX
tE2LQX
tBLQX
tGLQX
tE1HQZ
tE2HQZ
tBHQZ
tGHQZ
tAVQX
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
--
70
70
70
70
30
--
Chip Select Access Time
(CE1)
tACS1
tACS2
tBA
--
--
Chip Select Access Time
(CE2)
--
--
Data Byte Control Access Time
(LB, UB)
--
--
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE1)
tCLZ1
tCLZ2
tBE
10
10
10
5
--
Chip Select to Output Low Z
(CE2)
--
--
Data Byte Control to Output Low Z
(LB, UB)
--
--
tOLZ
tCHZ1
tCHZ2
tBDO
tOHZ
tOH
Output Enable to Output Low Z
Chip Select to Output High Z
--
--
(CE1)
--
--
25
25
25
25
--
Chip Select to Output High Z
(CE2)
--
--
Data Byte Control to Output High Z
(LB, UB)
--
--
Output Enable to Output High Z
Data Hold from Address Change
--
--
10
--
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
DOUT
tAA
tOH
tOH
R0201-BH616UV8010
Revision 1.0
5
Jul.
2005
BSI
BH616UV8010
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
(6)
tACS2
(5, 6)
tCHZ
(5,6)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tOHZ
tCHZ
(5)
(1,5)
tCLZ1
CE2
tACS2
(5)
(2,5)
tCLZ2
tCHZ2
tBA
tBE
LB, UB
DOUT
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
6
BSI
BH616UV8010
n AC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
PARANETER
DESCRIPTION
UNITS
NAME
MIN.
70
0
TYP.
--
MAX.
--
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
--
--
tAW
tCW
tBW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
50
50
50
35
0
--
--
Chip Select to End of Write
--
--
Data Byte Control to End of Write
(LB, UB)
--
--
Write Pulse Width
--
--
Write Recovery Time
(CE1, WE)
(CE2)
--
--
Write Recovery Time
0
--
--
Write to Output High Z
--
--
20
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
30
0
--
--
--
tOHZ
tOW
--
--
25
--
5
--
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
(11)
tCW
(5)
(5)
CE1
CE2
tCW
(3)
tWR2
tBW
LB, UB
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
R0201-BH616UV8010
Revision 1.0
7
Jul.
2005
BSI
BH616UV8010
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
(11)
tCW
(5)
CE1
CE2
(5)
(11)
tCW
tBW
(3)
tWR
(12)
LB, UB
WE
tAW
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH616UV8010
Revision 1.0
Jul. 2005
8
BSI
BH616UV8010
n ORDERING INFORMATION
BH616UV8010 X
X
Z Y Y
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
GRADE
I: -25oC ~ +85oC
PACKAGE
T: TSOP 1-48
A: BGA-48-0608
D:DICE
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
n
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BH616UV8010
Revision 1.0
Jul. 2005
9
BSI
BH616UV8010
PACKAGE DIMENSIONS
TSOP1-48 Pin (12mm x 20mm)
R0201-BH616UV8010
Revision 1.0
10
Jul.
2005
BSI
BH616UV8010
n Revision History
Revision No.
1.0
History
Draft Date
July 15,2005
Remark
Initial
Initial Production Version
R0201-BH616UV8010
Revision 1.0
Jul. 2005
11
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