BS616LV2019ECG55 [BSI]
Very Low Power CMOS SRAM 256K X 16 bit; 超低功耗CMOS SRAM 256K ×16位型号: | BS616LV2019ECG55 |
厂家: | BRILLIANCE SEMICONDUCTOR |
描述: | Very Low Power CMOS SRAM 256K X 16 bit |
文件: | 总11页 (文件大小:209K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Very Low Power CMOS SRAM
256K X 16 bit
BS616LV4017
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
ŸWide VCC operation voltage : 2.4V ~ 5.5V
n DESCRIPTION
The BS616LV4017 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.25uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
ŸVery low power consumption :
VCC = 3.0V
VCC = 5.0V
Operation current : 27mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.25uA (Typ.)at 25OC
Operation current : 65mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25OC
ŸHigh speed access time :
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
-55
-70
55ns(Max.) at VCC=3.0~5.5V
70ns(Max.) at VCC=2.7~5.5V
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS616LV4017 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV4017 is available in DICE form, JEDEC standard
44-pin TSOP II and 48-ball BGA package.
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=5.0V
10MHz
VCC=3.0V
10MHz
VCC=5.0V VCC=3.0V
1MHz
9mA
fMax.
1MHz
fMax.
BS616LV4017DC
BS616LV4017AC
BS616LV4017EC
BS616LV4017AI
BS616LV4017EI
DICE
Commercial
10uA
20uA
2.0uA
4.0uA
39mA
40mA
63mA
1.5mA
14mA
15mA
26mA
BGA-48-0608
TSOP II-44
BGA-48-0608
TSOP II-44
+0OC to +70OC
Industrial
10mA
65mA
2mA
27mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
A5
A6
A7
OE
UB
LB
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A12
A11
A10
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
A9
A8
A5
A6
A7
A4
A3
Address
Input
1024
Memory Array
10
9
Row
Decoder
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV4017EC
BS616LV4017EI
Buffer
1024 x 4096
4096
DQ0
Data
Input
Buffer
16
16
Column I/O
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
16
1
2
3
4
5
6
.
16
Data
Output
Buffer
.
.
256
A
B
C
D
E
F
LB
D8
OE
A0
A1
A2
NC
D0
Column Decoder
DQ15
UB
D10
D11
D12
D13
NC
A3
A5
A4
A6
CE
D1
8
CE
WE
OE
UB
LB
D9
D2
Address Input Buffer
Control
VSS
VCC
D14
D15
NC
A17
NC
A14
A12
A9
A7
D3
VCC
VSS
D6
A13 A14 A15 A16 A17 A0 A1 A2
A16
A15
A13
A10
D4
VCC
VSS
D5
G
H
WE
A11
D7
A8
NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4017
Revision 1.3
May. 2006
1
BS616LV4017
n PIN DESCRIPTIONS
Name
Function
These 18 address inputs select one of the 262,144 x 16-bit in the RAM
A0-A17 Address Input
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
There 16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
X
H
L
UB
X
H
X
L
IO0~IO7
High Z
High Z
High Z
High Z
DOUT
IO8~IO15
High Z
High Z
High Z
High Z
DOUT
VCC CURRENT
ICCSB, ICCSB1
Chip De-selected
(Power Down)
X
X
X
ICCSB, ICCSB1
L
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Output Disabled
Read
L
H
H
X
L
L
L
L
H
L
L
H
L
L
High Z
DOUT
DOUT
H
L
High Z
DIN
L
DIN
Write
X
H
L
L
X
DIN
H
DIN
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
Revision 1.3
R0201-BS616LV4017
2
May.
2006
BS616LV4017
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
-0.5(2) to 7.0
-40 to +125
-60 to +150
1.0
UNITS
V
RANG
VCC
Terminal Voltage with
Respect to GND
Commercial
Industrial
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
NAME
Power Supply
2.4
--
5.5
V
VCC
Input Low Voltage
-0.5(2)
2.2
--
--
--
--
--
--
--
--
--
--
0.8
V
V
VIL
VIH
IIL
Input High Voltage
VCC+0.3(3)
VIN = 0V to VCC
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
1
1
uA
uA
V
CE= VIH
VI/O = 0V to VCC
,
--
ILO
CE= VIH or OE = VIH
VCC = Max, IOL = 2.0mA
--
0.4
--
VOL
VOH
VCC = Min, IOH = -1.0mA
CE = VIL,
2.4
--
V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
27
65
2
Operating Power Supply
Current
(5)
ICC
mA
mA
mA
uA
(4)
IIO = 0mA, f = FMAX
CE = VIL,
Operating Power Supply
Current
--
ICC1
10
1.0
2.0
4.0
20
IIO = 0mA, f = 1MHz
CE = VIH,
IIO = 0mA
Standby Current – TTL
--
ICCSB
0.25
1.5
CE≧VCC-0.2V
(6)
Standby Current – CMOS
--
ICCSB1
VIN≧VCC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 26mA/63mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 2.0uA/10uA at VCC=3.0V/5.0V and TA=70OC.
Revision 1.3
May. 2006
R0201-BS616LV4017
3
BS616LV4017
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
TEST CONDITIONS
CE≧VCC-0.2V
MIN.
TYP. (1)
MAX.
UNITS
VCC for Data Retention
1.5
--
--
V
VIN≧VCC-0.2V or VIN≦0.2V
CE≧VCC-0.2V
(3)
Data Retention Current
--
0
0.1
--
1.5
--
uA
ns
ns
ICCDR
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
tCDR
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
tR
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 1.0uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
DR≧1.5V
V
VCC
VCC
VCC
CE
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
DOES NOT
APPLY
(1)
®
¬
®
¬
CL
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
Revision 1.3
R0201-BS616LV4017
4
May.
2006
BS616LV4017
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC=3.0~5.5V) (VCC=2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
tAVAX
tAVQX
tELQV
tBLQV
tGLQV
tELQX
tBLQX
tGLQX
tEHQZ
tBHQZ
tGHQZ
tAVQX
tRC
tAA
tACS
tBA
Read Cycle Time
55
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
(CE)
--
--
Data Byte Control Access Time
(LB, UB)
--
--
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE)
tCLZ
tBE
10
10
5
10
10
5
Data Byte Control to Output Low Z (LB, UB)
Output Enable to Output Low Z
--
--
tOLZ
tCHZ
tBDO
tOHZ
tOH
--
--
Chip Select to Output High Z
(CE)
--
30
30
25
--
--
35
35
30
--
Data Byte Control to Output High Z (LB, UB)
--
--
Output Enable to Output High Z
Data Hold from Address Change
--
--
10
10
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
Revision 1.3
May. 2006
R0201-BS616LV4017
5
BS616LV4017
READ CYCLE 2 (1,3,4)
CE
tACS
tBA
tBE
LB, UB
DOUT
(5)
tCHZ
tBDO
(5)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
CE
tOH
tOE
tOLZ
(5)
tOHZ
tCHZ
(5)
(1,5)
tCLZ
tBA
tBE
LB, UB
DOUT
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 1.3
May. 2006
R0201-BS616LV4017
6
BS616LV4017
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC=3.0~5.5V) (VCC=2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
Write Cycle Time
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
tAW
tCW
tBW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
Chip Select to End of Write
55
55
25
30
0
--
70
70
30
35
0
--
(CE)
--
--
Data Byte Control to End of Write
(LB, UB)
--
--
Write Pulse Width
--
--
Write Recovery Time
(CE, WE)
--
--
Write to Output High Z
--
25
--
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
25
0
30
0
--
--
tOHZ
tOW
--
25
--
--
30
--
5
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
CE
tBW
LB, UB
(3)
tWR2
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 1.3
May. 2006
R0201-BS616LV4017
7
BS616LV4017
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
CE
tBW
(12)
LB, UB
WE
(3)
tAW
tWR2
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low to the end of write.
12.The change of Read/Write cycle must accompany with CE or address toggled.
Revision 1.3
R0201-BS616LV4017
8
May.
2006
BS616LV4017
n ORDERING INFORMATION
BS616LV4017
X
X
Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
A: BGA-48-0608
E: TSOP II-44
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
TSOP II-44
Revision 1.3
May. 2006
R0201-BS616LV4017
9
BS616LV4017
n PACKAGE DIMENSIONS (continued)
NOTES
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8mm)
Revision 1.3
May. 2006
R0201-BS616LV4017
10
BS616LV4017
n Revision History
Revision No.
1.2
History
Draft Date
Remark
Add Icc1 characteristic parameter
Improve Iccsb1 spec.
Jan. 13, 2006
I-grade from 60uA to 20uA at 5.0V
10uA to 4.0uA at 3.0V
C-grade from 30uA to 10uA at 5.0V
5.0uA to 2.0uA at 3.0V
1.3
Change I-grade operation temperature range
May. 25, 2006
- from –25OC to –40OC
Revision 1.3
R0201-BS616LV4017
11
May.
2006
相关型号:
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