BS616LV8017EC-55 [BSI]
Very Low Power/Voltage CMOS SRAM 512K X 16 bit; 非常低的功率/电压CMOS SRAM 512K ×16位
| 型号： | BS616LV8017EC-55 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 512K X 16 bit |
| 文件： | 总9页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Single CE Pin)
BSI
BS616LV8017
FEATURES
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.) CMOS standby current
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV8017 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
• High speed access time :
-55
-70
55ns
70ns
The BS616LV8017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8017 is available in 48B BGA and 44L TSOP2 packages.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
Vcc=5V
70ns
Vcc=3V
70ns
55ns : 3.0~5.5V
70ns : 2.7~5.5V
Vcc=3V
Vcc=5V
BS616LV8017EC
BS616LV8017FC
BS616LV8017EI
BS616LV8017FI
TSOP2-44
BGA-48-0912
TSOP2-44
+0O C to +70OC 2.4V ~ 5.5V
-40OC to +85OC 2.4V ~ 5.5V
55 / 70
55 / 70
5uA
55uA
24mA
25mA
60mA
10uA
110uA
61mA
BGA-48-0912
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
DQ0
DQ1
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
Vss
A4
A3
A2
A1
A0
Address
Input
22
2048
9
DQ2
DQ3
Vcc
A17
A16
Row
Memory Array
2048 x 4096
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV8017EC
BS616LV8017EI
Buffer
Vss
Vcc
A15
A14
A13
A12
Decoder
DQ4
DQ5
DQ6
DQ7
WE
A18
A17
A16
A15
A14
DQ11
DQ10
DQ9
DQ8
A8
4096
A9
A10
A11
A12
A13
Data
Input
16
16
Column I/O
D0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
6
16
5
A2
256
Data
Output
16
LB
OE
A0
A1
NC
A
B
C
D
E
F
Buffer
Column Decoder
D15
D8
D9
UB
A3
A5
A4
A6
A7
CE
D1
D3
D0
D2
D10
D11
16
CE
V
A17
V
CC
SS
SS
CC
WE
OE
UB
Control
Address Input Buffer
A16
A 15
A13
A10
D4
D5
VSS
A14
A12
A9
V
V
D12
D13
D6
D14
D15
A18
LB
A11 A10 A9 A8 A7
A6 A5 A18
WE
A11
D7
N.C
A8
Vcc
Vss
G
H
NC
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
R0201-BS616LV8017
1
Jan.
2004
BSI
PIN DESCRIPTIONS
Name
BS616LV8017
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Vss
Power Supply
Ground
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
X
UB
D0~D7
High Z
High Z
High Z
High Z
Dout
D8~D15
Vcc CURRENT
Not selected
(Power Down)
X
H
H
X
L
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
ICCSB , ICCSB1
X
X
X
H
ICCSB , ICCSB1
ICC
L
L
X
H
X
H
H
X
Output Disabled
Read
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
H
L
L
H
L
L
High Z
Dout
H
L
L
Din
Write
L
L
X
H
L
L
X
Din
H
Din
X
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
V
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
VTERM
Commercial
Industrial
0O C to +70O C
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
BIAS
T
T
-40O C to +85O C
O C
STG
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
W
PT
DC Output Current
20
mA
IOUT
SYMBOL
IN
PARAMETER CONDITIONS MAX.
UNIT
Input
IN
=0V
C
V
10
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance
Input/Output
Capacitance
DQ
C
I/O
=0V
V
12
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.1
Jan. 2004
R0201-BS616LV8017
2
BSI
BS616LV8017
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
(1)
UNITS
V
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
0.8
NAME
Vcc=3.0V
Vcc=5.0V
Guaranteed Input Low
Voltage(3)
IL
V
-0.5
--
Vcc=3.0V
Vcc=5.0V
2.0
2.2
Guaranteed Input High
Voltage(3)
Vcc+0.
3
IH
V
--
--
--
V
1
1
IN
IL
I
Input Leakage Current Vcc = Max, V = 0V to Vcc
--
--
--
uA
IH
IH
,
,
Vcc = Max, CE = V or OE = V
Output Leakage Current
LO
I
uA
V
I/O
V
= 0V to Vcc
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
0.4
--
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
--
--
OH
OH
V
Vcc = Min, I = -1mA
2.4
V
(4)
70ns
70ns
25
61
1
--
--
--
--
--
--
--
Operating Power Supply
Current
DQ= 0mA
IL
CE = V ,I
CC
I
mA
mA
,F = Fmax(2)
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
--
Standby Current TTL
-
IH
DQ
CCSB
I
CE = V ,I = 0mA
2
--
(5)
CCSB1
10
1.5
CE
IN
V
Vcc -0.2V,
Vcc- 0.2V or V
≧
Standby Current CMOS
-
I
uA
0.2V
≦
IN
≧
Vcc=5.0V
110
--
8.0
1. Typical characteristics are at TA = 25oC.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc_Max. is 31mA(@3.0V) / 76mA(@5.0V) under 55ns operation.
5.IccsB1 is 5uA/55uA at Vcc=3.0V/5.0V and TA=70oC.
2. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE ≧ Vcc - 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE ≧ Vcc - 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
0.8
2.5
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
3. IccDR(Max.) is 1.3uA at TA=70OC.
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE
t
R
t
CDR
≥
CE
Vcc - 0.2V
VIH
VIH
Revision 2.1
R0201-BS616LV8017
3
Jan.
2004
BSI
BS616LV8017
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
Vcc = 2.7~5.5V
MIN. TYP. MAX.
CYCLE TIME : 55ns
PARAMETER
DESCRIPTION
Read Cycle Time
Vcc = 3.0~5.5V
UNIT
NAME
MIN. TYP. MAX.
tAVAX
tRC
70
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tBA
tAA
Address Access Time
70
70
35
35
--
55
55
30
30
--
tACS
(CE)
Chip Select Access Time
(1)
tBA
(LB,UB)
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
tGLQV
tELQX
tBE
tOE
tCLZ
tBE
(CE)
(LB,UB)
--
--
tGLQX
tEHQZ
tBDO
tGHQZ
tOLZ
tCHZ
tBDO
tOHZ
5
--
5
--
(CE)
--
--
--
35
35
30
--
--
--
30
30
25
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
t
t
AXOX
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
Revision 2.1
Jan. 2004
R0201-BS616LV8017
4
BSI
BS616LV8017
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
D OUT
(5)
CHZ
t
BDO
t
BE
t
(5)
CLZ
t
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
CE
t
OH
t
OE
t
OLZ
(5)
t
ACS
t
OHZ
(1,5)
CHZ
(5)
t
CLZ
t
LB,UB
t
BE
t
BDO
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL .
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
Revision 2.1
Jan. 2004
R0201-BS616LV8017
5
BSI
BS616LV8017
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
Vcc = 2.7~5.5V
MIN. TYP. MAX.
CYCLE TIME : 55ns
Vcc = 3.0~5.5V
MIN. TYP. MAX.
PARAMETER
DESCRIPTION
Write Cycle Time
UNIT
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWC
tCW
tAS
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
70
35
0
--
55
30
0
--
--
--
Write recovery Time
(CE,WE)
--
--
(1)
Date Byte Control to End of Write
Write to Output in High Z
tBW
(LB,UB) 30
--
25
--
--
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHZ
tDW
tDH
--
30
0
30
--
25
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
25
0
--
--
tOHZ
--
30
--
25
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
(5)
CE
t
BW
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.1
Jan. 2004
R0201-BS616LV8017
6
BSI
BS616LV8017
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
WHZ
t
OW
(7)
(8)
t
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.1
R0201-BS616LV8017
7
Jan.
2004
BSI
BS616LV8017
ORDERING INFORMATION
BS616LV8017 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
F :BGA-48-0912
E :TSOP2-44
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
N
D
E
D1
E1
e
D1
48
12.0
9.0
5.25
3.75
0.75
3.375
SOLDER BALL 0.35±0.05
VIEW A
48 mini-BGA (9mm x 12mm)
Revision 2.1
Jan. 2004
R0201-BS616LV8017
8
BSI
BS616LV8017
PACKAGE DIMENSIONS (continued)
TSOP2-44
Revision 2.1
R0201-BS616LV8017
9
Jan.
2004
相关型号：
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