BS616UV1010AI [BSI]
Ultra Low Power/Voltage CMOS SRAM 64K X 16 bit; 超低功率/电压CMOS SRAM 64K ×16位
| 型号： | BS616UV1010AI |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 64K X 16 bit |
| 文件： | 总10页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
64K X 16 bit
BSI
BS616UV1010
DESCRIPTION
FEATURES
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
The BS616UV1010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.01uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
Vcc = 2.0V
C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
C-grade : 15mA (Max.) operating current
I- grade : 20mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 3.0V
• High speed access time :
-15
150ns (Max.) at Vcc = 3.0V
The BS616UV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin mini-BGA.
• Input levels are CMOS-compatible
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
Vcc=3.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
BS616UV1010EC
BS616UV1010AC
TSOP2-44
+0O C to +70O
-40 O C to +85O
C
C
1.8V ~ 3.6V
1.8V ~ 3.6V
150
0.5uA
1.5uA
0.3uA
15mA
20mA
10mA
BGA-48-0608
BS616UV1010EI
BS616UV1010AI
TSOP2-44
BGA-48-0608
150
1uA
15mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
A6
A7
OE
UB
LB
2
A3
3
A2
4
A1
5
A8
A0
6
CE
A13
A15
7
DQ0
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
Address
8
DQ1
18
512
9
DQ2
A14
A12
A7
Input
10
Row
DQ3
BS616UV1010EC
Memory Array
512 x 2048
11
VCC
12
BS616UV1010EI
GND
Buffer
13
Decoder
DQ4
14
A6
A5
A4
DQ5
15
DQ6
16
DQ7
17
WE
18
A15
2048
A8
19
A14
A9
Data
20
A13
A10
16
16
16
Column I/O
21
Input
A12
A11
DQ0
22
NC
NC
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
16
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
NC
IO0
IO2
VCC
VSS
IO6
IO7
NC
Output
Buffer
Column Decoder
DQ15
IO8
CE
14
CE
WE
OE
UB
IO9
IO10
IO11
IO12
IO13
NC
A5
A6
IO1
IO3
IO4
IO5
WE
A11
Control
Address Input Buffer
VSS
VCC
IO14
IO15
NC
NC
NC
A14
A12
A9
A7
LB
A11 A9 A3 A2 A1
A0 A10
NC
A15
A13
A10
Vcc
Gnd
G
H
A8
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS616UV1010
1
BSI
BS616UV1010
PIN DESCRIPTIONS
Name
Function
A0-A15 Address Input
These 16 address input select one of the 65,536 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
X
X
High Z
High Z
I
CCSB, ICCSB1
(Power Down)
Output Disabled
L
H
H
X
L
H
L
L
H
L
X
L
L
H
L
L
High Z
Dout
High Z
Dout
Din
High Z
Dout
Dout
High Z
Din
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Read
L
L
H
L
L
Write
X
X
Din
Din
X
H
Revision 2.2
April 2001
R0201-BS616UV1010
2
BSI
BS616UV1010
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
-0.5 to
V
0O C to +70O
-40O C to +85O
C
1.8V ~ 3.6V
1.8V ~ 3.6V
TERM
BIAS
STG
T
V
T
T
P
Respect to GND
Vcc+0.5
Commercial
Industrial
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX. UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
IN
IN
C
V
=0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.(1) MAX.
NAME
VIL
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Guaranteed Input Low
0.6
-0.5
--
V
Voltage(2)
0.8
Guaranteed Input High
Voltage(2)
1.4
2.0
--
VIH
IIL
--
--
Vcc+0.2
V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
1
1
uA
IH
IH
Vcc = Max, CE = V , or OE = V ,
IOL
Output Leakage Current
--
--
uA
V
I/O = 0V to Vcc
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 1mA
--
--
--
0.4
--
V
V
1.6
2.4
--
--
--
--
--
--
Vcc = Min, IOH = -0.5mA
--
--
10
15
Operating Power Supply
Current
ICC
CE = VIL, IDQ = 0mA, F = Fmax(3)
mA
mA
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
--
0.5
1
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
--
0.01
0.02
0.3
0.5
CE Њ Vcc-0.2V,
ICCSB1
Standby Current-CMOS
uA
V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE
Vcc - 0.2V
Њ
Њ
VDR
Vcc for Data Retention
1.5
--
0.01
--
V
IN
IN
V
Vcc - 0.2V or V
0.2V
Љ
Љ
CE
Vcc -0.2V
Vcc - 0.2V or V
Њ
Њ
ICCDR
Data Retention Current
--
0
0.2
uA
IN
IN
V
0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
Revision 2.2
April 2001
R0201-BS616UV1010
3
BSI
BS616UV1010
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1333
1333
5PF
MAY CHANGE
FROM L TO H
WILL BE
2V
2V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
100PF
DON T CARE:
CHANGE :
STATE
INCLUDING
INCLUDING
ANY CHANGE
PERMITTED
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
BS616UV1010-15
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
UNIT
NAME
Read Cycle Time
150
--
--
--
--
--
--
--
--
--
--
--
--
150
150
150
80
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
tACS
tBA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
tOH
tAVAX
tAVQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tAXOX
Address Access Time
--
--
Chip Select Access Time
(CE)
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
--
--
(CE)
15
15
15
0
(LB,UB)
--
--
(CE)
45
40
40
(LB,UB)
0
0
Output Disable to Output Address Change
15
--
--
ns
Revision 2.2
April 2001
R0201-BS616UV1010
4
BSI
BS616UV1010
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
CHZ
t
t
BE
t
BDO
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
(1,5)
(5) t ACS
CLZ
t
OHZ
t
t
CHZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS616UV1010
5
BSI
BS616UV1010
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
WRITE CYCLE
JEDEC
BS616UV1010-15
MIN. TYP. MAX.
PARAMETER
PARAMETER
NAME
DESCRIPTION
UNIT
NAME
tWC
tAVAX
Write Cycle Time
150
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
40
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWLQZ
tDVWH
tWHDX
tGHQZ
tCW
tAS
tAW
tWP
tWR
tBW
tWHZ
tDW
tDH
Chip Select to End of Write
Address Setup Time
150
0
Address Valid to End of Write
Write Pulse Width
150
80
0
Write recovery Time
(CE,WE)
(LB,UB)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
70
0
40
0
tOHZ
0
40
tWHOX
tOW
End of Write to Output Active
5
--
--
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
BW
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS616UV1010
6
BSI
BS616UV1010
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
t
WHZ
(7)
(8)
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
12. The change of Read/Write cycle must accompany with CE or address toggled.
Revision 2.2
April 2001
R0201-BS616UV1010
7
BSI
BS616UV1010
ORDERING INFORMATION
BS616UV1010 X X -- Y Y
SPEED
15: 150ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
E: TSOP II - 44 PIN
A: BGA-48 PIN(6x8mm)
PACKAGE DIMENSIONS
TSOP2-44
Revision 2.2
April 2001
R0201-BS616UV1010
8
BSI
BS616UV1010
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 2.2
April 2001
R0201-BS616UV1010
9
BSI
REVISION HISTORY
BS616UV1010
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS616UV1010
10
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